Discussion:
[PATCH v1 0/9]Encoder Architecture Changes (Primarily AVC)
(too old to reply)
Pengfei Qu
2017-01-13 09:24:03 UTC
Permalink
Encoder architecture restructuring for H.264 (with some impact to HEVC now) on HSW+
* Improvements to the shaders
* Improvements to the B frame efficiency
* Improvements to the low bit rate mode
* Improved features in two stage VME/PAK pipeline

v1:
Reduce the patch number and re org for VME and MFX related patches.
Patch re org for VME pipeline
Patch re org for MFX pipeline
keep assert for internal logic and replace assert for input validation function.
Remove unnecessary comments and enum value.
Use the 64bit version OUT_BCS_RELOC64.
Move kernel binary into header file.
use misc parameter from encoder_context structure.


Pengfe (9):
ENC: move gpe related function into src/i965_gpe_utils.h/c
ENC: add common structure for AVC/HEVC encoder
ENC: add const data/table for AVC encoder
ENC: add AVC kernel binary on SKL
ENC: add AVC common structure and functions
ENC: add kernel related structure and define for AVC
ENC: add VME pipeline for AVC encoder
ENC: add MFX pipeline for AVC encoder
ENC:support more quality level and switch to new AVC encoder solution
on SKL

src/Makefile.am | 10 +
src/gen9_avc_const_def.c | 1090 ++++
src/gen9_avc_const_def.h | 115 +
src/gen9_avc_encoder.c | 7630 +++++++++++++++++++++++++
src/gen9_avc_encoder.h | 2339 ++++++++
src/gen9_avc_encoder_kernels.h | 12078 +++++++++++++++++++++++++++++++++++++++
src/gen9_vp9_encoder.c | 154 +-
src/gen9_vp9_encoder.h | 10 -
src/i965_avc_encoder_common.c | 319 ++
src/i965_avc_encoder_common.h | 305 +
src/i965_defines.h | 3 +
src/i965_drv_video.c | 8 +-
src/i965_drv_video.h | 2 +
src/i965_encoder.c | 52 +-
src/i965_encoder_api.h | 47 +
src/i965_encoder_common.c | 124 +
src/i965_encoder_common.h | 541 ++
src/i965_gpe_utils.c | 282 +
src/i965_gpe_utils.h | 86 +
19 files changed, 25027 insertions(+), 168 deletions(-)
create mode 100755 src/gen9_avc_const_def.c
create mode 100755 src/gen9_avc_const_def.h
create mode 100755 src/gen9_avc_encoder.c
create mode 100755 src/gen9_avc_encoder.h
create mode 100755 src/gen9_avc_encoder_kernels.h
create mode 100755 src/i965_avc_encoder_common.c
create mode 100755 src/i965_avc_encoder_common.h
create mode 100755 src/i965_encoder_api.h
create mode 100755 src/i965_encoder_common.c
create mode 100755 src/i965_encoder_common.h
--
2.7.4
Pengfei Qu
2017-01-13 09:24:04 UTC
Permalink
v1:
add align version for obj surface conversion to gpe surface
remove comments and enum value

Signed-off-by: Pengfei Qu <***@intel.com>
Reviewed-by: Sean V Kelley<***@posteo.de>
---
src/gen9_vp9_encoder.c | 154 ++-------------------------
src/gen9_vp9_encoder.h | 10 --
src/i965_defines.h | 3 +
src/i965_gpe_utils.c | 282 +++++++++++++++++++++++++++++++++++++++++++++++++
src/i965_gpe_utils.h | 86 +++++++++++++++
5 files changed, 377 insertions(+), 158 deletions(-)

diff --git a/src/gen9_vp9_encoder.c b/src/gen9_vp9_encoder.c
index 05d86da..32ed729 100644
--- a/src/gen9_vp9_encoder.c
+++ b/src/gen9_vp9_encoder.c
@@ -58,7 +58,6 @@
#define BRC_KERNEL_AVBR 0x0040
#define BRC_KERNEL_CQL 0x0080

-#define DEFAULT_MOCS 0x02
#define VP9_PIC_STATE_BUFFER_SIZE 192

typedef struct _intel_kernel_header_
@@ -842,7 +841,7 @@ gen9_vp9_free_resources(struct gen9_encoder_context_vp9 *vme_context)

static void
gen9_init_media_object_walker_parameter(struct intel_encoder_context *encoder_context,
- struct vp9_encoder_kernel_walker_parameter *kernel_walker_param,
+ struct gpe_encoder_kernel_walker_parameter *kernel_walker_param,
struct gpe_media_object_walker_parameter *walker_param)
{
memset(walker_param, 0, sizeof(*walker_param));
@@ -924,147 +923,6 @@ gen9_init_media_object_walker_parameter(struct intel_encoder_context *encoder_co
}

static void
-gen9_add_2d_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct object_surface *obj_surface,
- int is_uv_surface,
- int is_media_block_rw,
- unsigned int format,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
- gpe_surface.gpe_resource = &gpe_resource;
- gpe_surface.is_2d_surface = 1;
- gpe_surface.is_uv_surface = !!is_uv_surface;
- gpe_surface.is_media_block_rw = !!is_media_block_rw;
-
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.format = format;
-
- gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
- i965_free_gpe_resource(&gpe_resource);
-}
-
-static void
-gen9_add_adv_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct object_surface *obj_surface,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
- gpe_surface.gpe_resource = &gpe_resource;
- gpe_surface.is_adv_surface = 1;
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.v_direction = 2;
-
- gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
- i965_free_gpe_resource(&gpe_resource);
-}
-
-static void
-gen9_add_buffer_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct i965_gpe_resource *gpe_buffer,
- int is_raw_buffer,
- unsigned int size,
- unsigned int offset,
- int index)
-{
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- gpe_surface.gpe_resource = gpe_buffer;
- gpe_surface.is_buffer = 1;
- gpe_surface.is_raw_buffer = !!is_raw_buffer;
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.size = size;
- gpe_surface.offset = offset;
-
- gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
-}
-
-static void
-gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct i965_gpe_resource *gpe_buffer,
- int is_media_block_rw,
- unsigned int format,
- int index)
-{
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- gpe_surface.gpe_resource = gpe_buffer;
- gpe_surface.is_2d_surface = 1;
- gpe_surface.is_media_block_rw = !!is_media_block_rw;
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.format = format;
-
- gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
-}
-
-static void
-gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- dri_bo *bo,
- int is_raw_buffer,
- unsigned int size,
- unsigned int offset,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
-
- i965_dri_object_to_buffer_gpe_resource(&gpe_resource, bo);
- gen9_add_buffer_gpe_surface(ctx,
- gpe_context,
- &gpe_resource,
- is_raw_buffer,
- size,
- offset,
- index);
-
- i965_free_gpe_resource(&gpe_resource);
-}
-
-/*
-static void
-gen9_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- dri_bo *bo,
- unsigned int width,
- unsigned int height,
- unsigned int pitch,
- int is_media_block_rw,
- unsigned int format,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
-
- i965_dri_object_to_2d_gpe_resource(&gpe_resource, bo, width, height, pitch);
- gen9_add_buffer_2d_gpe_surface(ctx,
- gpe_context,
- &gpe_resource,
- is_media_block_rw,
- format,
- index);
-
- i965_free_gpe_resource(&gpe_resource);
-}
-*/
-
-static void
gen9_run_kernel_media_object(VADriverContextP ctx,
struct intel_encoder_context *encoder_context,
struct i965_gpe_context *gpe_context,
@@ -1491,7 +1349,7 @@ gen9_vp9_brc_intra_dist_kernel(VADriverContextP ctx,
VAEncPictureParameterBufferVP9 *pic_param;
struct gen9_vp9_state *vp9_state;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;

vp9_state = (struct gen9_vp9_state *) encoder_context->enc_priv_state;

@@ -2331,7 +2189,7 @@ gen9_vp9_me_kernel(VADriverContextP ctx,
struct gen9_vp9_me_curbe_param me_curbe_param;
struct gen9_vp9_state *vp9_state;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;

vp9_state = (struct gen9_vp9_state *) encoder_context->enc_priv_state;
if (!vp9_state || !vp9_state->pic_param)
@@ -2471,7 +2329,7 @@ gen9_vp9_scaling_kernel(VADriverContextP ctx,
struct gen9_vp9_state *vp9_state;
VAEncPictureParameterBufferVP9 *pic_param;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
struct object_surface *obj_surface;
struct object_surface *input_surface, *output_surface;
struct gen9_surface_vp9 *vp9_priv_surface;
@@ -2738,7 +2596,7 @@ gen9_vp9_dys_kernel(VADriverContextP ctx,
struct gen9_vp9_dys_curbe_param curbe_param;
struct gen9_vp9_dys_surface_param surface_param;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
unsigned int resolution_x, resolution_y;

media_function = VP9_MEDIA_STATE_DYS;
@@ -3526,7 +3384,7 @@ gen9_vp9_mbenc_kernel(VADriverContextP ctx,
struct gen9_encoder_context_vp9 *vme_context = encoder_context->vme_context;
struct i965_gpe_context *gpe_context, *tx_gpe_context;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
unsigned int resolution_x, resolution_y;
struct gen9_vp9_state *vp9_state;
VAEncPictureParameterBufferVP9 *pic_param;
diff --git a/src/gen9_vp9_encoder.h b/src/gen9_vp9_encoder.h
index 972e2ad..c61a796 100644
--- a/src/gen9_vp9_encoder.h
+++ b/src/gen9_vp9_encoder.h
@@ -83,16 +83,6 @@ struct vp9_encoder_kernel_parameter
unsigned int sampler_size;
};

-struct vp9_encoder_kernel_walker_parameter
-{
- unsigned int walker_degree;
- unsigned int use_scoreboard;
- unsigned int scoreboard_mask;
- unsigned int no_dependency;
- unsigned int resolution_x;
- unsigned int resolution_y;
-};
-
struct vp9_encoder_scoreboard_parameter
{
unsigned int mask;
diff --git a/src/i965_defines.h b/src/i965_defines.h
index 941ad4e..a5ca7bf 100755
--- a/src/i965_defines.h
+++ b/src/i965_defines.h
@@ -977,7 +977,10 @@
#define VDENC_SURFACE_NV21 11

#define MFC_BITSTREAM_BYTECOUNT_FRAME_REG 0x128A0
+#define MFC_BITSTREAM_BYTECOUNT_SLICE_REG 0x128D0
+#define MFC_IMAGE_STATUS_MASK_REG 0x128B4
#define MFC_IMAGE_STATUS_CTRL_REG 0x128B8
+#define MFC_QP_STATUS_COUNT_REG 0x128bc

#define GEN9_CACHE_PTE 0x02

diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index 548cbf4..62520e8 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -35,6 +35,8 @@
#include "i965_drv_video.h"
#include "i965_gpe_utils.h"

+#define DEFAULT_MOCS 2
+
static void
i965_gpe_select(VADriverContextP ctx,
struct i965_gpe_context *gpe_context,
@@ -1404,6 +1406,27 @@ i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res,
}

void
+i965_object_surface_to_2d_gpe_resource_with_align(struct i965_gpe_resource *res,
+ struct object_surface *obj_surface)
+{
+ unsigned int swizzle;
+
+ res->type = I965_GPE_RESOURCE_2D;
+ res->width = ALIGN(obj_surface->orig_width,16);
+ res->height = ALIGN(obj_surface->orig_height,16);
+ res->pitch = obj_surface->width;
+ res->size = obj_surface->size;
+ res->cb_cr_pitch = obj_surface->cb_cr_pitch;
+ res->x_cb_offset = obj_surface->x_cb_offset;
+ res->y_cb_offset = obj_surface->y_cb_offset;
+ res->bo = obj_surface->bo;
+ res->map = NULL;
+
+ dri_bo_reference(res->bo);
+ dri_bo_get_tiling(obj_surface->bo, &res->tiling, &swizzle);
+}
+
+void
i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res,
dri_bo *bo)
{
@@ -2523,6 +2546,265 @@ gen8_gpe_pipe_control(VADriverContextP ctx,
__OUT_BATCH(batch, param->dw1);
}

+void
+i965_init_media_object_walker_parameter(struct gpe_encoder_kernel_walker_parameter *kernel_walker_param,
+ struct gpe_media_object_walker_parameter *walker_param)
+{
+ memset(walker_param, 0, sizeof(*walker_param));
+
+ walker_param->use_scoreboard = kernel_walker_param->use_scoreboard;
+
+ walker_param->block_resolution.x = kernel_walker_param->resolution_x;
+ walker_param->block_resolution.y = kernel_walker_param->resolution_y;
+
+ walker_param->global_resolution.x = kernel_walker_param->resolution_x;
+ walker_param->global_resolution.y = kernel_walker_param->resolution_y;
+
+ walker_param->global_outer_loop_stride.x = kernel_walker_param->resolution_x;
+ walker_param->global_outer_loop_stride.y = 0;
+
+ walker_param->global_inner_loop_unit.x = 0;
+ walker_param->global_inner_loop_unit.y = kernel_walker_param->resolution_y;
+
+ walker_param->local_loop_exec_count = 0xFFFF; //MAX VALUE
+ walker_param->global_loop_exec_count = 0xFFFF; //MAX VALUE
+
+ if (kernel_walker_param->no_dependency) {
+ walker_param->scoreboard_mask = 0;
+ // Raster scan walking pattern
+ walker_param->local_outer_loop_stride.x = 0;
+ walker_param->local_outer_loop_stride.y = 1;
+ walker_param->local_inner_loop_unit.x = 1;
+ walker_param->local_inner_loop_unit.y = 0;
+ walker_param->local_end.x = kernel_walker_param->resolution_x - 1;
+ walker_param->local_end.y = 0;
+ } else if (kernel_walker_param->use_vertical_raster_scan) {
+ walker_param->scoreboard_mask = 0x1;
+ walker_param->use_scoreboard = 0;
+ // Raster scan walking pattern
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+ walker_param->local_inner_loop_unit.x = 0;
+ walker_param->local_inner_loop_unit.y = 1;
+ walker_param->local_end.x = 0;
+ walker_param->local_end.y = kernel_walker_param->resolution_y - 1;
+ } else {
+ walker_param->local_end.x = 0;
+ walker_param->local_end.y = 0;
+
+ if (kernel_walker_param->walker_degree == WALKER_45Z_DEGREE) {
+ // 45z degree vp9
+ walker_param->scoreboard_mask = 0x0F;
+
+ walker_param->global_loop_exec_count = 0x3FF;
+ walker_param->local_loop_exec_count = 0x3FF;
+
+ walker_param->global_resolution.x = (unsigned int)(kernel_walker_param->resolution_x / 2.f) + 1;
+ walker_param->global_resolution.y = 2 * kernel_walker_param->resolution_y;
+
+ walker_param->global_start.x = 0;
+ walker_param->global_start.y = 0;
+
+ walker_param->global_outer_loop_stride.x = walker_param->global_resolution.x;
+ walker_param->global_outer_loop_stride.y = 0;
+
+ walker_param->global_inner_loop_unit.x = 0;
+ walker_param->global_inner_loop_unit.y = walker_param->global_resolution.y;
+
+ walker_param->block_resolution.x = walker_param->global_resolution.x;
+ walker_param->block_resolution.y = walker_param->global_resolution.y;
+
+ walker_param->local_start.x = 0;
+ walker_param->local_start.y = 0;
+
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+
+ walker_param->local_inner_loop_unit.x = -1;
+ walker_param->local_inner_loop_unit.y = 4;
+
+ walker_param->middle_loop_extra_steps = 3;
+ walker_param->mid_loop_unit_x = 0;
+ walker_param->mid_loop_unit_y = 1;
+ } else if (kernel_walker_param->walker_degree == WALKER_45_DEGREE) {
+
+ walker_param->scoreboard_mask = 0x03;
+ // 45 order in local loop
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+ walker_param->local_inner_loop_unit.x = -1;
+ walker_param->local_inner_loop_unit.y = 1;
+ } else if (kernel_walker_param->walker_degree == WALKER_26Z_DEGREE) {
+ // 26z HEVC
+ walker_param->scoreboard_mask = 0x7f;
+
+ // z order in local loop
+ walker_param->local_outer_loop_stride.x = 0;
+ walker_param->local_outer_loop_stride.y = 1;
+ walker_param->local_inner_loop_unit.x = 1;
+ walker_param->local_inner_loop_unit.y = 0;
+
+ walker_param->block_resolution.x = 2;
+ walker_param->block_resolution.y = 2;
+
+ walker_param->global_outer_loop_stride.x = 2;
+ walker_param->global_outer_loop_stride.y = 0;
+
+ walker_param->global_inner_loop_unit.x = 0xFFF - 4 + 1;
+ walker_param->global_inner_loop_unit.y = 2;
+
+ } else {
+ // 26 degree
+ walker_param->scoreboard_mask = 0x0F;
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+ walker_param->local_inner_loop_unit.x = -2;
+ walker_param->local_inner_loop_unit.y = 1;
+ }
+ }
+}
+
+void
+gen9_add_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int is_uv_surface,
+ int is_media_block_rw,
+ unsigned int format,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
+ gpe_surface.gpe_resource = &gpe_resource;
+ gpe_surface.is_2d_surface = 1;
+ gpe_surface.is_uv_surface = !!is_uv_surface;
+ gpe_surface.is_media_block_rw = !!is_media_block_rw;
+
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.format = format;
+
+ gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
+ i965_free_gpe_resource(&gpe_resource);
+}
+
+void
+gen9_add_adv_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
+ gpe_surface.gpe_resource = &gpe_resource;
+ gpe_surface.is_adv_surface = 1;
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.v_direction = 2;
+
+ gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
+ i965_free_gpe_resource(&gpe_resource);
+}
+
+void
+gen9_add_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index)
+{
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ gpe_surface.gpe_resource = gpe_buffer;
+ gpe_surface.is_buffer = 1;
+ gpe_surface.is_raw_buffer = !!is_raw_buffer;
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.size = size;
+ gpe_surface.offset = offset;
+
+ gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
+}
+
+void
+gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_media_block_rw,
+ unsigned int format,
+ int index)
+{
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ gpe_surface.gpe_resource = gpe_buffer;
+ gpe_surface.is_2d_surface = 1;
+ gpe_surface.is_media_block_rw = !!is_media_block_rw;
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.format = format;
+
+ gen9_gpe_context_add_surface(gpe_context, &gpe_surface, index);
+}
+
+void
+gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+
+ i965_dri_object_to_buffer_gpe_resource(&gpe_resource, bo);
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &gpe_resource,
+ is_raw_buffer,
+ size,
+ offset,
+ index);
+
+ i965_free_gpe_resource(&gpe_resource);
+}
+
+/*
+void
+gen9_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ int is_media_block_rw,
+ unsigned int format,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+
+ i965_gpe_dri_object_to_2d_gpe_resource(&gpe_resource, bo, width, height, pitch);
+ gen9_add_buffer_2d_gpe_surface(ctx,
+ gpe_context,
+ &gpe_resource,
+ is_media_block_rw,
+ format,
+ index);
+
+ i965_free_gpe_resource(&gpe_resource);
+}
+*/
+
bool
i965_gpe_table_init(VADriverContextP ctx)
{
diff --git a/src/i965_gpe_utils.h b/src/i965_gpe_utils.h
index 52097d3..3efcb19 100644
--- a/src/i965_gpe_utils.h
+++ b/src/i965_gpe_utils.h
@@ -358,6 +358,9 @@ Bool i965_allocate_gpe_resource(dri_bufmgr *bufmgr,
void i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res,
struct object_surface *obj_surface);

+void i965_object_surface_to_2d_gpe_resource_with_align(struct i965_gpe_resource *res,
+ struct object_surface *obj_surface);
+
void i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res,
dri_bo *bo);

@@ -412,6 +415,18 @@ void gen8_gpe_mi_batch_buffer_start(VADriverContextP ctx,
struct gpe_mi_batch_buffer_start_parameter *params);


+struct gpe_media_object_inline_data
+{
+ union {
+ struct {
+ unsigned int x:8;
+ unsigned int y:8;
+ unsigned int reserved:16;
+ };
+ unsigned int value;
+ };
+};
+
struct gpe_media_object_parameter
{
unsigned int use_scoreboard;
@@ -507,6 +522,25 @@ struct gpe_media_object_walker_parameter
struct gpe_walker_xy global_inner_loop_unit;
};

+enum walker_degree
+{
+ WALKER_NO_DEGREE = 0,
+ WALKER_45_DEGREE,
+ WALKER_26_DEGREE,
+ WALKER_26Z_DEGREE,
+ WALKER_45Z_DEGREE,
+};
+struct gpe_encoder_kernel_walker_parameter
+{
+ unsigned int walker_degree;
+ unsigned int use_scoreboard;
+ unsigned int scoreboard_mask;
+ unsigned int no_dependency;
+ unsigned int resolution_x;
+ unsigned int resolution_y;
+ unsigned int use_vertical_raster_scan;
+};
+
extern void
gen8_gpe_media_object(VADriverContextP ctx,
struct i965_gpe_context *gpe_context,
@@ -555,6 +589,58 @@ gen8_gpe_pipe_control(VADriverContextP ctx,
struct intel_batchbuffer *batch,
struct gpe_pipe_control_parameter *param);

+extern void
+i965_init_media_object_walker_parameter(struct gpe_encoder_kernel_walker_parameter *kernel_walker_param,
+ struct gpe_media_object_walker_parameter *walker_param);
+
+extern void
+gen9_add_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int is_uv_surface,
+ int is_media_block_rw,
+ unsigned int format,
+ int index);
+extern void
+gen9_add_adv_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int index);
+extern void
+gen9_add_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index);
+extern void
+gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_media_block_rw,
+ unsigned int format,
+ int index);
+extern void
+gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index);
+/*
+extern void
+gen9_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ int is_media_block_rw,
+ unsigned int format,
+ int index);
+*/
struct i965_gpe_table
{
void (*context_init)(VADriverContextP ctx,
--
2.7.4
Zhao Yakui
2017-01-17 00:55:21 UTC
Permalink
Post by Pengfei Qu
add align version for obj surface conversion to gpe surface
remove comments and enum value
This version patch looks much clearer.

But it seems that the this patch still adds more defintions besides
moving the GPE functions for generic usage.
Post by Pengfei Qu
---
src/gen9_vp9_encoder.c | 154 ++-------------------------
src/gen9_vp9_encoder.h | 10 --
src/i965_defines.h | 3 +
src/i965_gpe_utils.c | 282 +++++++++++++++++++++++++++++++++++++++++++++++++
src/i965_gpe_utils.h | 86 +++++++++++++++
5 files changed, 377 insertions(+), 158 deletions(-)
diff --git a/src/gen9_vp9_encoder.c b/src/gen9_vp9_encoder.c
index 05d86da..32ed729 100644
--- a/src/gen9_vp9_encoder.c
+++ b/src/gen9_vp9_encoder.c
@@ -58,7 +58,6 @@
#define BRC_KERNEL_AVBR 0x0040
#define BRC_KERNEL_CQL 0x0080
-#define DEFAULT_MOCS 0x02
#define VP9_PIC_STATE_BUFFER_SIZE 192
typedef struct _intel_kernel_header_
@@ -842,7 +841,7 @@ gen9_vp9_free_resources(struct gen9_encoder_context_vp9 *vme_context)
static void
gen9_init_media_object_walker_parameter(struct intel_encoder_context *encoder_context,
- struct vp9_encoder_kernel_walker_parameter *kernel_walker_param,
+ struct gpe_encoder_kernel_walker_parameter *kernel_walker_param,
struct gpe_media_object_walker_parameter *walker_param)
{
memset(walker_param, 0, sizeof(*walker_param));
@@ -924,147 +923,6 @@ gen9_init_media_object_walker_parameter(struct intel_encoder_context *encoder_co
}
static void
-gen9_add_2d_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct object_surface *obj_surface,
- int is_uv_surface,
- int is_media_block_rw,
- unsigned int format,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
- gpe_surface.gpe_resource =&gpe_resource;
- gpe_surface.is_2d_surface = 1;
- gpe_surface.is_uv_surface = !!is_uv_surface;
- gpe_surface.is_media_block_rw = !!is_media_block_rw;
-
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.format = format;
-
- gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
- i965_free_gpe_resource(&gpe_resource);
-}
-
-static void
-gen9_add_adv_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct object_surface *obj_surface,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
- gpe_surface.gpe_resource =&gpe_resource;
- gpe_surface.is_adv_surface = 1;
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.v_direction = 2;
-
- gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
- i965_free_gpe_resource(&gpe_resource);
-}
-
-static void
-gen9_add_buffer_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct i965_gpe_resource *gpe_buffer,
- int is_raw_buffer,
- unsigned int size,
- unsigned int offset,
- int index)
-{
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- gpe_surface.gpe_resource = gpe_buffer;
- gpe_surface.is_buffer = 1;
- gpe_surface.is_raw_buffer = !!is_raw_buffer;
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.size = size;
- gpe_surface.offset = offset;
-
- gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
-}
-
-static void
-gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct i965_gpe_resource *gpe_buffer,
- int is_media_block_rw,
- unsigned int format,
- int index)
-{
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- gpe_surface.gpe_resource = gpe_buffer;
- gpe_surface.is_2d_surface = 1;
- gpe_surface.is_media_block_rw = !!is_media_block_rw;
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.format = format;
-
- gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
-}
-
-static void
-gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- dri_bo *bo,
- int is_raw_buffer,
- unsigned int size,
- unsigned int offset,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
-
- i965_dri_object_to_buffer_gpe_resource(&gpe_resource, bo);
- gen9_add_buffer_gpe_surface(ctx,
- gpe_context,
-&gpe_resource,
- is_raw_buffer,
- size,
- offset,
- index);
-
- i965_free_gpe_resource(&gpe_resource);
-}
-
-/*
-static void
-gen9_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- dri_bo *bo,
- unsigned int width,
- unsigned int height,
- unsigned int pitch,
- int is_media_block_rw,
- unsigned int format,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
-
- i965_dri_object_to_2d_gpe_resource(&gpe_resource, bo, width, height, pitch);
- gen9_add_buffer_2d_gpe_surface(ctx,
- gpe_context,
-&gpe_resource,
- is_media_block_rw,
- format,
- index);
-
- i965_free_gpe_resource(&gpe_resource);
-}
-*/
-
-static void
gen9_run_kernel_media_object(VADriverContextP ctx,
struct intel_encoder_context *encoder_context,
struct i965_gpe_context *gpe_context,
@@ -1491,7 +1349,7 @@ gen9_vp9_brc_intra_dist_kernel(VADriverContextP ctx,
VAEncPictureParameterBufferVP9 *pic_param;
struct gen9_vp9_state *vp9_state;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
vp9_state = (struct gen9_vp9_state *) encoder_context->enc_priv_state;
@@ -2331,7 +2189,7 @@ gen9_vp9_me_kernel(VADriverContextP ctx,
struct gen9_vp9_me_curbe_param me_curbe_param;
struct gen9_vp9_state *vp9_state;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
vp9_state = (struct gen9_vp9_state *) encoder_context->enc_priv_state;
if (!vp9_state || !vp9_state->pic_param)
@@ -2471,7 +2329,7 @@ gen9_vp9_scaling_kernel(VADriverContextP ctx,
struct gen9_vp9_state *vp9_state;
VAEncPictureParameterBufferVP9 *pic_param;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
struct object_surface *obj_surface;
struct object_surface *input_surface, *output_surface;
struct gen9_surface_vp9 *vp9_priv_surface;
@@ -2738,7 +2596,7 @@ gen9_vp9_dys_kernel(VADriverContextP ctx,
struct gen9_vp9_dys_curbe_param curbe_param;
struct gen9_vp9_dys_surface_param surface_param;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
unsigned int resolution_x, resolution_y;
media_function = VP9_MEDIA_STATE_DYS;
@@ -3526,7 +3384,7 @@ gen9_vp9_mbenc_kernel(VADriverContextP ctx,
struct gen9_encoder_context_vp9 *vme_context = encoder_context->vme_context;
struct i965_gpe_context *gpe_context, *tx_gpe_context;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
unsigned int resolution_x, resolution_y;
struct gen9_vp9_state *vp9_state;
VAEncPictureParameterBufferVP9 *pic_param;
diff --git a/src/gen9_vp9_encoder.h b/src/gen9_vp9_encoder.h
index 972e2ad..c61a796 100644
--- a/src/gen9_vp9_encoder.h
+++ b/src/gen9_vp9_encoder.h
@@ -83,16 +83,6 @@ struct vp9_encoder_kernel_parameter
unsigned int sampler_size;
};
-struct vp9_encoder_kernel_walker_parameter
-{
- unsigned int walker_degree;
- unsigned int use_scoreboard;
- unsigned int scoreboard_mask;
- unsigned int no_dependency;
- unsigned int resolution_x;
- unsigned int resolution_y;
-};
-
struct vp9_encoder_scoreboard_parameter
{
unsigned int mask;
diff --git a/src/i965_defines.h b/src/i965_defines.h
index 941ad4e..a5ca7bf 100755
--- a/src/i965_defines.h
+++ b/src/i965_defines.h
@@ -977,7 +977,10 @@
#define VDENC_SURFACE_NV21 11
#define MFC_BITSTREAM_BYTECOUNT_FRAME_REG 0x128A0
+#define MFC_BITSTREAM_BYTECOUNT_SLICE_REG 0x128D0
+#define MFC_IMAGE_STATUS_MASK_REG 0x128B4
#define MFC_IMAGE_STATUS_CTRL_REG 0x128B8
+#define MFC_QP_STATUS_COUNT_REG 0x128bc
#define GEN9_CACHE_PTE 0x02
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index 548cbf4..62520e8 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -35,6 +35,8 @@
#include "i965_drv_video.h"
#include "i965_gpe_utils.h"
+#define DEFAULT_MOCS 2
+
Please use the GEN9_CACHE_PTE instead of DEFAULT_MOCS.
Post by Pengfei Qu
static void
i965_gpe_select(VADriverContextP ctx,
struct i965_gpe_context *gpe_context,
@@ -1404,6 +1406,27 @@ i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res,
}
void
+i965_object_surface_to_2d_gpe_resource_with_align(struct i965_gpe_resource *res,
+ struct object_surface *obj_surface)
+{
+ unsigned int swizzle;
+
+ res->type = I965_GPE_RESOURCE_2D;
+ res->width = ALIGN(obj_surface->orig_width,16);
+ res->height = ALIGN(obj_surface->orig_height,16);
+ res->pitch = obj_surface->width;
+ res->size = obj_surface->size;
+ res->cb_cr_pitch = obj_surface->cb_cr_pitch;
+ res->x_cb_offset = obj_surface->x_cb_offset;
+ res->y_cb_offset = obj_surface->y_cb_offset;
+ res->bo = obj_surface->bo;
+ res->map = NULL;
+
+ dri_bo_reference(res->bo);
+ dri_bo_get_tiling(obj_surface->bo,&res->tiling,&swizzle);
+}
+
+void
i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res,
dri_bo *bo)
{
@@ -2523,6 +2546,265 @@ gen8_gpe_pipe_control(VADriverContextP ctx,
__OUT_BATCH(batch, param->dw1);
}
+void
+i965_init_media_object_walker_parameter(struct gpe_encoder_kernel_walker_parameter *kernel_walker_param,
+ struct gpe_media_object_walker_parameter *walker_param)
+{
+ memset(walker_param, 0, sizeof(*walker_param));
+
+ walker_param->use_scoreboard = kernel_walker_param->use_scoreboard;
+
+ walker_param->block_resolution.x = kernel_walker_param->resolution_x;
+ walker_param->block_resolution.y = kernel_walker_param->resolution_y;
+
+ walker_param->global_resolution.x = kernel_walker_param->resolution_x;
+ walker_param->global_resolution.y = kernel_walker_param->resolution_y;
+
+ walker_param->global_outer_loop_stride.x = kernel_walker_param->resolution_x;
+ walker_param->global_outer_loop_stride.y = 0;
+
+ walker_param->global_inner_loop_unit.x = 0;
+ walker_param->global_inner_loop_unit.y = kernel_walker_param->resolution_y;
+
+ walker_param->local_loop_exec_count = 0xFFFF; //MAX VALUE
+ walker_param->global_loop_exec_count = 0xFFFF; //MAX VALUE
+
+ if (kernel_walker_param->no_dependency) {
+ walker_param->scoreboard_mask = 0;
+ // Raster scan walking pattern
+ walker_param->local_outer_loop_stride.x = 0;
+ walker_param->local_outer_loop_stride.y = 1;
+ walker_param->local_inner_loop_unit.x = 1;
+ walker_param->local_inner_loop_unit.y = 0;
+ walker_param->local_end.x = kernel_walker_param->resolution_x - 1;
+ walker_param->local_end.y = 0;
+ } else if (kernel_walker_param->use_vertical_raster_scan) {
+ walker_param->scoreboard_mask = 0x1;
+ walker_param->use_scoreboard = 0;
+ // Raster scan walking pattern
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+ walker_param->local_inner_loop_unit.x = 0;
+ walker_param->local_inner_loop_unit.y = 1;
+ walker_param->local_end.x = 0;
+ walker_param->local_end.y = kernel_walker_param->resolution_y - 1;
+ } else {
+ walker_param->local_end.x = 0;
+ walker_param->local_end.y = 0;
+
+ if (kernel_walker_param->walker_degree == WALKER_45Z_DEGREE) {
+ // 45z degree vp9
+ walker_param->scoreboard_mask = 0x0F;
+
+ walker_param->global_loop_exec_count = 0x3FF;
+ walker_param->local_loop_exec_count = 0x3FF;
+
+ walker_param->global_resolution.x = (unsigned int)(kernel_walker_param->resolution_x / 2.f) + 1;
+ walker_param->global_resolution.y = 2 * kernel_walker_param->resolution_y;
+
+ walker_param->global_start.x = 0;
+ walker_param->global_start.y = 0;
+
+ walker_param->global_outer_loop_stride.x = walker_param->global_resolution.x;
+ walker_param->global_outer_loop_stride.y = 0;
+
+ walker_param->global_inner_loop_unit.x = 0;
+ walker_param->global_inner_loop_unit.y = walker_param->global_resolution.y;
+
+ walker_param->block_resolution.x = walker_param->global_resolution.x;
+ walker_param->block_resolution.y = walker_param->global_resolution.y;
+
+ walker_param->local_start.x = 0;
+ walker_param->local_start.y = 0;
+
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+
+ walker_param->local_inner_loop_unit.x = -1;
+ walker_param->local_inner_loop_unit.y = 4;
+
+ walker_param->middle_loop_extra_steps = 3;
+ walker_param->mid_loop_unit_x = 0;
+ walker_param->mid_loop_unit_y = 1;
+ } else if (kernel_walker_param->walker_degree == WALKER_45_DEGREE) {
+
+ walker_param->scoreboard_mask = 0x03;
+ // 45 order in local loop
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+ walker_param->local_inner_loop_unit.x = -1;
+ walker_param->local_inner_loop_unit.y = 1;
+ } else if (kernel_walker_param->walker_degree == WALKER_26Z_DEGREE) {
+ // 26z HEVC
+ walker_param->scoreboard_mask = 0x7f;
+
+ // z order in local loop
+ walker_param->local_outer_loop_stride.x = 0;
+ walker_param->local_outer_loop_stride.y = 1;
+ walker_param->local_inner_loop_unit.x = 1;
+ walker_param->local_inner_loop_unit.y = 0;
+
+ walker_param->block_resolution.x = 2;
+ walker_param->block_resolution.y = 2;
+
+ walker_param->global_outer_loop_stride.x = 2;
+ walker_param->global_outer_loop_stride.y = 0;
+
+ walker_param->global_inner_loop_unit.x = 0xFFF - 4 + 1;
+ walker_param->global_inner_loop_unit.y = 2;
+
+ } else {
+ // 26 degree
+ walker_param->scoreboard_mask = 0x0F;
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+ walker_param->local_inner_loop_unit.x = -2;
+ walker_param->local_inner_loop_unit.y = 1;
+ }
+ }
+}
+
+void
+gen9_add_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int is_uv_surface,
+ int is_media_block_rw,
+ unsigned int format,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
+ gpe_surface.gpe_resource =&gpe_resource;
+ gpe_surface.is_2d_surface = 1;
+ gpe_surface.is_uv_surface = !!is_uv_surface;
+ gpe_surface.is_media_block_rw = !!is_media_block_rw;
+
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.format = format;
+
+ gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
+ i965_free_gpe_resource(&gpe_resource);
+}
+
+void
+gen9_add_adv_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
+ gpe_surface.gpe_resource =&gpe_resource;
+ gpe_surface.is_adv_surface = 1;
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.v_direction = 2;
+
+ gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
+ i965_free_gpe_resource(&gpe_resource);
+}
+
+void
+gen9_add_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index)
+{
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ gpe_surface.gpe_resource = gpe_buffer;
+ gpe_surface.is_buffer = 1;
+ gpe_surface.is_raw_buffer = !!is_raw_buffer;
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.size = size;
+ gpe_surface.offset = offset;
+
+ gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
+}
+
+void
+gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_media_block_rw,
+ unsigned int format,
+ int index)
+{
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ gpe_surface.gpe_resource = gpe_buffer;
+ gpe_surface.is_2d_surface = 1;
+ gpe_surface.is_media_block_rw = !!is_media_block_rw;
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.format = format;
+
+ gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
+}
+
+void
+gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+
+ i965_dri_object_to_buffer_gpe_resource(&gpe_resource, bo);
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+&gpe_resource,
+ is_raw_buffer,
+ size,
+ offset,
+ index);
+
+ i965_free_gpe_resource(&gpe_resource);
+}
+
It seems that the below function is not defined or declared as it is
commented.
It will be better that it is removed.

If it is really useful, please remove the comment so that it is
defined/declared.
Post by Pengfei Qu
+/*
+void
+gen9_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ int is_media_block_rw,
+ unsigned int format,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+
+ i965_gpe_dri_object_to_2d_gpe_resource(&gpe_resource, bo, width, height, pitch);
+ gen9_add_buffer_2d_gpe_surface(ctx,
+ gpe_context,
+&gpe_resource,
+ is_media_block_rw,
+ format,
+ index);
+
+ i965_free_gpe_resource(&gpe_resource);
+}
+*/
+
bool
i965_gpe_table_init(VADriverContextP ctx)
{
diff --git a/src/i965_gpe_utils.h b/src/i965_gpe_utils.h
index 52097d3..3efcb19 100644
--- a/src/i965_gpe_utils.h
+++ b/src/i965_gpe_utils.h
@@ -358,6 +358,9 @@ Bool i965_allocate_gpe_resource(dri_bufmgr *bufmgr,
void i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res,
struct object_surface *obj_surface);
+void i965_object_surface_to_2d_gpe_resource_with_align(struct i965_gpe_resource *res,
+ struct object_surface *obj_surface);
+
void i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res,
dri_bo *bo);
@@ -412,6 +415,18 @@ void gen8_gpe_mi_batch_buffer_start(VADriverContextP ctx,
struct gpe_mi_batch_buffer_start_parameter *params);
+struct gpe_media_object_inline_data
+{
+ union {
+ struct {
+ unsigned int x:8;
+ unsigned int y:8;
+ unsigned int reserved:16;
+ };
+ unsigned int value;
+ };
+};
+
struct gpe_media_object_parameter
{
unsigned int use_scoreboard;
@@ -507,6 +522,25 @@ struct gpe_media_object_walker_parameter
struct gpe_walker_xy global_inner_loop_unit;
};
+enum walker_degree
+{
+ WALKER_NO_DEGREE = 0,
+ WALKER_45_DEGREE,
+ WALKER_26_DEGREE,
+ WALKER_26Z_DEGREE,
+ WALKER_45Z_DEGREE,
+};
+struct gpe_encoder_kernel_walker_parameter
+{
+ unsigned int walker_degree;
+ unsigned int use_scoreboard;
+ unsigned int scoreboard_mask;
+ unsigned int no_dependency;
+ unsigned int resolution_x;
+ unsigned int resolution_y;
+ unsigned int use_vertical_raster_scan;
+};
+
extern void
gen8_gpe_media_object(VADriverContextP ctx,
struct i965_gpe_context *gpe_context,
@@ -555,6 +589,58 @@ gen8_gpe_pipe_control(VADriverContextP ctx,
struct intel_batchbuffer *batch,
struct gpe_pipe_control_parameter *param);
+extern void
+i965_init_media_object_walker_parameter(struct gpe_encoder_kernel_walker_parameter *kernel_walker_param,
+ struct gpe_media_object_walker_parameter *walker_param);
+
+extern void
+gen9_add_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int is_uv_surface,
+ int is_media_block_rw,
+ unsigned int format,
+ int index);
+extern void
+gen9_add_adv_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int index);
+extern void
+gen9_add_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index);
+extern void
+gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_media_block_rw,
+ unsigned int format,
+ int index);
+extern void
+gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index);
It seems that the below function is not defined or declared as it is
commented.
It will be better that it is removed.
Post by Pengfei Qu
+/*
+extern void
+gen9_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ int is_media_block_rw,
+ unsigned int format,
+ int index);
+*/
struct i965_gpe_table
{
void (*context_init)(VADriverContextP ctx,
Qu, Pengfei
2017-01-18 11:26:27 UTC
Permalink
-----Original Message-----
From: Zhao, Yakui
Sent: Tuesday, January 17, 2017 8:55 AM
To: Qu, Pengfei <***@intel.com>
Cc: ***@lists.freedesktop.org
Subject: Re: [Libva] [PATCH v1 1/9] ENC: move gpe related function into src/i965_gpe_utils.h/c
add align version for obj surface conversion to gpe surface remove
comments and enum value
This version patch looks much clearer.

But it seems that the this patch still adds more defintions besides moving the GPE functions for generic usage.
[Pengfei] the function will be commented out.
---
src/gen9_vp9_encoder.c | 154 ++-------------------------
src/gen9_vp9_encoder.h | 10 --
src/i965_defines.h | 3 +
src/i965_gpe_utils.c | 282 +++++++++++++++++++++++++++++++++++++++++++++++++
src/i965_gpe_utils.h | 86 +++++++++++++++
5 files changed, 377 insertions(+), 158 deletions(-)
diff --git a/src/gen9_vp9_encoder.c b/src/gen9_vp9_encoder.c index
05d86da..32ed729 100644
--- a/src/gen9_vp9_encoder.c
+++ b/src/gen9_vp9_encoder.c
@@ -58,7 +58,6 @@
#define BRC_KERNEL_AVBR 0x0040
#define BRC_KERNEL_CQL 0x0080
-#define DEFAULT_MOCS 0x02
#define VP9_PIC_STATE_BUFFER_SIZE 192
gen9_vp9_free_resources(struct gen9_encoder_context_vp9 *vme_context)
static void
gen9_init_media_object_walker_parameter(struct intel_encoder_context *encoder_context,
- struct vp9_encoder_kernel_walker_parameter *kernel_walker_param,
+ struct
+ gpe_encoder_kernel_walker_parameter *kernel_walker_param,
struct gpe_media_object_walker_parameter *walker_param)
{
}
static void
-gen9_add_2d_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct object_surface *obj_surface,
- int is_uv_surface,
- int is_media_block_rw,
- unsigned int format,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
- gpe_surface.gpe_resource =&gpe_resource;
- gpe_surface.is_2d_surface = 1;
- gpe_surface.is_uv_surface = !!is_uv_surface;
- gpe_surface.is_media_block_rw = !!is_media_block_rw;
-
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.format = format;
-
- gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
- i965_free_gpe_resource(&gpe_resource);
-}
-
-static void
-gen9_add_adv_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct object_surface *obj_surface,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
- gpe_surface.gpe_resource =&gpe_resource;
- gpe_surface.is_adv_surface = 1;
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.v_direction = 2;
-
- gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
- i965_free_gpe_resource(&gpe_resource);
-}
-
-static void
-gen9_add_buffer_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct i965_gpe_resource *gpe_buffer,
- int is_raw_buffer,
- unsigned int size,
- unsigned int offset,
- int index)
-{
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- gpe_surface.gpe_resource = gpe_buffer;
- gpe_surface.is_buffer = 1;
- gpe_surface.is_raw_buffer = !!is_raw_buffer;
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.size = size;
- gpe_surface.offset = offset;
-
- gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
-}
-
-static void
-gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- struct i965_gpe_resource *gpe_buffer,
- int is_media_block_rw,
- unsigned int format,
- int index)
-{
- struct i965_gpe_surface gpe_surface;
-
- memset(&gpe_surface, 0, sizeof(gpe_surface));
-
- gpe_surface.gpe_resource = gpe_buffer;
- gpe_surface.is_2d_surface = 1;
- gpe_surface.is_media_block_rw = !!is_media_block_rw;
- gpe_surface.cacheability_control = DEFAULT_MOCS;
- gpe_surface.format = format;
-
- gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
-}
-
-static void
-gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- dri_bo *bo,
- int is_raw_buffer,
- unsigned int size,
- unsigned int offset,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
-
- i965_dri_object_to_buffer_gpe_resource(&gpe_resource, bo);
- gen9_add_buffer_gpe_surface(ctx,
- gpe_context,
-&gpe_resource,
- is_raw_buffer,
- size,
- offset,
- index);
-
- i965_free_gpe_resource(&gpe_resource);
-}
-
-/*
-static void
-gen9_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
- struct i965_gpe_context *gpe_context,
- dri_bo *bo,
- unsigned int width,
- unsigned int height,
- unsigned int pitch,
- int is_media_block_rw,
- unsigned int format,
- int index)
-{
- struct i965_gpe_resource gpe_resource;
-
- i965_dri_object_to_2d_gpe_resource(&gpe_resource, bo, width, height, pitch);
- gen9_add_buffer_2d_gpe_surface(ctx,
- gpe_context,
-&gpe_resource,
- is_media_block_rw,
- format,
- index);
-
- i965_free_gpe_resource(&gpe_resource);
-}
-*/
-
-static void
gen9_run_kernel_media_object(VADriverContextP ctx,
struct intel_encoder_context *encoder_context,
struct i965_gpe_context *gpe_context,
@@ -1491,7 +1349,7 @@ gen9_vp9_brc_intra_dist_kernel(VADriverContextP ctx,
VAEncPictureParameterBufferVP9 *pic_param;
struct gen9_vp9_state *vp9_state;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
vp9_state = (struct gen9_vp9_state *)
encoder_context->enc_priv_state;
@@ -2331,7 +2189,7 @@ gen9_vp9_me_kernel(VADriverContextP ctx,
struct gen9_vp9_me_curbe_param me_curbe_param;
struct gen9_vp9_state *vp9_state;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
vp9_state = (struct gen9_vp9_state *) encoder_context->enc_priv_state;
gen9_vp9_scaling_kernel(VADriverContextP ctx,
struct gen9_vp9_state *vp9_state;
VAEncPictureParameterBufferVP9 *pic_param;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
struct object_surface *obj_surface;
struct object_surface *input_surface, *output_surface;
gen9_vp9_dys_kernel(VADriverContextP ctx,
struct gen9_vp9_dys_curbe_param curbe_param;
struct gen9_vp9_dys_surface_param surface_param;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
unsigned int resolution_x, resolution_y;
gen9_vp9_mbenc_kernel(VADriverContextP ctx,
struct gen9_encoder_context_vp9 *vme_context = encoder_context->vme_context;
struct i965_gpe_context *gpe_context, *tx_gpe_context;
struct gpe_media_object_walker_parameter media_object_walker_param;
- struct vp9_encoder_kernel_walker_parameter kernel_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
unsigned int resolution_x, resolution_y;
struct gen9_vp9_state *vp9_state;
VAEncPictureParameterBufferVP9 *pic_param; diff --git
a/src/gen9_vp9_encoder.h b/src/gen9_vp9_encoder.h index
972e2ad..c61a796 100644
--- a/src/gen9_vp9_encoder.h
+++ b/src/gen9_vp9_encoder.h
@@ -83,16 +83,6 @@ struct vp9_encoder_kernel_parameter
unsigned int sampler_size;
};
-struct vp9_encoder_kernel_walker_parameter
-{
- unsigned int walker_degree;
- unsigned int use_scoreboard;
- unsigned int scoreboard_mask;
- unsigned int no_dependency;
- unsigned int resolution_x;
- unsigned int resolution_y;
-};
-
struct vp9_encoder_scoreboard_parameter
{
unsigned int mask;
diff --git a/src/i965_defines.h b/src/i965_defines.h index
941ad4e..a5ca7bf 100755
--- a/src/i965_defines.h
+++ b/src/i965_defines.h
@@ -977,7 +977,10 @@
#define VDENC_SURFACE_NV21 11
#define MFC_BITSTREAM_BYTECOUNT_FRAME_REG 0x128A0
+#define MFC_BITSTREAM_BYTECOUNT_SLICE_REG 0x128D0
+#define MFC_IMAGE_STATUS_MASK_REG 0x128B4
#define MFC_IMAGE_STATUS_CTRL_REG 0x128B8
+#define MFC_QP_STATUS_COUNT_REG 0x128bc
#define GEN9_CACHE_PTE 0x02
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c index
548cbf4..62520e8 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -35,6 +35,8 @@
#include "i965_drv_video.h"
#include "i965_gpe_utils.h"
+#define DEFAULT_MOCS 2
+
Please use the GEN9_CACHE_PTE instead of DEFAULT_MOCS.
static void
i965_gpe_select(VADriverContextP ctx,
}
void
+i965_object_surface_to_2d_gpe_resource_with_align(struct i965_gpe_resource *res,
+ struct
+object_surface *obj_surface) {
+ unsigned int swizzle;
+
+ res->type = I965_GPE_RESOURCE_2D;
+ res->width = ALIGN(obj_surface->orig_width,16);
+ res->height = ALIGN(obj_surface->orig_height,16);
+ res->pitch = obj_surface->width;
+ res->size = obj_surface->size;
+ res->cb_cr_pitch = obj_surface->cb_cr_pitch;
+ res->x_cb_offset = obj_surface->x_cb_offset;
+ res->y_cb_offset = obj_surface->y_cb_offset;
+ res->bo = obj_surface->bo;
+ res->map = NULL;
+
+ dri_bo_reference(res->bo);
+ dri_bo_get_tiling(obj_surface->bo,&res->tiling,&swizzle);
+}
+
+void
i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res,
dri_bo *bo)
{
@@ -2523,6 +2546,265 @@ gen8_gpe_pipe_control(VADriverContextP ctx,
__OUT_BATCH(batch, param->dw1);
}
+void
+i965_init_media_object_walker_parameter(struct gpe_encoder_kernel_walker_parameter *kernel_walker_param,
+ struct
+gpe_media_object_walker_parameter *walker_param) {
+ memset(walker_param, 0, sizeof(*walker_param));
+
+ walker_param->use_scoreboard =
+ kernel_walker_param->use_scoreboard;
+
+ walker_param->block_resolution.x = kernel_walker_param->resolution_x;
+ walker_param->block_resolution.y =
+ kernel_walker_param->resolution_y;
+
+ walker_param->global_resolution.x = kernel_walker_param->resolution_x;
+ walker_param->global_resolution.y =
+ kernel_walker_param->resolution_y;
+
+ walker_param->global_outer_loop_stride.x = kernel_walker_param->resolution_x;
+ walker_param->global_outer_loop_stride.y = 0;
+
+ walker_param->global_inner_loop_unit.x = 0;
+ walker_param->global_inner_loop_unit.y =
+ kernel_walker_param->resolution_y;
+
+ walker_param->local_loop_exec_count = 0xFFFF; //MAX VALUE
+ walker_param->global_loop_exec_count = 0xFFFF; //MAX VALUE
+
+ if (kernel_walker_param->no_dependency) {
+ walker_param->scoreboard_mask = 0;
+ // Raster scan walking pattern
+ walker_param->local_outer_loop_stride.x = 0;
+ walker_param->local_outer_loop_stride.y = 1;
+ walker_param->local_inner_loop_unit.x = 1;
+ walker_param->local_inner_loop_unit.y = 0;
+ walker_param->local_end.x = kernel_walker_param->resolution_x - 1;
+ walker_param->local_end.y = 0;
+ } else if (kernel_walker_param->use_vertical_raster_scan) {
+ walker_param->scoreboard_mask = 0x1;
+ walker_param->use_scoreboard = 0;
+ // Raster scan walking pattern
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+ walker_param->local_inner_loop_unit.x = 0;
+ walker_param->local_inner_loop_unit.y = 1;
+ walker_param->local_end.x = 0;
+ walker_param->local_end.y = kernel_walker_param->resolution_y - 1;
+ } else {
+ walker_param->local_end.x = 0;
+ walker_param->local_end.y = 0;
+
+ if (kernel_walker_param->walker_degree == WALKER_45Z_DEGREE) {
+ // 45z degree vp9
+ walker_param->scoreboard_mask = 0x0F;
+
+ walker_param->global_loop_exec_count = 0x3FF;
+ walker_param->local_loop_exec_count = 0x3FF;
+
+ walker_param->global_resolution.x = (unsigned int)(kernel_walker_param->resolution_x / 2.f) + 1;
+ walker_param->global_resolution.y = 2 *
+ kernel_walker_param->resolution_y;
+
+ walker_param->global_start.x = 0;
+ walker_param->global_start.y = 0;
+
+ walker_param->global_outer_loop_stride.x = walker_param->global_resolution.x;
+ walker_param->global_outer_loop_stride.y = 0;
+
+ walker_param->global_inner_loop_unit.x = 0;
+ walker_param->global_inner_loop_unit.y =
+ walker_param->global_resolution.y;
+
+ walker_param->block_resolution.x = walker_param->global_resolution.x;
+ walker_param->block_resolution.y =
+ walker_param->global_resolution.y;
+
+ walker_param->local_start.x = 0;
+ walker_param->local_start.y = 0;
+
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+
+ walker_param->local_inner_loop_unit.x = -1;
+ walker_param->local_inner_loop_unit.y = 4;
+
+ walker_param->middle_loop_extra_steps = 3;
+ walker_param->mid_loop_unit_x = 0;
+ walker_param->mid_loop_unit_y = 1;
+ } else if (kernel_walker_param->walker_degree ==
+ WALKER_45_DEGREE) {
+
+ walker_param->scoreboard_mask = 0x03;
+ // 45 order in local loop
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+ walker_param->local_inner_loop_unit.x = -1;
+ walker_param->local_inner_loop_unit.y = 1;
+ } else if (kernel_walker_param->walker_degree == WALKER_26Z_DEGREE) {
+ // 26z HEVC
+ walker_param->scoreboard_mask = 0x7f;
+
+ // z order in local loop
+ walker_param->local_outer_loop_stride.x = 0;
+ walker_param->local_outer_loop_stride.y = 1;
+ walker_param->local_inner_loop_unit.x = 1;
+ walker_param->local_inner_loop_unit.y = 0;
+
+ walker_param->block_resolution.x = 2;
+ walker_param->block_resolution.y = 2;
+
+ walker_param->global_outer_loop_stride.x = 2;
+ walker_param->global_outer_loop_stride.y = 0;
+
+ walker_param->global_inner_loop_unit.x = 0xFFF - 4 + 1;
+ walker_param->global_inner_loop_unit.y = 2;
+
+ } else {
+ // 26 degree
+ walker_param->scoreboard_mask = 0x0F;
+ walker_param->local_outer_loop_stride.x = 1;
+ walker_param->local_outer_loop_stride.y = 0;
+ walker_param->local_inner_loop_unit.x = -2;
+ walker_param->local_inner_loop_unit.y = 1;
+ }
+ }
+}
+
+void
+gen9_add_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int is_uv_surface,
+ int is_media_block_rw,
+ unsigned int format,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
+ gpe_surface.gpe_resource =&gpe_resource;
+ gpe_surface.is_2d_surface = 1;
+ gpe_surface.is_uv_surface = !!is_uv_surface;
+ gpe_surface.is_media_block_rw = !!is_media_block_rw;
+
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.format = format;
+
+ gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
+ i965_free_gpe_resource(&gpe_resource);
+}
+
+void
+gen9_add_adv_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
+ gpe_surface.gpe_resource =&gpe_resource;
+ gpe_surface.is_adv_surface = 1;
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.v_direction = 2;
+
+ gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
+ i965_free_gpe_resource(&gpe_resource);
+}
+
+void
+gen9_add_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index) {
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ gpe_surface.gpe_resource = gpe_buffer;
+ gpe_surface.is_buffer = 1;
+ gpe_surface.is_raw_buffer = !!is_raw_buffer;
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.size = size;
+ gpe_surface.offset = offset;
+
+ gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index); }
+
+void
+gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_media_block_rw,
+ unsigned int format,
+ int index) {
+ struct i965_gpe_surface gpe_surface;
+
+ memset(&gpe_surface, 0, sizeof(gpe_surface));
+
+ gpe_surface.gpe_resource = gpe_buffer;
+ gpe_surface.is_2d_surface = 1;
+ gpe_surface.is_media_block_rw = !!is_media_block_rw;
+ gpe_surface.cacheability_control = DEFAULT_MOCS;
+ gpe_surface.format = format;
+
+ gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index); }
+
+void
+gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index) {
+ struct i965_gpe_resource gpe_resource;
+
+ i965_dri_object_to_buffer_gpe_resource(&gpe_resource, bo);
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context, &gpe_resource,
+ is_raw_buffer,
+ size,
+ offset,
+ index);
+
+ i965_free_gpe_resource(&gpe_resource);
+}
+
It seems that the below function is not defined or declared as it is commented.
It will be better that it is removed.

If it is really useful, please remove the comment so that it is defined/declared.
+/*
+void
+gen9_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ int is_media_block_rw,
+ unsigned int format,
+ int index)
+{
+ struct i965_gpe_resource gpe_resource;
+
+ i965_gpe_dri_object_to_2d_gpe_resource(&gpe_resource, bo, width, height, pitch);
+ gen9_add_buffer_2d_gpe_surface(ctx,
+ gpe_context,
+&gpe_resource,
+ is_media_block_rw,
+ format,
+ index);
+
+ i965_free_gpe_resource(&gpe_resource);
+}
+*/
+
bool
i965_gpe_table_init(VADriverContextP ctx)
{
diff --git a/src/i965_gpe_utils.h b/src/i965_gpe_utils.h
index 52097d3..3efcb19 100644
--- a/src/i965_gpe_utils.h
+++ b/src/i965_gpe_utils.h
@@ -358,6 +358,9 @@ Bool i965_allocate_gpe_resource(dri_bufmgr *bufmgr,
void i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res,
struct object_surface *obj_surface);
+void i965_object_surface_to_2d_gpe_resource_with_align(struct i965_gpe_resource *res,
+ struct object_surface *obj_surface);
+
void i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res,
dri_bo *bo);
@@ -412,6 +415,18 @@ void gen8_gpe_mi_batch_buffer_start(VADriverContextP ctx,
struct gpe_mi_batch_buffer_start_parameter *params);
+struct gpe_media_object_inline_data
+{
+ union {
+ struct {
+ unsigned int x:8;
+ unsigned int y:8;
+ unsigned int reserved:16;
+ };
+ unsigned int value;
+ };
+};
+
struct gpe_media_object_parameter
{
unsigned int use_scoreboard;
@@ -507,6 +522,25 @@ struct gpe_media_object_walker_parameter
struct gpe_walker_xy global_inner_loop_unit;
};
+enum walker_degree
+{
+ WALKER_NO_DEGREE = 0,
+ WALKER_45_DEGREE,
+ WALKER_26_DEGREE,
+ WALKER_26Z_DEGREE,
+ WALKER_45Z_DEGREE,
+};
+struct gpe_encoder_kernel_walker_parameter
+{
+ unsigned int walker_degree;
+ unsigned int use_scoreboard;
+ unsigned int scoreboard_mask;
+ unsigned int no_dependency;
+ unsigned int resolution_x;
+ unsigned int resolution_y;
+ unsigned int use_vertical_raster_scan;
+};
+
extern void
gen8_gpe_media_object(VADriverContextP ctx,
struct i965_gpe_context *gpe_context,
@@ -555,6 +589,58 @@ gen8_gpe_pipe_control(VADriverContextP ctx,
struct intel_batchbuffer *batch,
struct gpe_pipe_control_parameter *param);
+extern void
+i965_init_media_object_walker_parameter(struct gpe_encoder_kernel_walker_parameter *kernel_walker_param,
+ struct gpe_media_object_walker_parameter *walker_param);
+
+extern void
+gen9_add_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int is_uv_surface,
+ int is_media_block_rw,
+ unsigned int format,
+ int index);
+extern void
+gen9_add_adv_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct object_surface *obj_surface,
+ int index);
+extern void
+gen9_add_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index);
+extern void
+gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct i965_gpe_resource *gpe_buffer,
+ int is_media_block_rw,
+ unsigned int format,
+ int index);
+extern void
+gen9_add_dri_buffer_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ int is_raw_buffer,
+ unsigned int size,
+ unsigned int offset,
+ int index);
It seems that the below function is not defined or declared as it is
commented.
It will be better that it is removed.
+/*
+extern void
+gen9_add_dri_buffer_2d_gpe_surface(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ dri_bo *bo,
+ unsigned int width,
+ unsigned int height,
+ unsigned int pitch,
+ int is_media_block_rw,
+ unsigned int format,
+ int index);
+*/
struct i965_gpe_table
{
void (*context_init)(VADriverContextP ctx,
Pengfei Qu
2017-01-13 09:24:05 UTC
Permalink
add context init function for AVC encoder

Signed-off-by: Pengfei Qu <***@intel.com>
Reviewed-by: Sean V Kelley<***@posteo.de>
---
src/i965_encoder_api.h | 47 ++++
src/i965_encoder_common.c | 124 +++++++++++
src/i965_encoder_common.h | 533 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 704 insertions(+)
create mode 100755 src/i965_encoder_api.h
create mode 100755 src/i965_encoder_common.c
create mode 100755 src/i965_encoder_common.h

diff --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h
new file mode 100755
index 0000000..ebb0edc
--- /dev/null
+++ b/src/i965_encoder_api.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Pengfei Qu <***@intel.com>
+ *
+ */
+
+#ifndef _I965_ENCODER_API_H_
+#define _I965_ENCODER_API_H_
+
+#include <va/va.h>
+
+struct intel_encoder_context;
+struct hw_context;
+
+/* H264/AVC */
+extern Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
+
+extern Bool
+gen9_avc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
+
+extern VAStatus
+gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct hw_context *hw_context);
+
+#endif // _I965_ENCODER_API_H_
diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c
new file mode 100755
index 0000000..930aba9
--- /dev/null
+++ b/src/i965_encoder_common.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu <***@intel.com>
+ *
+ */
+#include <stdio.h>
+#include <string.h>
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+#include "i965_encoder_common.h"
+#include "i965_gpe_utils.h"
+
+
+const unsigned int table_enc_search_path[2][8][16] =
+{
+ // I-Frame & P-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101,
+ 0x01010101, 0x11010101, 0x01010101, 0x00010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding P frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ },
+ // B-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding B frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ }
+};
\ No newline at end of file
diff --git a/src/i965_encoder_common.h b/src/i965_encoder_common.h
new file mode 100755
index 0000000..bffbd8f
--- /dev/null
+++ b/src/i965_encoder_common.h
@@ -0,0 +1,533 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu <***@intel.com>
+ *
+ */
+
+#ifndef _I965_COMMON_ENCODER_H
+#define _I965_COMMON_ENCODER_H
+
+#include <drm.h>
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+
+#include <va/va.h>
+#include "i965_encoder.h"
+#include "i965_gpe_utils.h"
+//#include "gen9_avc_encoder.h"
+
+struct encode_state;
+struct intel_encoder_context;
+
+/*
+ this file define the common structure for encoder, such as H264/H265/VP8/VP9
+*/
+
+#define INTEL_BRC_NONE 0
+#define INTEL_BRC_CBR 1
+#define INTEL_BRC_VBR 2
+#define INTEL_BRC_CQP 3
+#define INTEL_BRC_AVBR 4
+
+#define INTEL_BRC_INIT_FLAG_CBR 0x0010,
+#define INTEL_BRC_INIT_FLAG_VBR 0x0020,
+#define INTEL_BRC_INIT_FLAG_AVBR 0x0040,
+#define INTEL_BRC_INIT_FLAG_CQL 0x0080,
+#define INTEL_BRC_INIT_FLAG_FIELD_PIC 0x0100,
+#define INTEL_BRC_INIT_FLAG_ICQ 0x0200,
+#define INTEL_BRC_INIT_FLAG_VCM 0x0400,
+#define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
+#define INTEL_BRC_INIT_FLAG_QVBR 0x4000,
+#define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC 0x8000
+
+
+#define INTEL_BRC_UPDATE_FLAG_FIELD 0x01,
+#define INTEL_BRC_UPDATE_FLAG_MBAFF (0x01 << 1),
+#define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD (0x01 << 2),
+#define INTEL_BRC_UPDATE_FLAG_ACTUALQP (0x01 << 6),
+#define INTEL_BRC_UPDATE_FLAG_REFERENCE (0x01 << 7)
+
+#define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT 48
+
+extern const unsigned int table_enc_search_path[2][8][16];
+
+// BRC Flag in BRC Init Kernel
+typedef enum _INTEL_ENCODE_BRCINIT_FLAG
+{
+ INTEL_ENCODE_BRCINIT_ISCBR = 0x0010,
+ INTEL_ENCODE_BRCINIT_ISVBR = 0x0020,
+ INTEL_ENCODE_BRCINIT_ISAVBR = 0x0040,
+ INTEL_ENCODE_BRCINIT_ISCQL = 0x0080,
+ INTEL_ENCODE_BRCINIT_FIELD_PIC = 0x0100,
+ INTEL_ENCODE_BRCINIT_ISICQ = 0x0200,
+ INTEL_ENCODE_BRCINIT_ISVCM = 0x0400,
+ INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE = 0x2000,
+ INTEL_ENCODE_BRCINIT_ISQVBR = 0x4000,
+ INTEL_ENCODE_BRCINIT_DISABLE_MBBRC = 0x8000
+} INTEL_ENCODE_BRCINIT_FLAG;
+
+// BRC Flag in BRC Update Kernel
+typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG
+{
+ INTEL_ENCODE_BRCUPDATE_IS_FIELD = 0x01,
+ INTEL_ENCODE_BRCUPDATE_IS_MBAFF = (0x01 << 1),
+ INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD = (0x01 << 2),
+ INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP = (0x01 << 6),
+ INTEL_ENCODE_BRCUPDATE_IS_REFERENCE = (0x01 << 7)
+} INTEL_ENCODE_BRCUPDATE_FLAG;
+
+/*
+kernel operation related defines
+*/
+typedef enum _INTEL_GENERIC_ENC_OPERATION
+{
+ INTEL_GENERIC_ENC_SCALING4X = 0,
+ INTEL_GENERIC_ENC_SCALING2X,
+ INTEL_GENERIC_ENC_ME,
+ INTEL_GENERIC_ENC_BRC,
+ INTEL_GENERIC_ENC_MBENC,
+ INTEL_GENERIC_ENC_MBENC_WIDI,
+ INTEL_GENERIC_ENC_RESETVLINESTRIDE,
+ INTEL_GENERIC_ENC_MC,
+ INTEL_GENERIC_ENC_MBPAK,
+ INTEL_GENERIC_ENC_DEBLOCK,
+ INTEL_GENERIC_ENC_PREPROC,
+ INTEL_GENERIC_VDENC_ME,
+ INTEL_GENERIC_ENC_WP,
+ INTEL_GENERIC_ENC_SFD, // Static frame detection
+ INTEL_GENERIC_ENC_DYS
+} INTEL_GENERIC_ENC_OPERATION;
+
+typedef enum _INTEL_MEDIA_STATE_TYPE
+{
+ INTEL_MEDIA_STATE_OLP = 0,
+ INTEL_MEDIA_STATE_ENC_NORMAL = 1,
+ INTEL_MEDIA_STATE_ENC_PERFORMANCE = 2,
+ INTEL_MEDIA_STATE_ENC_QUALITY = 3,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_DIST = 4,
+ INTEL_MEDIA_STATE_32X_SCALING = 5,
+ INTEL_MEDIA_STATE_16X_SCALING = 6,
+ INTEL_MEDIA_STATE_4X_SCALING = 7,
+ INTEL_MEDIA_STATE_32X_ME = 8,
+ INTEL_MEDIA_STATE_16X_ME = 9,
+ INTEL_MEDIA_STATE_4X_ME = 10,
+ INTEL_MEDIA_STATE_BRC_INIT_RESET = 11,
+ INTEL_MEDIA_STATE_BRC_UPDATE = 12,
+ INTEL_MEDIA_STATE_BRC_BLOCK_COPY = 13,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P1 = 14,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P2 = 15,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_CHROMA = 16,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_LUMA = 17,
+ INTEL_MEDIA_STATE_MPU_FHB = 18,
+ INTEL_MEDIA_STATE_TPU_FHB = 19,
+ INTEL_MEDIA_STATE_PA_COPY = 20,
+ INTEL_MEDIA_STATE_PL2_COPY = 21,
+ INTEL_MEDIA_STATE_ENC_WIDI = 22,
+ INTEL_MEDIA_STATE_2X_SCALING = 23,
+ INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION = 24,
+ INTEL_MEDIA_STATE_16x16_PU_SAD = 25,
+ INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION = 26,
+ INTEL_MEDIA_STATE_8x8_PU = 27,
+ INTEL_MEDIA_STATE_8x8_PU_FMODE = 28,
+ INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK = 29,
+ INTEL_MEDIA_STATE_HEVC_B_MBENC = 30,
+ INTEL_MEDIA_STATE_RESET_VLINE_STRIDE = 31,
+ INTEL_MEDIA_STATE_HEVC_B_PAK = 32,
+ INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE = 33,
+ INTEL_MEDIA_STATE_ME_VDENC_STREAMIN = 34,
+ INTEL_MEDIA_STATE_VP9_ENC_I_32x32 = 35,
+ INTEL_MEDIA_STATE_VP9_ENC_I_16x16 = 36,
+ INTEL_MEDIA_STATE_VP9_ENC_P = 37,
+ INTEL_MEDIA_STATE_VP9_ENC_TX = 38,
+ INTEL_MEDIA_STATE_VP9_DYS = 39,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_RECON = 40,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_RECON = 41,
+ INTEL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK = 42,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK = 43,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK = 44,
+ INTEL_MEDIA_STATE_VP9_PAK_MC_PRED = 45,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON = 46,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON_32x32 = 47,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON = 48,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON = 49,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON = 50,
+ INTEL_MEDIA_STATE_PREPROC = 51,
+ INTEL_MEDIA_STATE_ENC_WP = 52,
+ INTEL_MEDIA_STATE_HEVC_I_MBENC = 53,
+ INTEL_MEDIA_STATE_CSC_DS_COPY = 54,
+ INTEL_MEDIA_STATE_2X_4X_SCALING = 55,
+ INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC = 56,
+ INTEL_MEDIA_STATE_MB_BRC_UPDATE = 57,
+ INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION = 58,
+ INTEL_MEDIA_STATE_HEVC_ROI = 59,
+ INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT = 60,
+ INTEL_NUM_MEDIA_STATES = 61
+} INTEL_MEDIA_STATE_TYPE;
+
+struct encoder_kernel_parameter
+{
+ unsigned int curbe_size;
+ unsigned int inline_data_size;
+ unsigned int sampler_size;
+};
+
+struct encoder_scoreboard_parameter
+{
+ unsigned int mask;
+ unsigned int type;
+ unsigned int enable;
+ unsigned int walkpat_flag;
+};
+
+
+/*
+ME related defines
+*/
+#define INTEL_ENC_HME_4x 0
+#define INTEL_ENC_HME_16x 1
+#define INTEL_ENC_HME_32x 2
+
+/*
+ the definition for rate control
+*/
+#define GENERIC_BRC_SEQ 0x01
+#define GENERIC_BRC_HRD 0x02
+#define GENERIC_BRC_RC 0x04
+#define GENERIC_BRC_FR 0x08
+#define GENERIC_BRC_FAILURE (1 << 31)
+
+enum INTEL_ENC_KERNAL_MODE
+{
+ INTEL_ENC_KERNEL_QUALITY = 0,
+ INTEL_ENC_KERNEL_NORMAL,
+ INTEL_ENC_KERNEL_PERFORMANCE
+};
+
+enum INTEL_ENC_PRESET_MODE
+{
+ INTEL_PRESET_UNKNOWN = 0,
+ INTEL_PRESET_BEST_QUALITY = 1,
+ INTEL_PRESET_HI_QUALITY = 2,
+ INTEL_PRESET_OPT_QUALITY = 3,
+ INTEL_PRESET_OK_QUALITY = 5,
+ INTEL_PRESET_NO_SPEED = 1,
+ INTEL_PRESET_OPT_SPEED = 3,
+ INTEL_PRESET_RT_SPEED = 4,
+ INTEL_PRESET_HI_SPEED = 6,
+ INTEL_PRESET_BEST_SPEED = 7,
+ INTEL_PRESET_LOW_LATENCY = 0x10,
+ INTEL_PRESET_MULTIPASS = 0x20
+};
+/*
+ the definition for encoder status
+*/
+struct encoder_status
+{
+ uint32_t bs_byte_count;
+ uint32_t image_status_ctrl;
+ uint32_t media_index;
+};
+
+struct encoder_status_buffer_internal
+{
+ uint32_t bs_byte_count_offset;
+ uint32_t reserved[15];
+
+ uint32_t image_status_ctrl_offset;
+
+ uint32_t bs_frame_reg_offset;
+ uint32_t image_status_ctrl_reg_offset;
+ dri_bo *bo;
+ uint32_t status_buffer_size;
+ uint32_t base_offset;
+
+ uint32_t media_index_offset;
+};
+
+struct {
+ struct i965_gpe_resource res;
+ uint32_t base_offset;
+ uint32_t size;
+ uint32_t bytes_per_frame_offset;
+} status_bffuer;
+
+/*
+ the definition for encoder VME/PAK context
+*/
+
+
+struct generic_encoder_context
+{
+ //scoreboard
+ uint32_t use_hw_scoreboard;
+ uint32_t use_hw_non_stalling_scoreboard;
+ //input surface
+ struct i965_gpe_resource res_uncompressed_input_surface;
+ //reconstructed surface
+ struct i965_gpe_resource res_reconstructed_surface;
+ //output bitstream
+ struct {
+ struct i965_gpe_resource res;
+ uint32_t start_offset;
+ uint32_t end_offset;
+ } compressed_bitstream;
+
+ //curbe set function pointer
+ void (*pfn_set_curbe_scaling2x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_scaling4x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_me)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_mbenc)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_init_reset)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_frame_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_mb_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_sfd)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_wp)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ //surface set function pointer
+ void (*pfn_send_scaling_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_me_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_mbenc_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_init_reset_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_frame_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_mb_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_sfd_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_wp_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+
+
+};
+/*
+ the definition for encoder codec state
+*/
+
+struct generic_enc_codec_state {
+
+ //generic related
+ int32_t kernel_mode;
+ int32_t preset;
+ int32_t seq_frame_number;
+ int32_t total_frame_number;
+ int32_t herder_bytes_inserted;
+ uint8_t frame_type;
+ bool first_frame;
+
+ // original width/height
+ uint32_t frame_width_in_pixel;
+ uint32_t frame_height_in_pixel;
+ uint32_t frame_width_in_mbs;
+ uint32_t frame_height_in_mbs;
+
+ //scaling related
+ uint32_t frame_width_2x;
+ uint32_t frame_height_2x;
+ uint32_t downscaled_width_2x_in_mb;
+ uint32_t downscaled_height_2x_in_mb;
+ uint32_t frame_width_4x;
+ uint32_t frame_height_4x;
+ uint32_t frame_width_16x;
+ uint32_t frame_height_16x;
+ uint32_t frame_width_32x;
+ uint32_t frame_height_32x;
+ uint32_t downscaled_width_4x_in_mb;
+ uint32_t downscaled_height_4x_in_mb;
+ uint32_t downscaled_width_16x_in_mb;
+ uint32_t downscaled_height_16x_in_mb;
+ uint32_t downscaled_width_32x_in_mb;
+ uint32_t downscaled_height_32x_in_mb;
+
+ // ME related
+ uint32_t hme_supported:1;
+ uint32_t b16xme_supported:1;
+ uint32_t b32xme_supported:1;
+ uint32_t hme_enabled:1;
+ uint32_t b16xme_enabled:1;
+ uint32_t b32xme_enabled:1;
+ uint32_t brc_distortion_buffer_supported:1;
+ uint32_t brc_constant_buffer_supported:1;
+ uint32_t hme_reserved:24;
+
+ //BRC related
+ uint32_t frame_rate;
+
+ uint32_t brc_allocated:1;
+ uint32_t brc_inited:1;
+ uint32_t brc_need_reset:1;
+ uint32_t is_low_delay:1;
+ uint32_t brc_enabled:1;
+ uint32_t internal_rate_mode:4;
+ uint32_t curr_pak_pass:4;
+ uint32_t num_pak_passes:4;
+ uint32_t is_first_pass:1;
+ uint32_t is_last_pass:1;
+ uint32_t mb_brc_enabled:1;
+ uint32_t brc_roi_enable:1;
+ uint32_t brc_dirty_roi_enable:1;
+ uint32_t skip_frame_enbale:1;
+ uint32_t brc_reserved:9;
+
+ uint32_t target_bit_rate;
+ uint32_t max_bit_rate;
+ uint32_t min_bit_rate;
+ uint64_t init_vbv_buffer_fullness_in_bit;
+ uint64_t vbv_buffer_size_in_bit;
+ uint32_t frames_per_100s;
+ uint32_t gop_size;
+ uint32_t gop_ref_distance;
+ uint32_t brc_target_size;
+ uint32_t brc_mode;
+ double brc_init_current_target_buf_full_in_bits;
+ double brc_init_reset_input_bits_per_frame;
+ uint32_t brc_init_reset_buf_size_in_bits;
+ uint32_t brc_init_previous_target_buf_full_in_bits;
+ int32_t window_size;
+ int32_t target_percentage;
+ uint16_t avbr_curracy;
+ uint16_t avbr_convergence;
+
+ //skip frame enbale
+ uint32_t num_skip_frames;
+ uint32_t size_skip_frames;
+
+ // ROI related
+ uint32_t dirty_num_roi;
+ uint32_t num_roi;
+ uint32_t max_delta_qp;
+ uint32_t min_delta_qp;
+ struct intel_roi roi[3];
+
+};
+
+/*
+ by now VME and PAK use the same context. it will bind the ctx according to the codec and platform, also vdenc and non-vdenc
+*/
+struct encoder_vme_mfc_context {
+ int32_t codec_id;
+ void * generic_enc_ctx;
+ void * private_enc_ctx; //pointer to the specific enc_ctx
+ void * generic_enc_state;
+ void * private_enc_state; //pointer to the specific enc_state
+};
+
+#endif /* _I965_COMMON_ENCODER_H */
\ No newline at end of file
--
2.7.4
Zhao Yakui
2017-01-17 01:05:33 UTC
Permalink
Post by Pengfei Qu
add context init function for AVC encoder
---
src/i965_encoder_api.h | 47 ++++
src/i965_encoder_common.c | 124 +++++++++++
src/i965_encoder_common.h | 533 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 704 insertions(+)
create mode 100755 src/i965_encoder_api.h
create mode 100755 src/i965_encoder_common.c
create mode 100755 src/i965_encoder_common.h
diff --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h
new file mode 100755
index 0000000..ebb0edc
--- /dev/null
+++ b/src/i965_encoder_api.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+
+#ifndef _I965_ENCODER_API_H_
+#define _I965_ENCODER_API_H_
+
+#include<va/va.h>
+
+struct intel_encoder_context;
+struct hw_context;
+
+/* H264/AVC */
+extern Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
+
+extern Bool
+gen9_avc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
+
+extern VAStatus
+gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct hw_context *hw_context);
+
+#endif // _I965_ENCODER_API_H_
diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c
new file mode 100755
index 0000000..930aba9
--- /dev/null
+++ b/src/i965_encoder_common.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ *
+ */
+#include<stdio.h>
+#include<string.h>
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+#include "i965_encoder_common.h"
+#include "i965_gpe_utils.h"
+
+
+const unsigned int table_enc_search_path[2][8][16] =
+{
+ // I-Frame& P-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101,
+ 0x01010101, 0x11010101, 0x01010101, 0x00010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding P frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ },
+ // B-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding B frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ }
+};
\ No newline at end of file
diff --git a/src/i965_encoder_common.h b/src/i965_encoder_common.h
new file mode 100755
index 0000000..bffbd8f
--- /dev/null
+++ b/src/i965_encoder_common.h
@@ -0,0 +1,533 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ *
+ */
+
+#ifndef _I965_COMMON_ENCODER_H
+#define _I965_COMMON_ENCODER_H
+
+#include<drm.h>
+#include<i915_drm.h>
+#include<intel_bufmgr.h>
+
+#include<va/va.h>
+#include "i965_encoder.h"
+#include "i965_gpe_utils.h"
+//#include "gen9_avc_encoder.h"
+
+struct encode_state;
+struct intel_encoder_context;
+
+/*
+ this file define the common structure for encoder, such as H264/H265/VP8/VP9
+*/
+
+#define INTEL_BRC_NONE 0
+#define INTEL_BRC_CBR 1
+#define INTEL_BRC_VBR 2
+#define INTEL_BRC_CQP 3
+#define INTEL_BRC_AVBR 4
+
+#define INTEL_BRC_INIT_FLAG_CBR 0x0010,
+#define INTEL_BRC_INIT_FLAG_VBR 0x0020,
+#define INTEL_BRC_INIT_FLAG_AVBR 0x0040,
+#define INTEL_BRC_INIT_FLAG_CQL 0x0080,
+#define INTEL_BRC_INIT_FLAG_FIELD_PIC 0x0100,
+#define INTEL_BRC_INIT_FLAG_ICQ 0x0200,
+#define INTEL_BRC_INIT_FLAG_VCM 0x0400,
+#define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
+#define INTEL_BRC_INIT_FLAG_QVBR 0x4000,
+#define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC 0x8000
+
+
+#define INTEL_BRC_UPDATE_FLAG_FIELD 0x01,
+#define INTEL_BRC_UPDATE_FLAG_MBAFF (0x01<< 1),
+#define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD (0x01<< 2),
+#define INTEL_BRC_UPDATE_FLAG_ACTUALQP (0x01<< 6),
+#define INTEL_BRC_UPDATE_FLAG_REFERENCE (0x01<< 7)
+
+#define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT 48
+
+extern const unsigned int table_enc_search_path[2][8][16];
+
+// BRC Flag in BRC Init Kernel
+typedef enum _INTEL_ENCODE_BRCINIT_FLAG
+{
+ INTEL_ENCODE_BRCINIT_ISCBR = 0x0010,
+ INTEL_ENCODE_BRCINIT_ISVBR = 0x0020,
+ INTEL_ENCODE_BRCINIT_ISAVBR = 0x0040,
+ INTEL_ENCODE_BRCINIT_ISCQL = 0x0080,
+ INTEL_ENCODE_BRCINIT_FIELD_PIC = 0x0100,
+ INTEL_ENCODE_BRCINIT_ISICQ = 0x0200,
+ INTEL_ENCODE_BRCINIT_ISVCM = 0x0400,
+ INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE = 0x2000,
+ INTEL_ENCODE_BRCINIT_ISQVBR = 0x4000,
+ INTEL_ENCODE_BRCINIT_DISABLE_MBBRC = 0x8000
+} INTEL_ENCODE_BRCINIT_FLAG;
+
+// BRC Flag in BRC Update Kernel
+typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG
+{
+ INTEL_ENCODE_BRCUPDATE_IS_FIELD = 0x01,
+ INTEL_ENCODE_BRCUPDATE_IS_MBAFF = (0x01<< 1),
+ INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD = (0x01<< 2),
+ INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP = (0x01<< 6),
+ INTEL_ENCODE_BRCUPDATE_IS_REFERENCE = (0x01<< 7)
+} INTEL_ENCODE_BRCUPDATE_FLAG;
+
+/*
+kernel operation related defines
+*/
+typedef enum _INTEL_GENERIC_ENC_OPERATION
+{
+ INTEL_GENERIC_ENC_SCALING4X = 0,
+ INTEL_GENERIC_ENC_SCALING2X,
+ INTEL_GENERIC_ENC_ME,
+ INTEL_GENERIC_ENC_BRC,
+ INTEL_GENERIC_ENC_MBENC,
+ INTEL_GENERIC_ENC_MBENC_WIDI,
+ INTEL_GENERIC_ENC_RESETVLINESTRIDE,
+ INTEL_GENERIC_ENC_MC,
+ INTEL_GENERIC_ENC_MBPAK,
+ INTEL_GENERIC_ENC_DEBLOCK,
+ INTEL_GENERIC_ENC_PREPROC,
+ INTEL_GENERIC_VDENC_ME,
+ INTEL_GENERIC_ENC_WP,
+ INTEL_GENERIC_ENC_SFD, // Static frame detection
+ INTEL_GENERIC_ENC_DYS
+} INTEL_GENERIC_ENC_OPERATION;
+
+typedef enum _INTEL_MEDIA_STATE_TYPE
+{
+ INTEL_MEDIA_STATE_OLP = 0,
+ INTEL_MEDIA_STATE_ENC_NORMAL = 1,
+ INTEL_MEDIA_STATE_ENC_PERFORMANCE = 2,
+ INTEL_MEDIA_STATE_ENC_QUALITY = 3,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_DIST = 4,
+ INTEL_MEDIA_STATE_32X_SCALING = 5,
+ INTEL_MEDIA_STATE_16X_SCALING = 6,
+ INTEL_MEDIA_STATE_4X_SCALING = 7,
+ INTEL_MEDIA_STATE_32X_ME = 8,
+ INTEL_MEDIA_STATE_16X_ME = 9,
+ INTEL_MEDIA_STATE_4X_ME = 10,
+ INTEL_MEDIA_STATE_BRC_INIT_RESET = 11,
+ INTEL_MEDIA_STATE_BRC_UPDATE = 12,
+ INTEL_MEDIA_STATE_BRC_BLOCK_COPY = 13,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P1 = 14,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P2 = 15,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_CHROMA = 16,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_LUMA = 17,
+ INTEL_MEDIA_STATE_MPU_FHB = 18,
+ INTEL_MEDIA_STATE_TPU_FHB = 19,
+ INTEL_MEDIA_STATE_PA_COPY = 20,
+ INTEL_MEDIA_STATE_PL2_COPY = 21,
+ INTEL_MEDIA_STATE_ENC_WIDI = 22,
+ INTEL_MEDIA_STATE_2X_SCALING = 23,
+ INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION = 24,
+ INTEL_MEDIA_STATE_16x16_PU_SAD = 25,
+ INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION = 26,
+ INTEL_MEDIA_STATE_8x8_PU = 27,
+ INTEL_MEDIA_STATE_8x8_PU_FMODE = 28,
+ INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK = 29,
+ INTEL_MEDIA_STATE_HEVC_B_MBENC = 30,
+ INTEL_MEDIA_STATE_RESET_VLINE_STRIDE = 31,
+ INTEL_MEDIA_STATE_HEVC_B_PAK = 32,
+ INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE = 33,
+ INTEL_MEDIA_STATE_ME_VDENC_STREAMIN = 34,
+ INTEL_MEDIA_STATE_VP9_ENC_I_32x32 = 35,
+ INTEL_MEDIA_STATE_VP9_ENC_I_16x16 = 36,
+ INTEL_MEDIA_STATE_VP9_ENC_P = 37,
+ INTEL_MEDIA_STATE_VP9_ENC_TX = 38,
+ INTEL_MEDIA_STATE_VP9_DYS = 39,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_RECON = 40,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_RECON = 41,
+ INTEL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK = 42,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK = 43,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK = 44,
+ INTEL_MEDIA_STATE_VP9_PAK_MC_PRED = 45,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON = 46,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON_32x32 = 47,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON = 48,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON = 49,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON = 50,
+ INTEL_MEDIA_STATE_PREPROC = 51,
+ INTEL_MEDIA_STATE_ENC_WP = 52,
+ INTEL_MEDIA_STATE_HEVC_I_MBENC = 53,
+ INTEL_MEDIA_STATE_CSC_DS_COPY = 54,
+ INTEL_MEDIA_STATE_2X_4X_SCALING = 55,
+ INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC = 56,
+ INTEL_MEDIA_STATE_MB_BRC_UPDATE = 57,
+ INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION = 58,
+ INTEL_MEDIA_STATE_HEVC_ROI = 59,
+ INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT = 60,
+ INTEL_NUM_MEDIA_STATES = 61
+} INTEL_MEDIA_STATE_TYPE;
+
+struct encoder_kernel_parameter
+{
+ unsigned int curbe_size;
+ unsigned int inline_data_size;
+ unsigned int sampler_size;
+};
+
+struct encoder_scoreboard_parameter
+{
+ unsigned int mask;
+ unsigned int type;
+ unsigned int enable;
+ unsigned int walkpat_flag;
+};
+
+
+/*
+ME related defines
+*/
+#define INTEL_ENC_HME_4x 0
+#define INTEL_ENC_HME_16x 1
+#define INTEL_ENC_HME_32x 2
+
+/*
+ the definition for rate control
+*/
+#define GENERIC_BRC_SEQ 0x01
+#define GENERIC_BRC_HRD 0x02
+#define GENERIC_BRC_RC 0x04
+#define GENERIC_BRC_FR 0x08
+#define GENERIC_BRC_FAILURE (1<< 31)
+
+enum INTEL_ENC_KERNAL_MODE
+{
+ INTEL_ENC_KERNEL_QUALITY = 0,
+ INTEL_ENC_KERNEL_NORMAL,
+ INTEL_ENC_KERNEL_PERFORMANCE
+};
+
+enum INTEL_ENC_PRESET_MODE
+{
+ INTEL_PRESET_UNKNOWN = 0,
+ INTEL_PRESET_BEST_QUALITY = 1,
+ INTEL_PRESET_HI_QUALITY = 2,
+ INTEL_PRESET_OPT_QUALITY = 3,
+ INTEL_PRESET_OK_QUALITY = 5,
+ INTEL_PRESET_NO_SPEED = 1,
+ INTEL_PRESET_OPT_SPEED = 3,
+ INTEL_PRESET_RT_SPEED = 4,
+ INTEL_PRESET_HI_SPEED = 6,
+ INTEL_PRESET_BEST_SPEED = 7,
+ INTEL_PRESET_LOW_LATENCY = 0x10,
+ INTEL_PRESET_MULTIPASS = 0x20
+};
The following two definitions are codec-specific.
It varies on the different codec. Even for the same codec, it varies on
the different platforms.
So I don't think that it is worth being added into the common structure.
Post by Pengfei Qu
+/*
+ the definition for encoder status
+*/
+struct encoder_status
+{
+ uint32_t bs_byte_count;
+ uint32_t image_status_ctrl;
+ uint32_t media_index;
+};
+
+struct encoder_status_buffer_internal
+{
+ uint32_t bs_byte_count_offset;
+ uint32_t reserved[15];
+
+ uint32_t image_status_ctrl_offset;
+
+ uint32_t bs_frame_reg_offset;
+ uint32_t image_status_ctrl_reg_offset;
+ dri_bo *bo;
+ uint32_t status_buffer_size;
+ uint32_t base_offset;
+
+ uint32_t media_index_offset;
+};
+
+struct {
+ struct i965_gpe_resource res;
+ uint32_t base_offset;
+ uint32_t size;
+ uint32_t bytes_per_frame_offset;
+} status_bffuer;
+
+/*
+ the definition for encoder VME/PAK context
+*/
+
The following definition has some duplicated definition with that in
intel_encoder_context.

And the intel_encoder_context/generic_encoder_context are a little
confusing.

At the same time the defined callback function table is also codec-specific.
It will be better that it is defined per codec.
Post by Pengfei Qu
+
+struct generic_encoder_context
+{
+ //scoreboard
+ uint32_t use_hw_scoreboard;
+ uint32_t use_hw_non_stalling_scoreboard;
+ //input surface
+ struct i965_gpe_resource res_uncompressed_input_surface;
+ //reconstructed surface
+ struct i965_gpe_resource res_reconstructed_surface;
+ //output bitstream
+ struct {
+ struct i965_gpe_resource res;
+ uint32_t start_offset;
+ uint32_t end_offset;
+ } compressed_bitstream;
+
+ //curbe set function pointer
+ void (*pfn_set_curbe_scaling2x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_scaling4x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_me)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_mbenc)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_init_reset)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_frame_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_mb_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_sfd)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_wp)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ //surface set function pointer
+ void (*pfn_send_scaling_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_me_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_mbenc_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_init_reset_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_frame_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_mb_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_sfd_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_wp_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+
+
+};
+/*
+ the definition for encoder codec state
+*/
+
+struct generic_enc_codec_state {
+
+ //generic related
+ int32_t kernel_mode;
+ int32_t preset;
+ int32_t seq_frame_number;
+ int32_t total_frame_number;
+ int32_t herder_bytes_inserted;
+ uint8_t frame_type;
+ bool first_frame;
+
+ // original width/height
+ uint32_t frame_width_in_pixel;
+ uint32_t frame_height_in_pixel;
+ uint32_t frame_width_in_mbs;
+ uint32_t frame_height_in_mbs;
+
+ //scaling related
+ uint32_t frame_width_2x;
+ uint32_t frame_height_2x;
+ uint32_t downscaled_width_2x_in_mb;
+ uint32_t downscaled_height_2x_in_mb;
+ uint32_t frame_width_4x;
+ uint32_t frame_height_4x;
+ uint32_t frame_width_16x;
+ uint32_t frame_height_16x;
+ uint32_t frame_width_32x;
+ uint32_t frame_height_32x;
+ uint32_t downscaled_width_4x_in_mb;
+ uint32_t downscaled_height_4x_in_mb;
+ uint32_t downscaled_width_16x_in_mb;
+ uint32_t downscaled_height_16x_in_mb;
+ uint32_t downscaled_width_32x_in_mb;
+ uint32_t downscaled_height_32x_in_mb;
+
+ // ME related
+ uint32_t hme_supported:1;
+ uint32_t b16xme_supported:1;
+ uint32_t b32xme_supported:1;
+ uint32_t hme_enabled:1;
+ uint32_t b16xme_enabled:1;
+ uint32_t b32xme_enabled:1;
+ uint32_t brc_distortion_buffer_supported:1;
+ uint32_t brc_constant_buffer_supported:1;
+ uint32_t hme_reserved:24;
+
+ //BRC related
+ uint32_t frame_rate;
+
+ uint32_t brc_allocated:1;
+ uint32_t brc_inited:1;
+ uint32_t brc_need_reset:1;
+ uint32_t is_low_delay:1;
+ uint32_t brc_enabled:1;
+ uint32_t internal_rate_mode:4;
+ uint32_t curr_pak_pass:4;
+ uint32_t num_pak_passes:4;
+ uint32_t is_first_pass:1;
+ uint32_t is_last_pass:1;
+ uint32_t mb_brc_enabled:1;
+ uint32_t brc_roi_enable:1;
+ uint32_t brc_dirty_roi_enable:1;
+ uint32_t skip_frame_enbale:1;
+ uint32_t brc_reserved:9;
+
+ uint32_t target_bit_rate;
+ uint32_t max_bit_rate;
+ uint32_t min_bit_rate;
+ uint64_t init_vbv_buffer_fullness_in_bit;
+ uint64_t vbv_buffer_size_in_bit;
+ uint32_t frames_per_100s;
+ uint32_t gop_size;
+ uint32_t gop_ref_distance;
+ uint32_t brc_target_size;
+ uint32_t brc_mode;
+ double brc_init_current_target_buf_full_in_bits;
+ double brc_init_reset_input_bits_per_frame;
+ uint32_t brc_init_reset_buf_size_in_bits;
+ uint32_t brc_init_previous_target_buf_full_in_bits;
+ int32_t window_size;
+ int32_t target_percentage;
+ uint16_t avbr_curracy;
+ uint16_t avbr_convergence;
+
+ //skip frame enbale
+ uint32_t num_skip_frames;
+ uint32_t size_skip_frames;
+
+ // ROI related
+ uint32_t dirty_num_roi;
+ uint32_t num_roi;
+ uint32_t max_delta_qp;
+ uint32_t min_delta_qp;
+ struct intel_roi roi[3];
+
+};
+
+/*
+ by now VME and PAK use the same context. it will bind the ctx according to the codec and platform, also vdenc and non-vdenc
+*/
+struct encoder_vme_mfc_context {
+ int32_t codec_id;
+ void * generic_enc_ctx;
+ void * private_enc_ctx; //pointer to the specific enc_ctx
+ void * generic_enc_state;
+ void * private_enc_state; //pointer to the specific enc_state
+};
+
+#endif /* _I965_COMMON_ENCODER_H */
\ No newline at end of file
Qu, Pengfei
2017-01-18 11:34:12 UTC
Permalink
-----Original Message-----
From: Zhao, Yakui
Sent: Tuesday, January 17, 2017 9:06 AM
To: Qu, Pengfei <***@intel.com>
Cc: ***@lists.freedesktop.org
Subject: Re: [Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC encoder
Post by Pengfei Qu
add context init function for AVC encoder
---
src/i965_encoder_api.h | 47 ++++
src/i965_encoder_common.c | 124 +++++++++++
src/i965_encoder_common.h | 533 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 704 insertions(+)
create mode 100755 src/i965_encoder_api.h
create mode 100755 src/i965_encoder_common.c
create mode 100755 src/i965_encoder_common.h
diff --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h new file
mode 100755 index 0000000..ebb0edc
--- /dev/null
+++ b/src/i965_encoder_api.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction,
+including
+ * without limitation the rights to use, copy, modify, merge,
+publish,
+ * distribute, sub license, and/or sell copies of the Software, and
+to
+ * permit persons to whom the Software is furnished to do so, subject
+to
+ *
+ * The above copyright notice and this permission notice (including
+the
+ * next paragraph) shall be included in all copies or substantial
+portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
+FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+
+#ifndef _I965_ENCODER_API_H_
+#define _I965_ENCODER_API_H_
+
+#include<va/va.h>
+
+struct intel_encoder_context;
+struct hw_context;
+
+/* H264/AVC */
+extern Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct
+intel_encoder_context *encoder_context);
+
+extern Bool
+gen9_avc_pak_context_init(VADriverContextP ctx, struct
+intel_encoder_context *encoder_context);
+
+extern VAStatus
+gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct
+hw_context *hw_context);
+
+#endif // _I965_ENCODER_API_H_
diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c new
file mode 100755 index 0000000..930aba9
--- /dev/null
+++ b/src/i965_encoder_common.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction,
+including
+ * without limitation the rights to use, copy, modify, merge,
+publish,
+ * distribute, sub license, and/or sell copies of the Software, and
+to
+ * permit persons to whom the Software is furnished to do so, subject
+to
+ *
+ * The above copyright notice and this permission notice (including
+the
+ * next paragraph) shall be included in all copies or substantial
+portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
+FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ *
+ */
+#include<stdio.h>
+#include<string.h>
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+#include "i965_encoder_common.h"
+#include "i965_gpe_utils.h"
+
+
+const unsigned int table_enc_search_path[2][8][16] = {
+ // I-Frame& P-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101,
+ 0x01010101, 0x11010101, 0x01010101, 0x00010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding P frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ },
+ // B-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding B frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ }
+};
\ No newline at end of file
diff --git a/src/i965_encoder_common.h b/src/i965_encoder_common.h new
file mode 100755 index 0000000..bffbd8f
--- /dev/null
+++ b/src/i965_encoder_common.h
@@ -0,0 +1,533 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction,
+including
+ * without limitation the rights to use, copy, modify, merge,
+publish,
+ * distribute, sub license, and/or sell copies of the Software, and
+to
+ * permit persons to whom the Software is furnished to do so, subject
+to
+ *
+ * The above copyright notice and this permission notice (including
+the
+ * next paragraph) shall be included in all copies or substantial
+portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
+FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ *
+ */
+
+#ifndef _I965_COMMON_ENCODER_H
+#define _I965_COMMON_ENCODER_H
+
+#include<drm.h>
+#include<i915_drm.h>
+#include<intel_bufmgr.h>
+
+#include<va/va.h>
+#include "i965_encoder.h"
+#include "i965_gpe_utils.h"
+//#include "gen9_avc_encoder.h"
+
+struct encode_state;
+struct intel_encoder_context;
+
+/*
+ this file define the common structure for encoder, such as
+H264/H265/VP8/VP9 */
+
+#define INTEL_BRC_NONE 0
+#define INTEL_BRC_CBR 1
+#define INTEL_BRC_VBR 2
+#define INTEL_BRC_CQP 3
+#define INTEL_BRC_AVBR 4
+
+#define INTEL_BRC_INIT_FLAG_CBR 0x0010,
+#define INTEL_BRC_INIT_FLAG_VBR 0x0020,
+#define INTEL_BRC_INIT_FLAG_AVBR 0x0040,
+#define INTEL_BRC_INIT_FLAG_CQL 0x0080,
+#define INTEL_BRC_INIT_FLAG_FIELD_PIC 0x0100,
+#define INTEL_BRC_INIT_FLAG_ICQ 0x0200,
+#define INTEL_BRC_INIT_FLAG_VCM 0x0400,
+#define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
+#define INTEL_BRC_INIT_FLAG_QVBR 0x4000,
+#define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC 0x8000
+
+
+#define INTEL_BRC_UPDATE_FLAG_FIELD 0x01,
+#define INTEL_BRC_UPDATE_FLAG_MBAFF (0x01<< 1),
+#define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD (0x01<< 2),
+#define INTEL_BRC_UPDATE_FLAG_ACTUALQP (0x01<< 6),
+#define INTEL_BRC_UPDATE_FLAG_REFERENCE (0x01<< 7)
+
+#define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT 48
+
+extern const unsigned int table_enc_search_path[2][8][16];
+
+// BRC Flag in BRC Init Kernel
+typedef enum _INTEL_ENCODE_BRCINIT_FLAG {
+ INTEL_ENCODE_BRCINIT_ISCBR = 0x0010,
+ INTEL_ENCODE_BRCINIT_ISVBR = 0x0020,
+ INTEL_ENCODE_BRCINIT_ISAVBR = 0x0040,
+ INTEL_ENCODE_BRCINIT_ISCQL = 0x0080,
+ INTEL_ENCODE_BRCINIT_FIELD_PIC = 0x0100,
+ INTEL_ENCODE_BRCINIT_ISICQ = 0x0200,
+ INTEL_ENCODE_BRCINIT_ISVCM = 0x0400,
+ INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE = 0x2000,
+ INTEL_ENCODE_BRCINIT_ISQVBR = 0x4000,
+ INTEL_ENCODE_BRCINIT_DISABLE_MBBRC = 0x8000
+} INTEL_ENCODE_BRCINIT_FLAG;
+
+// BRC Flag in BRC Update Kernel
+typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG {
+ INTEL_ENCODE_BRCUPDATE_IS_FIELD = 0x01,
+ INTEL_ENCODE_BRCUPDATE_IS_MBAFF = (0x01<< 1),
+ INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD = (0x01<< 2),
+ INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP = (0x01<< 6),
+ INTEL_ENCODE_BRCUPDATE_IS_REFERENCE = (0x01<< 7)
+} INTEL_ENCODE_BRCUPDATE_FLAG;
+
+/*
+kernel operation related defines
+*/
+typedef enum _INTEL_GENERIC_ENC_OPERATION {
+ INTEL_GENERIC_ENC_SCALING4X = 0,
+ INTEL_GENERIC_ENC_SCALING2X,
+ INTEL_GENERIC_ENC_ME,
+ INTEL_GENERIC_ENC_BRC,
+ INTEL_GENERIC_ENC_MBENC,
+ INTEL_GENERIC_ENC_MBENC_WIDI,
+ INTEL_GENERIC_ENC_RESETVLINESTRIDE,
+ INTEL_GENERIC_ENC_MC,
+ INTEL_GENERIC_ENC_MBPAK,
+ INTEL_GENERIC_ENC_DEBLOCK,
+ INTEL_GENERIC_ENC_PREPROC,
+ INTEL_GENERIC_VDENC_ME,
+ INTEL_GENERIC_ENC_WP,
+ INTEL_GENERIC_ENC_SFD, // Static frame detection
+ INTEL_GENERIC_ENC_DYS
+} INTEL_GENERIC_ENC_OPERATION;
+
+typedef enum _INTEL_MEDIA_STATE_TYPE
+{
+ INTEL_MEDIA_STATE_OLP = 0,
+ INTEL_MEDIA_STATE_ENC_NORMAL = 1,
+ INTEL_MEDIA_STATE_ENC_PERFORMANCE = 2,
+ INTEL_MEDIA_STATE_ENC_QUALITY = 3,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_DIST = 4,
+ INTEL_MEDIA_STATE_32X_SCALING = 5,
+ INTEL_MEDIA_STATE_16X_SCALING = 6,
+ INTEL_MEDIA_STATE_4X_SCALING = 7,
+ INTEL_MEDIA_STATE_32X_ME = 8,
+ INTEL_MEDIA_STATE_16X_ME = 9,
+ INTEL_MEDIA_STATE_4X_ME = 10,
+ INTEL_MEDIA_STATE_BRC_INIT_RESET = 11,
+ INTEL_MEDIA_STATE_BRC_UPDATE = 12,
+ INTEL_MEDIA_STATE_BRC_BLOCK_COPY = 13,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P1 = 14,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P2 = 15,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_CHROMA = 16,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_LUMA = 17,
+ INTEL_MEDIA_STATE_MPU_FHB = 18,
+ INTEL_MEDIA_STATE_TPU_FHB = 19,
+ INTEL_MEDIA_STATE_PA_COPY = 20,
+ INTEL_MEDIA_STATE_PL2_COPY = 21,
+ INTEL_MEDIA_STATE_ENC_WIDI = 22,
+ INTEL_MEDIA_STATE_2X_SCALING = 23,
+ INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION = 24,
+ INTEL_MEDIA_STATE_16x16_PU_SAD = 25,
+ INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION = 26,
+ INTEL_MEDIA_STATE_8x8_PU = 27,
+ INTEL_MEDIA_STATE_8x8_PU_FMODE = 28,
+ INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK = 29,
+ INTEL_MEDIA_STATE_HEVC_B_MBENC = 30,
+ INTEL_MEDIA_STATE_RESET_VLINE_STRIDE = 31,
+ INTEL_MEDIA_STATE_HEVC_B_PAK = 32,
+ INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE = 33,
+ INTEL_MEDIA_STATE_ME_VDENC_STREAMIN = 34,
+ INTEL_MEDIA_STATE_VP9_ENC_I_32x32 = 35,
+ INTEL_MEDIA_STATE_VP9_ENC_I_16x16 = 36,
+ INTEL_MEDIA_STATE_VP9_ENC_P = 37,
+ INTEL_MEDIA_STATE_VP9_ENC_TX = 38,
+ INTEL_MEDIA_STATE_VP9_DYS = 39,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_RECON = 40,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_RECON = 41,
+ INTEL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK = 42,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK = 43,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK = 44,
+ INTEL_MEDIA_STATE_VP9_PAK_MC_PRED = 45,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON = 46,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON_32x32 = 47,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON = 48,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON = 49,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON = 50,
+ INTEL_MEDIA_STATE_PREPROC = 51,
+ INTEL_MEDIA_STATE_ENC_WP = 52,
+ INTEL_MEDIA_STATE_HEVC_I_MBENC = 53,
+ INTEL_MEDIA_STATE_CSC_DS_COPY = 54,
+ INTEL_MEDIA_STATE_2X_4X_SCALING = 55,
+ INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC = 56,
+ INTEL_MEDIA_STATE_MB_BRC_UPDATE = 57,
+ INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION = 58,
+ INTEL_MEDIA_STATE_HEVC_ROI = 59,
+ INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT = 60,
+ INTEL_NUM_MEDIA_STATES = 61
+} INTEL_MEDIA_STATE_TYPE;
+
+struct encoder_kernel_parameter
+{
+ unsigned int curbe_size;
+ unsigned int inline_data_size;
+ unsigned int sampler_size;
+};
+
+struct encoder_scoreboard_parameter
+{
+ unsigned int mask;
+ unsigned int type;
+ unsigned int enable;
+ unsigned int walkpat_flag;
+};
+
+
+/*
+ME related defines
+*/
+#define INTEL_ENC_HME_4x 0
+#define INTEL_ENC_HME_16x 1
+#define INTEL_ENC_HME_32x 2
+
+/*
+ the definition for rate control
+*/
+#define GENERIC_BRC_SEQ 0x01
+#define GENERIC_BRC_HRD 0x02
+#define GENERIC_BRC_RC 0x04
+#define GENERIC_BRC_FR 0x08
+#define GENERIC_BRC_FAILURE (1<< 31)
+
+enum INTEL_ENC_KERNAL_MODE
+{
+ INTEL_ENC_KERNEL_QUALITY = 0,
+ INTEL_ENC_KERNEL_NORMAL,
+ INTEL_ENC_KERNEL_PERFORMANCE
+};
+
+enum INTEL_ENC_PRESET_MODE
+{
+ INTEL_PRESET_UNKNOWN = 0,
+ INTEL_PRESET_BEST_QUALITY = 1,
+ INTEL_PRESET_HI_QUALITY = 2,
+ INTEL_PRESET_OPT_QUALITY = 3,
+ INTEL_PRESET_OK_QUALITY = 5,
+ INTEL_PRESET_NO_SPEED = 1,
+ INTEL_PRESET_OPT_SPEED = 3,
+ INTEL_PRESET_RT_SPEED = 4,
+ INTEL_PRESET_HI_SPEED = 6,
+ INTEL_PRESET_BEST_SPEED = 7,
+ INTEL_PRESET_LOW_LATENCY = 0x10,
+ INTEL_PRESET_MULTIPASS = 0x20
+};
The following two definitions are codec-specific.
It varies on the different codec. Even for the same codec, it varies on the different platforms.
So I don't think that it is worth being added into the common structure.
[Pengfei]this will cover more info for all codec and keep it here for future.
Post by Pengfei Qu
+/*
+ the definition for encoder status
+*/
+struct encoder_status
+{
+ uint32_t bs_byte_count;
+ uint32_t image_status_ctrl;
+ uint32_t media_index;
+};
+
+struct encoder_status_buffer_internal {
+ uint32_t bs_byte_count_offset;
+ uint32_t reserved[15];
+
+ uint32_t image_status_ctrl_offset;
+
+ uint32_t bs_frame_reg_offset;
+ uint32_t image_status_ctrl_reg_offset;
+ dri_bo *bo;
+ uint32_t status_buffer_size;
+ uint32_t base_offset;
+
+ uint32_t media_index_offset;
+};
+
+struct {
+ struct i965_gpe_resource res;
+ uint32_t base_offset;
+ uint32_t size;
+ uint32_t bytes_per_frame_offset;
+} status_bffuer;
+
+/*
+ the definition for encoder VME/PAK context */
+
The following definition has some duplicated definition with that in intel_encoder_context.

And the intel_encoder_context/generic_encoder_context are a little confusing.
[Pengfei] there is no duplication here and keep the structure define.

At the same time the defined callback function table is also codec-specific.
It will be better that it is defined per codec.
[Pengfei] here most call back are common for all codec and keep it here.
Post by Pengfei Qu
+
+struct generic_encoder_context
+{
+ //scoreboard
+ uint32_t use_hw_scoreboard;
+ uint32_t use_hw_non_stalling_scoreboard;
+ //input surface
+ struct i965_gpe_resource res_uncompressed_input_surface;
+ //reconstructed surface
+ struct i965_gpe_resource res_reconstructed_surface;
+ //output bitstream
+ struct {
+ struct i965_gpe_resource res;
+ uint32_t start_offset;
+ uint32_t end_offset;
+ } compressed_bitstream;
+
+ //curbe set function pointer
+ void (*pfn_set_curbe_scaling2x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_scaling4x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_me)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_mbenc)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_init_reset)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_frame_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_mb_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_sfd)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_wp)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ //surface set function pointer
+ void (*pfn_send_scaling_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_me_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_mbenc_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_init_reset_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_frame_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_mb_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_sfd_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_wp_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+
+
+};
+/*
+ the definition for encoder codec state */
+
+struct generic_enc_codec_state {
+
+ //generic related
+ int32_t kernel_mode;
+ int32_t preset;
+ int32_t seq_frame_number;
+ int32_t total_frame_number;
+ int32_t herder_bytes_inserted;
+ uint8_t frame_type;
+ bool first_frame;
+
+ // original width/height
+ uint32_t frame_width_in_pixel;
+ uint32_t frame_height_in_pixel;
+ uint32_t frame_width_in_mbs;
+ uint32_t frame_height_in_mbs;
+
+ //scaling related
+ uint32_t frame_width_2x;
+ uint32_t frame_height_2x;
+ uint32_t downscaled_width_2x_in_mb;
+ uint32_t downscaled_height_2x_in_mb;
+ uint32_t frame_width_4x;
+ uint32_t frame_height_4x;
+ uint32_t frame_width_16x;
+ uint32_t frame_height_16x;
+ uint32_t frame_width_32x;
+ uint32_t frame_height_32x;
+ uint32_t downscaled_width_4x_in_mb;
+ uint32_t downscaled_height_4x_in_mb;
+ uint32_t downscaled_width_16x_in_mb;
+ uint32_t downscaled_height_16x_in_mb;
+ uint32_t downscaled_width_32x_in_mb;
+ uint32_t downscaled_height_32x_in_mb;
+
+ // ME related
+ uint32_t hme_supported:1;
+ uint32_t b16xme_supported:1;
+ uint32_t b32xme_supported:1;
+ uint32_t hme_enabled:1;
+ uint32_t b16xme_enabled:1;
+ uint32_t b32xme_enabled:1;
+ uint32_t brc_distortion_buffer_supported:1;
+ uint32_t brc_constant_buffer_supported:1;
+ uint32_t hme_reserved:24;
+
+ //BRC related
+ uint32_t frame_rate;
+
+ uint32_t brc_allocated:1;
+ uint32_t brc_inited:1;
+ uint32_t brc_need_reset:1;
+ uint32_t is_low_delay:1;
+ uint32_t brc_enabled:1;
+ uint32_t internal_rate_mode:4;
+ uint32_t curr_pak_pass:4;
+ uint32_t num_pak_passes:4;
+ uint32_t is_first_pass:1;
+ uint32_t is_last_pass:1;
+ uint32_t mb_brc_enabled:1;
+ uint32_t brc_roi_enable:1;
+ uint32_t brc_dirty_roi_enable:1;
+ uint32_t skip_frame_enbale:1;
+ uint32_t brc_reserved:9;
+
+ uint32_t target_bit_rate;
+ uint32_t max_bit_rate;
+ uint32_t min_bit_rate;
+ uint64_t init_vbv_buffer_fullness_in_bit;
+ uint64_t vbv_buffer_size_in_bit;
+ uint32_t frames_per_100s;
+ uint32_t gop_size;
+ uint32_t gop_ref_distance;
+ uint32_t brc_target_size;
+ uint32_t brc_mode;
+ double brc_init_current_target_buf_full_in_bits;
+ double brc_init_reset_input_bits_per_frame;
+ uint32_t brc_init_reset_buf_size_in_bits;
+ uint32_t brc_init_previous_target_buf_full_in_bits;
+ int32_t window_size;
+ int32_t target_percentage;
+ uint16_t avbr_curracy;
+ uint16_t avbr_convergence;
+
+ //skip frame enbale
+ uint32_t num_skip_frames;
+ uint32_t size_skip_frames;
+
+ // ROI related
+ uint32_t dirty_num_roi;
+ uint32_t num_roi;
+ uint32_t max_delta_qp;
+ uint32_t min_delta_qp;
+ struct intel_roi roi[3];
+
+};
+
+/*
+ by now VME and PAK use the same context. it will bind the ctx
+according to the codec and platform, also vdenc and non-vdenc */
+struct encoder_vme_mfc_context {
+ int32_t codec_id;
+ void * generic_enc_ctx;
+ void * private_enc_ctx; //pointer to the specific enc_ctx
+ void * generic_enc_state;
+ void * private_enc_state; //pointer to the specific enc_state };
+
+#endif /* _I965_COMMON_ENCODER_H */
\ No newline at end of file
Zhao Yakui
2017-01-17 01:14:47 UTC
Permalink
Post by Pengfei Qu
add context init function for AVC encoder
More comments are added.
Post by Pengfei Qu
---
src/i965_encoder_api.h | 47 ++++
src/i965_encoder_common.c | 124 +++++++++++
src/i965_encoder_common.h | 533 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 704 insertions(+)
create mode 100755 src/i965_encoder_api.h
create mode 100755 src/i965_encoder_common.c
create mode 100755 src/i965_encoder_common.h
diff --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h
new file mode 100755
index 0000000..ebb0edc
--- /dev/null
+++ b/src/i965_encoder_api.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+
+#ifndef _I965_ENCODER_API_H_
+#define _I965_ENCODER_API_H_
+
+#include<va/va.h>
+
+struct intel_encoder_context;
+struct hw_context;
+
+/* H264/AVC */
+extern Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
+
+extern Bool
+gen9_avc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
+
+extern VAStatus
+gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct hw_context *hw_context);
+
+#endif // _I965_ENCODER_API_H_
diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c
new file mode 100755
index 0000000..930aba9
--- /dev/null
+++ b/src/i965_encoder_common.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ *
+ */
+#include<stdio.h>
+#include<string.h>
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+#include "i965_encoder_common.h"
+#include "i965_gpe_utils.h"
+
+
+const unsigned int table_enc_search_path[2][8][16] =
+{
+ // I-Frame& P-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101,
+ 0x01010101, 0x11010101, 0x01010101, 0x00010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding P frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ },
+ // B-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding B frames
Also MPEG2?
Post by Pengfei Qu
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ }
+};
\ No newline at end of file
diff --git a/src/i965_encoder_common.h b/src/i965_encoder_common.h
new file mode 100755
index 0000000..bffbd8f
--- /dev/null
+++ b/src/i965_encoder_common.h
@@ -0,0 +1,533 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ *
+ */
+
+#ifndef _I965_COMMON_ENCODER_H
+#define _I965_COMMON_ENCODER_H
+
+#include<drm.h>
+#include<i915_drm.h>
+#include<intel_bufmgr.h>
+
+#include<va/va.h>
+#include "i965_encoder.h"
+#include "i965_gpe_utils.h"
+//#include "gen9_avc_encoder.h"
+
+struct encode_state;
+struct intel_encoder_context;
+
+/*
+ this file define the common structure for encoder, such as H264/H265/VP8/VP9
+*/
+
+#define INTEL_BRC_NONE 0
+#define INTEL_BRC_CBR 1
+#define INTEL_BRC_VBR 2
+#define INTEL_BRC_CQP 3
+#define INTEL_BRC_AVBR 4
+
+#define INTEL_BRC_INIT_FLAG_CBR 0x0010,
+#define INTEL_BRC_INIT_FLAG_VBR 0x0020,
+#define INTEL_BRC_INIT_FLAG_AVBR 0x0040,
+#define INTEL_BRC_INIT_FLAG_CQL 0x0080,
+#define INTEL_BRC_INIT_FLAG_FIELD_PIC 0x0100,
+#define INTEL_BRC_INIT_FLAG_ICQ 0x0200,
+#define INTEL_BRC_INIT_FLAG_VCM 0x0400,
+#define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
+#define INTEL_BRC_INIT_FLAG_QVBR 0x4000,
+#define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC 0x8000
+
+
+#define INTEL_BRC_UPDATE_FLAG_FIELD 0x01,
+#define INTEL_BRC_UPDATE_FLAG_MBAFF (0x01<< 1),
+#define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD (0x01<< 2),
+#define INTEL_BRC_UPDATE_FLAG_ACTUALQP (0x01<< 6),
+#define INTEL_BRC_UPDATE_FLAG_REFERENCE (0x01<< 7)
+
+#define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT 48
+
+extern const unsigned int table_enc_search_path[2][8][16];
+
+// BRC Flag in BRC Init Kernel
+typedef enum _INTEL_ENCODE_BRCINIT_FLAG
+{
+ INTEL_ENCODE_BRCINIT_ISCBR = 0x0010,
+ INTEL_ENCODE_BRCINIT_ISVBR = 0x0020,
+ INTEL_ENCODE_BRCINIT_ISAVBR = 0x0040,
+ INTEL_ENCODE_BRCINIT_ISCQL = 0x0080,
+ INTEL_ENCODE_BRCINIT_FIELD_PIC = 0x0100,
+ INTEL_ENCODE_BRCINIT_ISICQ = 0x0200,
+ INTEL_ENCODE_BRCINIT_ISVCM = 0x0400,
+ INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE = 0x2000,
+ INTEL_ENCODE_BRCINIT_ISQVBR = 0x4000,
+ INTEL_ENCODE_BRCINIT_DISABLE_MBBRC = 0x8000
+} INTEL_ENCODE_BRCINIT_FLAG;
+
+// BRC Flag in BRC Update Kernel
+typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG
+{
+ INTEL_ENCODE_BRCUPDATE_IS_FIELD = 0x01,
+ INTEL_ENCODE_BRCUPDATE_IS_MBAFF = (0x01<< 1),
+ INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD = (0x01<< 2),
+ INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP = (0x01<< 6),
+ INTEL_ENCODE_BRCUPDATE_IS_REFERENCE = (0x01<< 7)
+} INTEL_ENCODE_BRCUPDATE_FLAG;
+
+/*
+kernel operation related defines
+*/
+typedef enum _INTEL_GENERIC_ENC_OPERATION
+{
+ INTEL_GENERIC_ENC_SCALING4X = 0,
+ INTEL_GENERIC_ENC_SCALING2X,
+ INTEL_GENERIC_ENC_ME,
+ INTEL_GENERIC_ENC_BRC,
+ INTEL_GENERIC_ENC_MBENC,
+ INTEL_GENERIC_ENC_MBENC_WIDI,
+ INTEL_GENERIC_ENC_RESETVLINESTRIDE,
+ INTEL_GENERIC_ENC_MC,
+ INTEL_GENERIC_ENC_MBPAK,
+ INTEL_GENERIC_ENC_DEBLOCK,
+ INTEL_GENERIC_ENC_PREPROC,
+ INTEL_GENERIC_VDENC_ME,
+ INTEL_GENERIC_ENC_WP,
+ INTEL_GENERIC_ENC_SFD, // Static frame detection
+ INTEL_GENERIC_ENC_DYS
+} INTEL_GENERIC_ENC_OPERATION;
+
+typedef enum _INTEL_MEDIA_STATE_TYPE
+{
+ INTEL_MEDIA_STATE_OLP = 0,
+ INTEL_MEDIA_STATE_ENC_NORMAL = 1,
+ INTEL_MEDIA_STATE_ENC_PERFORMANCE = 2,
+ INTEL_MEDIA_STATE_ENC_QUALITY = 3,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_DIST = 4,
+ INTEL_MEDIA_STATE_32X_SCALING = 5,
+ INTEL_MEDIA_STATE_16X_SCALING = 6,
+ INTEL_MEDIA_STATE_4X_SCALING = 7,
+ INTEL_MEDIA_STATE_32X_ME = 8,
+ INTEL_MEDIA_STATE_16X_ME = 9,
+ INTEL_MEDIA_STATE_4X_ME = 10,
+ INTEL_MEDIA_STATE_BRC_INIT_RESET = 11,
+ INTEL_MEDIA_STATE_BRC_UPDATE = 12,
+ INTEL_MEDIA_STATE_BRC_BLOCK_COPY = 13,
Hybrid is not used.
Post by Pengfei Qu
+ INTEL_MEDIA_STATE_HYBRID_PAK_P1 = 14,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P2 = 15,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_CHROMA = 16,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_LUMA = 17,
+ INTEL_MEDIA_STATE_MPU_FHB = 18,
+ INTEL_MEDIA_STATE_TPU_FHB = 19,
+ INTEL_MEDIA_STATE_PA_COPY = 20,
+ INTEL_MEDIA_STATE_PL2_COPY = 21,
+ INTEL_MEDIA_STATE_ENC_WIDI = 22,
+ INTEL_MEDIA_STATE_2X_SCALING = 23,
+ INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION = 24,
+ INTEL_MEDIA_STATE_16x16_PU_SAD = 25,
+ INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION = 26,
+ INTEL_MEDIA_STATE_8x8_PU = 27,
+ INTEL_MEDIA_STATE_8x8_PU_FMODE = 28,
+ INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK = 29,
+ INTEL_MEDIA_STATE_HEVC_B_MBENC = 30,
+ INTEL_MEDIA_STATE_RESET_VLINE_STRIDE = 31,
+ INTEL_MEDIA_STATE_HEVC_B_PAK = 32,
+ INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE = 33,
+ INTEL_MEDIA_STATE_ME_VDENC_STREAMIN = 34,
The following is defined for VP9. But it is never used.
Post by Pengfei Qu
+ INTEL_MEDIA_STATE_VP9_ENC_I_32x32 = 35,
+ INTEL_MEDIA_STATE_VP9_ENC_I_16x16 = 36,
+ INTEL_MEDIA_STATE_VP9_ENC_P = 37,
+ INTEL_MEDIA_STATE_VP9_ENC_TX = 38,
+ INTEL_MEDIA_STATE_VP9_DYS = 39,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_RECON = 40,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_RECON = 41,
+ INTEL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK = 42,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK = 43,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK = 44,
+ INTEL_MEDIA_STATE_VP9_PAK_MC_PRED = 45,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON = 46,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON_32x32 = 47,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON = 48,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON = 49,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON = 50,
+ INTEL_MEDIA_STATE_PREPROC = 51,
+ INTEL_MEDIA_STATE_ENC_WP = 52,
+ INTEL_MEDIA_STATE_HEVC_I_MBENC = 53,
+ INTEL_MEDIA_STATE_CSC_DS_COPY = 54,
+ INTEL_MEDIA_STATE_2X_4X_SCALING = 55,
+ INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC = 56,
+ INTEL_MEDIA_STATE_MB_BRC_UPDATE = 57,
+ INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION = 58,
+ INTEL_MEDIA_STATE_HEVC_ROI = 59,
+ INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT = 60,
+ INTEL_NUM_MEDIA_STATES = 61
+} INTEL_MEDIA_STATE_TYPE;
+
+struct encoder_kernel_parameter
+{
+ unsigned int curbe_size;
+ unsigned int inline_data_size;
+ unsigned int sampler_size;
+};
+
+struct encoder_scoreboard_parameter
+{
+ unsigned int mask;
+ unsigned int type;
+ unsigned int enable;
+ unsigned int walkpat_flag;
+};
+
+
+/*
+ME related defines
+*/
+#define INTEL_ENC_HME_4x 0
+#define INTEL_ENC_HME_16x 1
+#define INTEL_ENC_HME_32x 2
+
+/*
+ the definition for rate control
+*/
+#define GENERIC_BRC_SEQ 0x01
+#define GENERIC_BRC_HRD 0x02
+#define GENERIC_BRC_RC 0x04
+#define GENERIC_BRC_FR 0x08
+#define GENERIC_BRC_FAILURE (1<< 31)
+
+enum INTEL_ENC_KERNAL_MODE
+{
+ INTEL_ENC_KERNEL_QUALITY = 0,
+ INTEL_ENC_KERNEL_NORMAL,
+ INTEL_ENC_KERNEL_PERFORMANCE
+};
+
+enum INTEL_ENC_PRESET_MODE
+{
+ INTEL_PRESET_UNKNOWN = 0,
+ INTEL_PRESET_BEST_QUALITY = 1,
+ INTEL_PRESET_HI_QUALITY = 2,
+ INTEL_PRESET_OPT_QUALITY = 3,
+ INTEL_PRESET_OK_QUALITY = 5,
+ INTEL_PRESET_NO_SPEED = 1,
+ INTEL_PRESET_OPT_SPEED = 3,
+ INTEL_PRESET_RT_SPEED = 4,
+ INTEL_PRESET_HI_SPEED = 6,
+ INTEL_PRESET_BEST_SPEED = 7,
+ INTEL_PRESET_LOW_LATENCY = 0x10,
+ INTEL_PRESET_MULTIPASS = 0x20
+};
+/*
+ the definition for encoder status
+*/
+struct encoder_status
+{
+ uint32_t bs_byte_count;
+ uint32_t image_status_ctrl;
+ uint32_t media_index;
+};
+
+struct encoder_status_buffer_internal
+{
+ uint32_t bs_byte_count_offset;
+ uint32_t reserved[15];
+
+ uint32_t image_status_ctrl_offset;
+
+ uint32_t bs_frame_reg_offset;
+ uint32_t image_status_ctrl_reg_offset;
+ dri_bo *bo;
+ uint32_t status_buffer_size;
+ uint32_t base_offset;
+
+ uint32_t media_index_offset;
+};
+
+struct {
+ struct i965_gpe_resource res;
+ uint32_t base_offset;
+ uint32_t size;
+ uint32_t bytes_per_frame_offset;
+} status_bffuer;
+
+/*
+ the definition for encoder VME/PAK context
+*/
+
+
+struct generic_encoder_context
+{
+ //scoreboard
+ uint32_t use_hw_scoreboard;
+ uint32_t use_hw_non_stalling_scoreboard;
+ //input surface
+ struct i965_gpe_resource res_uncompressed_input_surface;
+ //reconstructed surface
+ struct i965_gpe_resource res_reconstructed_surface;
+ //output bitstream
+ struct {
+ struct i965_gpe_resource res;
+ uint32_t start_offset;
+ uint32_t end_offset;
+ } compressed_bitstream;
+
+ //curbe set function pointer
+ void (*pfn_set_curbe_scaling2x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_scaling4x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_me)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_mbenc)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_init_reset)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_frame_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_mb_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_sfd)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_wp)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ //surface set function pointer
+ void (*pfn_send_scaling_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_me_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_mbenc_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_init_reset_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_frame_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_mb_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_sfd_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_wp_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+
+
+};
+/*
+ the definition for encoder codec state
+*/
+
+struct generic_enc_codec_state {
+
+ //generic related
+ int32_t kernel_mode;
+ int32_t preset;
+ int32_t seq_frame_number;
+ int32_t total_frame_number;
+ int32_t herder_bytes_inserted;
+ uint8_t frame_type;
+ bool first_frame;
+
+ // original width/height
+ uint32_t frame_width_in_pixel;
+ uint32_t frame_height_in_pixel;
+ uint32_t frame_width_in_mbs;
+ uint32_t frame_height_in_mbs;
+
+ //scaling related
+ uint32_t frame_width_2x;
+ uint32_t frame_height_2x;
+ uint32_t downscaled_width_2x_in_mb;
+ uint32_t downscaled_height_2x_in_mb;
+ uint32_t frame_width_4x;
+ uint32_t frame_height_4x;
+ uint32_t frame_width_16x;
+ uint32_t frame_height_16x;
+ uint32_t frame_width_32x;
+ uint32_t frame_height_32x;
+ uint32_t downscaled_width_4x_in_mb;
+ uint32_t downscaled_height_4x_in_mb;
+ uint32_t downscaled_width_16x_in_mb;
+ uint32_t downscaled_height_16x_in_mb;
+ uint32_t downscaled_width_32x_in_mb;
+ uint32_t downscaled_height_32x_in_mb;
+
+ // ME related
+ uint32_t hme_supported:1;
+ uint32_t b16xme_supported:1;
+ uint32_t b32xme_supported:1;
+ uint32_t hme_enabled:1;
+ uint32_t b16xme_enabled:1;
+ uint32_t b32xme_enabled:1;
+ uint32_t brc_distortion_buffer_supported:1;
+ uint32_t brc_constant_buffer_supported:1;
+ uint32_t hme_reserved:24;
+
+ //BRC related
+ uint32_t frame_rate;
+
+ uint32_t brc_allocated:1;
+ uint32_t brc_inited:1;
+ uint32_t brc_need_reset:1;
+ uint32_t is_low_delay:1;
+ uint32_t brc_enabled:1;
+ uint32_t internal_rate_mode:4;
+ uint32_t curr_pak_pass:4;
+ uint32_t num_pak_passes:4;
+ uint32_t is_first_pass:1;
+ uint32_t is_last_pass:1;
+ uint32_t mb_brc_enabled:1;
+ uint32_t brc_roi_enable:1;
+ uint32_t brc_dirty_roi_enable:1;
+ uint32_t skip_frame_enbale:1;
+ uint32_t brc_reserved:9;
+
+ uint32_t target_bit_rate;
+ uint32_t max_bit_rate;
+ uint32_t min_bit_rate;
+ uint64_t init_vbv_buffer_fullness_in_bit;
+ uint64_t vbv_buffer_size_in_bit;
+ uint32_t frames_per_100s;
+ uint32_t gop_size;
+ uint32_t gop_ref_distance;
+ uint32_t brc_target_size;
+ uint32_t brc_mode;
+ double brc_init_current_target_buf_full_in_bits;
+ double brc_init_reset_input_bits_per_frame;
+ uint32_t brc_init_reset_buf_size_in_bits;
+ uint32_t brc_init_previous_target_buf_full_in_bits;
+ int32_t window_size;
+ int32_t target_percentage;
+ uint16_t avbr_curracy;
+ uint16_t avbr_convergence;
+
+ //skip frame enbale
+ uint32_t num_skip_frames;
+ uint32_t size_skip_frames;
+
+ // ROI related
+ uint32_t dirty_num_roi;
+ uint32_t num_roi;
+ uint32_t max_delta_qp;
+ uint32_t min_delta_qp;
+ struct intel_roi roi[3];
+
+};
+
+/*
+ by now VME and PAK use the same context. it will bind the ctx according to the codec and platform, also vdenc and non-vdenc
+*/
+struct encoder_vme_mfc_context {
+ int32_t codec_id;
+ void * generic_enc_ctx;
+ void * private_enc_ctx; //pointer to the specific enc_ctx
+ void * generic_enc_state;
+ void * private_enc_state; //pointer to the specific enc_state
+};
+
+#endif /* _I965_COMMON_ENCODER_H */
\ No newline at end of file
Qu, Pengfei
2017-01-18 11:36:44 UTC
Permalink
-----Original Message-----
From: Zhao, Yakui
Sent: Tuesday, January 17, 2017 9:15 AM
To: Qu, Pengfei <***@intel.com>
Cc: ***@lists.freedesktop.org
Subject: Re: [Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC encoder
Post by Pengfei Qu
add context init function for AVC encoder
More comments are added.
Post by Pengfei Qu
---
src/i965_encoder_api.h | 47 ++++
src/i965_encoder_common.c | 124 +++++++++++
src/i965_encoder_common.h | 533 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 704 insertions(+)
create mode 100755 src/i965_encoder_api.h
create mode 100755 src/i965_encoder_common.c
create mode 100755 src/i965_encoder_common.h
diff --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h new file
mode 100755 index 0000000..ebb0edc
--- /dev/null
+++ b/src/i965_encoder_api.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction,
+including
+ * without limitation the rights to use, copy, modify, merge,
+publish,
+ * distribute, sub license, and/or sell copies of the Software, and
+to
+ * permit persons to whom the Software is furnished to do so, subject
+to
+ *
+ * The above copyright notice and this permission notice (including
+the
+ * next paragraph) shall be included in all copies or substantial
+portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
+FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+
+#ifndef _I965_ENCODER_API_H_
+#define _I965_ENCODER_API_H_
+
+#include<va/va.h>
+
+struct intel_encoder_context;
+struct hw_context;
+
+/* H264/AVC */
+extern Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct
+intel_encoder_context *encoder_context);
+
+extern Bool
+gen9_avc_pak_context_init(VADriverContextP ctx, struct
+intel_encoder_context *encoder_context);
+
+extern VAStatus
+gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct
+hw_context *hw_context);
+
+#endif // _I965_ENCODER_API_H_
diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c new
file mode 100755 index 0000000..930aba9
--- /dev/null
+++ b/src/i965_encoder_common.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction,
+including
+ * without limitation the rights to use, copy, modify, merge,
+publish,
+ * distribute, sub license, and/or sell copies of the Software, and
+to
+ * permit persons to whom the Software is furnished to do so, subject
+to
+ *
+ * The above copyright notice and this permission notice (including
+the
+ * next paragraph) shall be included in all copies or substantial
+portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
+FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ *
+ */
+#include<stdio.h>
+#include<string.h>
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+#include "i965_encoder_common.h"
+#include "i965_gpe_utils.h"
+
+
+const unsigned int table_enc_search_path[2][8][16] = {
+ // I-Frame& P-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101, 0x11010101,
+ 0x01010101, 0x11010101, 0x01010101, 0x00010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding P frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ },
+ // B-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010, 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F, 0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding B frames
Also MPEG2?
[Pengfei] we did not use this. It will be removed.
Post by Pengfei Qu
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1, 0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+ }
+ }
+};
\ No newline at end of file
diff --git a/src/i965_encoder_common.h b/src/i965_encoder_common.h new
file mode 100755 index 0000000..bffbd8f
--- /dev/null
+++ b/src/i965_encoder_common.h
@@ -0,0 +1,533 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction,
+including
+ * without limitation the rights to use, copy, modify, merge,
+publish,
+ * distribute, sub license, and/or sell copies of the Software, and
+to
+ * permit persons to whom the Software is furnished to do so, subject
+to
+ *
+ * The above copyright notice and this permission notice (including
+the
+ * next paragraph) shall be included in all copies or substantial
+portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
+FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ *
+ */
+
+#ifndef _I965_COMMON_ENCODER_H
+#define _I965_COMMON_ENCODER_H
+
+#include<drm.h>
+#include<i915_drm.h>
+#include<intel_bufmgr.h>
+
+#include<va/va.h>
+#include "i965_encoder.h"
+#include "i965_gpe_utils.h"
+//#include "gen9_avc_encoder.h"
+
+struct encode_state;
+struct intel_encoder_context;
+
+/*
+ this file define the common structure for encoder, such as
+H264/H265/VP8/VP9 */
+
+#define INTEL_BRC_NONE 0
+#define INTEL_BRC_CBR 1
+#define INTEL_BRC_VBR 2
+#define INTEL_BRC_CQP 3
+#define INTEL_BRC_AVBR 4
+
+#define INTEL_BRC_INIT_FLAG_CBR 0x0010,
+#define INTEL_BRC_INIT_FLAG_VBR 0x0020,
+#define INTEL_BRC_INIT_FLAG_AVBR 0x0040,
+#define INTEL_BRC_INIT_FLAG_CQL 0x0080,
+#define INTEL_BRC_INIT_FLAG_FIELD_PIC 0x0100,
+#define INTEL_BRC_INIT_FLAG_ICQ 0x0200,
+#define INTEL_BRC_INIT_FLAG_VCM 0x0400,
+#define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
+#define INTEL_BRC_INIT_FLAG_QVBR 0x4000,
+#define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC 0x8000
+
+
+#define INTEL_BRC_UPDATE_FLAG_FIELD 0x01,
+#define INTEL_BRC_UPDATE_FLAG_MBAFF (0x01<< 1),
+#define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD (0x01<< 2),
+#define INTEL_BRC_UPDATE_FLAG_ACTUALQP (0x01<< 6),
+#define INTEL_BRC_UPDATE_FLAG_REFERENCE (0x01<< 7)
+
+#define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT 48
+
+extern const unsigned int table_enc_search_path[2][8][16];
+
+// BRC Flag in BRC Init Kernel
+typedef enum _INTEL_ENCODE_BRCINIT_FLAG {
+ INTEL_ENCODE_BRCINIT_ISCBR = 0x0010,
+ INTEL_ENCODE_BRCINIT_ISVBR = 0x0020,
+ INTEL_ENCODE_BRCINIT_ISAVBR = 0x0040,
+ INTEL_ENCODE_BRCINIT_ISCQL = 0x0080,
+ INTEL_ENCODE_BRCINIT_FIELD_PIC = 0x0100,
+ INTEL_ENCODE_BRCINIT_ISICQ = 0x0200,
+ INTEL_ENCODE_BRCINIT_ISVCM = 0x0400,
+ INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE = 0x2000,
+ INTEL_ENCODE_BRCINIT_ISQVBR = 0x4000,
+ INTEL_ENCODE_BRCINIT_DISABLE_MBBRC = 0x8000
+} INTEL_ENCODE_BRCINIT_FLAG;
+
+// BRC Flag in BRC Update Kernel
+typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG {
+ INTEL_ENCODE_BRCUPDATE_IS_FIELD = 0x01,
+ INTEL_ENCODE_BRCUPDATE_IS_MBAFF = (0x01<< 1),
+ INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD = (0x01<< 2),
+ INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP = (0x01<< 6),
+ INTEL_ENCODE_BRCUPDATE_IS_REFERENCE = (0x01<< 7)
+} INTEL_ENCODE_BRCUPDATE_FLAG;
+
+/*
+kernel operation related defines
+*/
+typedef enum _INTEL_GENERIC_ENC_OPERATION {
+ INTEL_GENERIC_ENC_SCALING4X = 0,
+ INTEL_GENERIC_ENC_SCALING2X,
+ INTEL_GENERIC_ENC_ME,
+ INTEL_GENERIC_ENC_BRC,
+ INTEL_GENERIC_ENC_MBENC,
+ INTEL_GENERIC_ENC_MBENC_WIDI,
+ INTEL_GENERIC_ENC_RESETVLINESTRIDE,
+ INTEL_GENERIC_ENC_MC,
+ INTEL_GENERIC_ENC_MBPAK,
+ INTEL_GENERIC_ENC_DEBLOCK,
+ INTEL_GENERIC_ENC_PREPROC,
+ INTEL_GENERIC_VDENC_ME,
+ INTEL_GENERIC_ENC_WP,
+ INTEL_GENERIC_ENC_SFD, // Static frame detection
+ INTEL_GENERIC_ENC_DYS
+} INTEL_GENERIC_ENC_OPERATION;
+
+typedef enum _INTEL_MEDIA_STATE_TYPE
+{
+ INTEL_MEDIA_STATE_OLP = 0,
+ INTEL_MEDIA_STATE_ENC_NORMAL = 1,
+ INTEL_MEDIA_STATE_ENC_PERFORMANCE = 2,
+ INTEL_MEDIA_STATE_ENC_QUALITY = 3,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_DIST = 4,
+ INTEL_MEDIA_STATE_32X_SCALING = 5,
+ INTEL_MEDIA_STATE_16X_SCALING = 6,
+ INTEL_MEDIA_STATE_4X_SCALING = 7,
+ INTEL_MEDIA_STATE_32X_ME = 8,
+ INTEL_MEDIA_STATE_16X_ME = 9,
+ INTEL_MEDIA_STATE_4X_ME = 10,
+ INTEL_MEDIA_STATE_BRC_INIT_RESET = 11,
+ INTEL_MEDIA_STATE_BRC_UPDATE = 12,
+ INTEL_MEDIA_STATE_BRC_BLOCK_COPY = 13,
Hybrid is not used.
[Pengfei] it will be removed
Post by Pengfei Qu
+ INTEL_MEDIA_STATE_HYBRID_PAK_P1 = 14,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P2 = 15,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_CHROMA = 16,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_LUMA = 17,
+ INTEL_MEDIA_STATE_MPU_FHB = 18,
+ INTEL_MEDIA_STATE_TPU_FHB = 19,
+ INTEL_MEDIA_STATE_PA_COPY = 20,
+ INTEL_MEDIA_STATE_PL2_COPY = 21,
+ INTEL_MEDIA_STATE_ENC_WIDI = 22,
+ INTEL_MEDIA_STATE_2X_SCALING = 23,
+ INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION = 24,
+ INTEL_MEDIA_STATE_16x16_PU_SAD = 25,
+ INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION = 26,
+ INTEL_MEDIA_STATE_8x8_PU = 27,
+ INTEL_MEDIA_STATE_8x8_PU_FMODE = 28,
+ INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK = 29,
+ INTEL_MEDIA_STATE_HEVC_B_MBENC = 30,
+ INTEL_MEDIA_STATE_RESET_VLINE_STRIDE = 31,
+ INTEL_MEDIA_STATE_HEVC_B_PAK = 32,
+ INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE = 33,
+ INTEL_MEDIA_STATE_ME_VDENC_STREAMIN = 34,
The following is defined for VP9. But it is never used.
[Pengfei] we keep this and will replace the definition in VP9.
Post by Pengfei Qu
+ INTEL_MEDIA_STATE_VP9_ENC_I_32x32 = 35,
+ INTEL_MEDIA_STATE_VP9_ENC_I_16x16 = 36,
+ INTEL_MEDIA_STATE_VP9_ENC_P = 37,
+ INTEL_MEDIA_STATE_VP9_ENC_TX = 38,
+ INTEL_MEDIA_STATE_VP9_DYS = 39,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_RECON = 40,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_RECON = 41,
+ INTEL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK = 42,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK = 43,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK = 44,
+ INTEL_MEDIA_STATE_VP9_PAK_MC_PRED = 45,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON = 46,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON_32x32 = 47,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON = 48,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON = 49,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON = 50,
+ INTEL_MEDIA_STATE_PREPROC = 51,
+ INTEL_MEDIA_STATE_ENC_WP = 52,
+ INTEL_MEDIA_STATE_HEVC_I_MBENC = 53,
+ INTEL_MEDIA_STATE_CSC_DS_COPY = 54,
+ INTEL_MEDIA_STATE_2X_4X_SCALING = 55,
+ INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC = 56,
+ INTEL_MEDIA_STATE_MB_BRC_UPDATE = 57,
+ INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION = 58,
+ INTEL_MEDIA_STATE_HEVC_ROI = 59,
+ INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT = 60,
+ INTEL_NUM_MEDIA_STATES = 61
+} INTEL_MEDIA_STATE_TYPE;
+
+struct encoder_kernel_parameter
+{
+ unsigned int curbe_size;
+ unsigned int inline_data_size;
+ unsigned int sampler_size;
+};
+
+struct encoder_scoreboard_parameter
+{
+ unsigned int mask;
+ unsigned int type;
+ unsigned int enable;
+ unsigned int walkpat_flag;
+};
+
+
+/*
+ME related defines
+*/
+#define INTEL_ENC_HME_4x 0
+#define INTEL_ENC_HME_16x 1
+#define INTEL_ENC_HME_32x 2
+
+/*
+ the definition for rate control
+*/
+#define GENERIC_BRC_SEQ 0x01
+#define GENERIC_BRC_HRD 0x02
+#define GENERIC_BRC_RC 0x04
+#define GENERIC_BRC_FR 0x08
+#define GENERIC_BRC_FAILURE (1<< 31)
+
+enum INTEL_ENC_KERNAL_MODE
+{
+ INTEL_ENC_KERNEL_QUALITY = 0,
+ INTEL_ENC_KERNEL_NORMAL,
+ INTEL_ENC_KERNEL_PERFORMANCE
+};
+
+enum INTEL_ENC_PRESET_MODE
+{
+ INTEL_PRESET_UNKNOWN = 0,
+ INTEL_PRESET_BEST_QUALITY = 1,
+ INTEL_PRESET_HI_QUALITY = 2,
+ INTEL_PRESET_OPT_QUALITY = 3,
+ INTEL_PRESET_OK_QUALITY = 5,
+ INTEL_PRESET_NO_SPEED = 1,
+ INTEL_PRESET_OPT_SPEED = 3,
+ INTEL_PRESET_RT_SPEED = 4,
+ INTEL_PRESET_HI_SPEED = 6,
+ INTEL_PRESET_BEST_SPEED = 7,
+ INTEL_PRESET_LOW_LATENCY = 0x10,
+ INTEL_PRESET_MULTIPASS = 0x20
+};
+/*
+ the definition for encoder status
+*/
+struct encoder_status
+{
+ uint32_t bs_byte_count;
+ uint32_t image_status_ctrl;
+ uint32_t media_index;
+};
+
+struct encoder_status_buffer_internal {
+ uint32_t bs_byte_count_offset;
+ uint32_t reserved[15];
+
+ uint32_t image_status_ctrl_offset;
+
+ uint32_t bs_frame_reg_offset;
+ uint32_t image_status_ctrl_reg_offset;
+ dri_bo *bo;
+ uint32_t status_buffer_size;
+ uint32_t base_offset;
+
+ uint32_t media_index_offset;
+};
+
+struct {
+ struct i965_gpe_resource res;
+ uint32_t base_offset;
+ uint32_t size;
+ uint32_t bytes_per_frame_offset;
+} status_bffuer;
+
+/*
+ the definition for encoder VME/PAK context */
+
+
+struct generic_encoder_context
+{
+ //scoreboard
+ uint32_t use_hw_scoreboard;
+ uint32_t use_hw_non_stalling_scoreboard;
+ //input surface
+ struct i965_gpe_resource res_uncompressed_input_surface;
+ //reconstructed surface
+ struct i965_gpe_resource res_reconstructed_surface;
+ //output bitstream
+ struct {
+ struct i965_gpe_resource res;
+ uint32_t start_offset;
+ uint32_t end_offset;
+ } compressed_bitstream;
+
+ //curbe set function pointer
+ void (*pfn_set_curbe_scaling2x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_scaling4x)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_me)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_mbenc)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_init_reset)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_frame_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_brc_mb_update)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_sfd)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_set_curbe_wp)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ //surface set function pointer
+ void (*pfn_send_scaling_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_me_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_mbenc_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_init_reset_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_frame_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_brc_mb_update_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_sfd_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+ void (*pfn_send_wp_surface)(
+ VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param);
+
+
+
+};
+/*
+ the definition for encoder codec state */
+
+struct generic_enc_codec_state {
+
+ //generic related
+ int32_t kernel_mode;
+ int32_t preset;
+ int32_t seq_frame_number;
+ int32_t total_frame_number;
+ int32_t herder_bytes_inserted;
+ uint8_t frame_type;
+ bool first_frame;
+
+ // original width/height
+ uint32_t frame_width_in_pixel;
+ uint32_t frame_height_in_pixel;
+ uint32_t frame_width_in_mbs;
+ uint32_t frame_height_in_mbs;
+
+ //scaling related
+ uint32_t frame_width_2x;
+ uint32_t frame_height_2x;
+ uint32_t downscaled_width_2x_in_mb;
+ uint32_t downscaled_height_2x_in_mb;
+ uint32_t frame_width_4x;
+ uint32_t frame_height_4x;
+ uint32_t frame_width_16x;
+ uint32_t frame_height_16x;
+ uint32_t frame_width_32x;
+ uint32_t frame_height_32x;
+ uint32_t downscaled_width_4x_in_mb;
+ uint32_t downscaled_height_4x_in_mb;
+ uint32_t downscaled_width_16x_in_mb;
+ uint32_t downscaled_height_16x_in_mb;
+ uint32_t downscaled_width_32x_in_mb;
+ uint32_t downscaled_height_32x_in_mb;
+
+ // ME related
+ uint32_t hme_supported:1;
+ uint32_t b16xme_supported:1;
+ uint32_t b32xme_supported:1;
+ uint32_t hme_enabled:1;
+ uint32_t b16xme_enabled:1;
+ uint32_t b32xme_enabled:1;
+ uint32_t brc_distortion_buffer_supported:1;
+ uint32_t brc_constant_buffer_supported:1;
+ uint32_t hme_reserved:24;
+
+ //BRC related
+ uint32_t frame_rate;
+
+ uint32_t brc_allocated:1;
+ uint32_t brc_inited:1;
+ uint32_t brc_need_reset:1;
+ uint32_t is_low_delay:1;
+ uint32_t brc_enabled:1;
+ uint32_t internal_rate_mode:4;
+ uint32_t curr_pak_pass:4;
+ uint32_t num_pak_passes:4;
+ uint32_t is_first_pass:1;
+ uint32_t is_last_pass:1;
+ uint32_t mb_brc_enabled:1;
+ uint32_t brc_roi_enable:1;
+ uint32_t brc_dirty_roi_enable:1;
+ uint32_t skip_frame_enbale:1;
+ uint32_t brc_reserved:9;
+
+ uint32_t target_bit_rate;
+ uint32_t max_bit_rate;
+ uint32_t min_bit_rate;
+ uint64_t init_vbv_buffer_fullness_in_bit;
+ uint64_t vbv_buffer_size_in_bit;
+ uint32_t frames_per_100s;
+ uint32_t gop_size;
+ uint32_t gop_ref_distance;
+ uint32_t brc_target_size;
+ uint32_t brc_mode;
+ double brc_init_current_target_buf_full_in_bits;
+ double brc_init_reset_input_bits_per_frame;
+ uint32_t brc_init_reset_buf_size_in_bits;
+ uint32_t brc_init_previous_target_buf_full_in_bits;
+ int32_t window_size;
+ int32_t target_percentage;
+ uint16_t avbr_curracy;
+ uint16_t avbr_convergence;
+
+ //skip frame enbale
+ uint32_t num_skip_frames;
+ uint32_t size_skip_frames;
+
+ // ROI related
+ uint32_t dirty_num_roi;
+ uint32_t num_roi;
+ uint32_t max_delta_qp;
+ uint32_t min_delta_qp;
+ struct intel_roi roi[3];
+
+};
+
+/*
+ by now VME and PAK use the same context. it will bind the ctx
+according to the codec and platform, also vdenc and non-vdenc */
+struct encoder_vme_mfc_context {
+ int32_t codec_id;
+ void * generic_enc_ctx;
+ void * private_enc_ctx; //pointer to the specific enc_ctx
+ void * generic_enc_state;
+ void * private_enc_state; //pointer to the specific enc_state };
+
+#endif /* _I965_COMMON_ENCODER_H */
\ No newline at end of file
Mark Thompson
2017-01-21 23:27:46 UTC
Permalink
Post by Pengfei Qu
add context init function for AVC encoder
---
src/i965_encoder_api.h | 47 ++++
src/i965_encoder_common.c | 124 +++++++++++
src/i965_encoder_common.h | 533 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 704 insertions(+)
create mode 100755 src/i965_encoder_api.h
create mode 100755 src/i965_encoder_common.c
create mode 100755 src/i965_encoder_common.h
Many of your new files have the execute bit set, in this and other patches.
Post by Pengfei Qu
...
diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c
new file mode 100755
index 0000000..930aba9
--- /dev/null
+++ b/src/i965_encoder_common.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
Similarly, the licence header on some new files is truncated.

- Mark
Qu, Pengfei
2017-01-22 07:26:52 UTC
Permalink
Yes. I will fix it.

-----Original Message-----
From: Mark Thompson [mailto:***@jkqxz.net]
Sent: Sunday, January 22, 2017 7:28 AM
To: ***@lists.freedesktop.org; Qu, Pengfei <***@intel.com>
Subject: Re: [Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC encoder
Post by Pengfei Qu
add context init function for AVC encoder
---
src/i965_encoder_api.h | 47 ++++
src/i965_encoder_common.c | 124 +++++++++++
src/i965_encoder_common.h | 533
++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 704 insertions(+)
create mode 100755 src/i965_encoder_api.h create mode 100755
src/i965_encoder_common.c create mode 100755
src/i965_encoder_common.h
Many of your new files have the execute bit set, in this and other patches.
Post by Pengfei Qu
...
diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c new
file mode 100755 index 0000000..930aba9
--- /dev/null
+++ b/src/i965_encoder_common.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction,
+including
+ * without limitation the rights to use, copy, modify, merge,
+publish,
+ * distribute, sub license, and/or sell copies of the Software, and
+to
+ * permit persons to whom the Software is furnished to do so, subject
+to
+ *
+ * The above copyright notice and this permission notice (including
+the
+ * next paragraph) shall be included in all copies or substantial
+portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
+FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
Similarly, the licence header on some new files is truncated.

- Mark
Pengfei Qu
2017-01-13 09:24:06 UTC
Permalink
Signed-off-by: Pengfei Qu <***@intel.com>
Reviewed-by: Sean V Kelley<***@posteo.de>
---
src/gen9_avc_const_def.c | 1090 ++++++++++++++++++++++++++++++++++++++++++++++
src/gen9_avc_const_def.h | 115 +++++
2 files changed, 1205 insertions(+)
create mode 100755 src/gen9_avc_const_def.c
create mode 100755 src/gen9_avc_const_def.h

diff --git a/src/gen9_avc_const_def.c b/src/gen9_avc_const_def.c
new file mode 100755
index 0000000..e0edfd4
--- /dev/null
+++ b/src/gen9_avc_const_def.c
@@ -0,0 +1,1090 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu <***@intel.com>
+ *
+ */
+
+
+#include "gen9_avc_const_def.h"
+
+/*
+init const table for scaling/sfd/curbe
+*/
+
+const char gen9_avc_sfd_cost_table_p_frame[AVC_QP_MAX] =
+{
+ 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 44, 60, 60, 60, 60,
+ 73, 73, 73, 76, 76, 76, 88, 89, 89, 91, 92, 93, 104, 104, 106, 107, 108, 109, 120,
+ 120, 122, 123, 124, 125, 136, 136, 138, 139, 140, 141, 143, 143
+};
+
+const char gen9_avc_sfd_cost_table_b_frame[AVC_QP_MAX] =
+{
+ 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 57, 73, 73, 73, 73,
+ 77, 77, 77, 89, 89, 89, 91, 93, 93, 95, 105, 106, 107, 108, 110, 111, 121, 122,
+ 123, 124, 125, 127, 137, 138, 139, 140, 142, 143, 143, 143, 143, 143
+};
+
+/*
+MBBRC const: mv mode cost ,skip value,scaling factor
+*/
+const unsigned int gen9_avc_old_intra_mode_cost[AVC_QP_MAX] =
+{
+ 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a,
+ 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a, 0x1e03000a,
+ 0x2e06001a, 0x2e06001a, 0x2e06001a, 0x2e06001a, 0x3b09001f, 0x3b09001f, 0x3b09001f, 0x3e0c002a,
+ 0x3e0c002a, 0x3e0c002a, 0x490f002d, 0x4b19002f, 0x4b19002f, 0x4c1b0039, 0x4e1c003a, 0x581e003b,
+ 0x591f003d, 0x5a28003e, 0x5b2a0048, 0x5c2b0049, 0x5e2c004a, 0x682e004b, 0x692f004d, 0x6a39004e,
+ 0x6b390058, 0x6d3b0059, 0x6e3c005a, 0x783e005b, 0x793f005d, 0x7a48005e, 0x7b4a0068, 0x7c4b0069,
+ 0x7e4c006a, 0x884e006b, 0x894f006d, 0x8a59006e
+};
+
+const unsigned int gen9_avc_mv_cost_p_skip_adjustment[AVC_QP_MAX] =
+{
+ 0x09060500, 0x09060500, 0x09060500, 0x09060500, 0x09060500, 0x09060500, 0x09060500, 0x09060500,
+ 0x09060500, 0x09060500, 0x09060500, 0x09060500, 0x09060500, 0x09060500, 0x09060500, 0x09060500,
+ 0x190c0a00, 0x190c0a00, 0x190c0a00, 0x190c0a00, 0x1e190f00, 0x1e190f00, 0x1e190f00, 0x291c1a00,
+ 0x291c1a00, 0x291c1a00, 0x2b1f1d00, 0x2e291f00, 0x2e291f00, 0x382b2900, 0x392c2a00, 0x3a2e2b00,
+ 0x3b2f2d00, 0x3c382e00, 0x3f3a3800, 0x483b3900, 0x493c3a00, 0x4a3e3b00, 0x4b3f3d00, 0x4d493e00,
+ 0x4e494800, 0x584b4900, 0x594c4a00, 0x5a4e4b00, 0x5b4f4d00, 0x5d584e00, 0x5e5a5800, 0x685b5900,
+ 0x695c5a00, 0x6a5e5b00, 0x6b5f5d00, 0x6d695e00
+};
+
+const unsigned short gen9_avc_skip_value_p[2][2][64] =
+{
+ {
+ // Block Based Skip = 0 and Transform Flag = 0
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0006,
+ 0x0006, 0x000c, 0x000c, 0x0015, 0x0015, 0x0021, 0x0021, 0x0033,
+ 0x0033, 0x004b, 0x004b, 0x0069, 0x0069, 0x0096, 0x0096, 0x00cc,
+ 0x00cc, 0x0111, 0x0111, 0x0165, 0x0165, 0x01cb, 0x01cb, 0x0246,
+ 0x0246, 0x02d3, 0x02d3, 0x0378, 0x0378, 0x0438, 0x0438, 0x0510,
+ 0x0510, 0x0603, 0x0603, 0x0714, 0x0714, 0x0846, 0x0846, 0x0999,
+ 0x0999, 0x0b10, 0x0b10, 0x0c3c, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ },
+
+ // Block Based Skip = 0 and Transform Flag = 1
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0006,
+ 0x0006, 0x000c, 0x000c, 0x0015, 0x0015, 0x0021, 0x0021, 0x0033,
+ 0x0033, 0x004b, 0x004b, 0x0069, 0x0069, 0x0096, 0x0096, 0x00cc,
+ 0x00cc, 0x0111, 0x0111, 0x0165, 0x0165, 0x01cb, 0x01cb, 0x0246,
+ 0x0246, 0x02d3, 0x02d3, 0x0378, 0x0378, 0x0438, 0x0438, 0x0510,
+ 0x0510, 0x0603, 0x0603, 0x0714, 0x0714, 0x0846, 0x0846, 0x0999,
+ 0x0999, 0x0b10, 0x0b10, 0x0c3c, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ }
+ },
+ {
+ // Block Based Skip = 1 and Transform Flag = 0
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001,
+ 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0005, 0x0005, 0x0008,
+ 0x0008, 0x000c, 0x000c, 0x0011, 0x0011, 0x0019, 0x0019, 0x0022,
+ 0x0022, 0x002d, 0x002d, 0x003b, 0x003b, 0x004c, 0x004c, 0x0061,
+ 0x0061, 0x0078, 0x0078, 0x0094, 0x0094, 0x00b4, 0x00b4, 0x00d8,
+ 0x00d8, 0x0100, 0x0100, 0x012e, 0x012e, 0x0161, 0x0161, 0x0199,
+ 0x0199, 0x01d8, 0x01d8, 0x020a, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ },
+
+ // Block Based Skip = 1 and Transform Flag = 1
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0002,
+ 0x0002, 0x0004, 0x0004, 0x0007, 0x0007, 0x000b, 0x000b, 0x0011,
+ 0x0011, 0x0019, 0x0019, 0x0023, 0x0023, 0x0032, 0x0032, 0x0044,
+ 0x0044, 0x005b, 0x005b, 0x0077, 0x0077, 0x0099, 0x0099, 0x00c2,
+ 0x00c2, 0x00f1, 0x00f1, 0x0128, 0x0128, 0x0168, 0x0168, 0x01b0,
+ 0x01b0, 0x0201, 0x0201, 0x025c, 0x025c, 0x02c2, 0x02c2, 0x0333,
+ 0x0333, 0x03b0, 0x03b0, 0x0414, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ }
+ }
+};
+
+const unsigned short gen9_avc_skip_value_b[2][2][64] =
+{
+ {
+ // Block Based Skip = 0 and Transform Flag = 0
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0024,
+ 0x0024, 0x0060, 0x0060, 0x0099, 0x0099, 0x00cf, 0x00cf, 0x0105,
+ 0x0105, 0x0141, 0x0141, 0x0183, 0x0183, 0x01ce, 0x01ce, 0x0228,
+ 0x0228, 0x0291, 0x0291, 0x030c, 0x030c, 0x039f, 0x039f, 0x0447,
+ 0x0447, 0x050d, 0x050d, 0x05f1, 0x05f1, 0x06f6, 0x06f6, 0x0822,
+ 0x0822, 0x0972, 0x0972, 0x0aef, 0x0aef, 0x0c96, 0x0c96, 0x0e70,
+ 0x0e70, 0x107a, 0x107a, 0x1284, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ },
+ // Block Based Skip = 0 and Transform Flag = 1
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0024,
+ 0x0024, 0x0060, 0x0060, 0x0099, 0x0099, 0x00cf, 0x00cf, 0x0105,
+ 0x0105, 0x0141, 0x0141, 0x0183, 0x0183, 0x01ce, 0x01ce, 0x0228,
+ 0x0228, 0x0291, 0x0291, 0x030c, 0x030c, 0x039f, 0x039f, 0x0447,
+ 0x0447, 0x050d, 0x050d, 0x05f1, 0x05f1, 0x06f6, 0x06f6, 0x0822,
+ 0x0822, 0x0972, 0x0972, 0x0aef, 0x0aef, 0x0c96, 0x0c96, 0x0e70,
+ 0x0e70, 0x107a, 0x107a, 0x1284, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ }
+ },
+ {
+ // Block Based Skip = 1 and Transform Flag = 0
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0006,
+ 0x0006, 0x0010, 0x0010, 0x0019, 0x0019, 0x0022, 0x0022, 0x002b,
+ 0x002b, 0x0035, 0x0035, 0x0040, 0x0040, 0x004d, 0x004d, 0x005c,
+ 0x005c, 0x006d, 0x006d, 0x0082, 0x0082, 0x009a, 0x009a, 0x00b6,
+ 0x00b6, 0x00d7, 0x00d7, 0x00fd, 0x00fd, 0x0129, 0x0129, 0x015b,
+ 0x015b, 0x0193, 0x0193, 0x01d2, 0x01d2, 0x0219, 0x0219, 0x0268,
+ 0x0268, 0x02bf, 0x02bf, 0x0316, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ },
+ // Block Based Skip = 1 and Transform Flag = 1
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x000c,
+ 0x000c, 0x0020, 0x0020, 0x0033, 0x0033, 0x0045, 0x0045, 0x0057,
+ 0x0057, 0x006b, 0x006b, 0x0081, 0x0081, 0x009a, 0x009a, 0x00b8,
+ 0x00b8, 0x00db, 0x00db, 0x0104, 0x0104, 0x0135, 0x0135, 0x016d,
+ 0x016d, 0x01af, 0x01af, 0x01fb, 0x01fb, 0x0252, 0x0252, 0x02b6,
+ 0x02b6, 0x0326, 0x0326, 0x03a5, 0x03a5, 0x0432, 0x0432, 0x04d0,
+ 0x04d0, 0x057e, 0x057e, 0x062c, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ }
+ }
+};
+
+// QP is from 0 - 51, pad it to 64 since BRC needs array size to be 64 bytes
+const unsigned char gen9_avc_adaptive_intra_scaling_factor[64] =
+{
+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0c, 0x0c,
+ 0x0c, 0x0c, 0x0d, 0x0d, 0x0d, 0x0d, 0x0e, 0x0e,
+ 0x0e, 0x0e, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+// QP is from 0 - 51, pad it to 64 since BRC needs array size to be 64 bytes
+const unsigned char gen9_avc_intra_scaling_factor[64] =
+{
+ 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c,
+ 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c,
+ 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+// AVC MBEnc CURBE init data
+const unsigned int gen9_avc_mbenc_curbe_normal_i_frame_init_data[GEN9_AVC_MBENC_CURBE_SIZE] =
+{
+ 0x00000082, 0x00000000, 0x00003910, 0x00a83000, 0x00000000, 0x28300000, 0x05000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x80800000, 0x00040c24, 0x00000000, 0xffff00ff, 0x40000000, 0x00000080, 0x00003900, 0x28301000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+
+const unsigned int gen9_avc_mbenc_curbe_normal_p_frame_init_data[GEN9_AVC_MBENC_CURBE_SIZE] =
+{
+ 0x000000a3, 0x00000008, 0x00003910, 0x00ae3000, 0x30000000, 0x28300000, 0x05000000, 0x01400060,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x80010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x60000000, 0x000000a1, 0x00003900, 0x28301000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000002,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+const unsigned int gen9_avc_mbenc_curbe_normal_b_frame_init_data[GEN9_AVC_MBENC_CURBE_SIZE] =
+{
+ 0x000000a3, 0x00200008, 0x00003910, 0x00aa7700, 0x50020000, 0x20200000, 0x05000000, 0xff400000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x01010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x60000000, 0x000000a1, 0x00003900, 0x28301000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000002,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+// AVC I_DIST CURBE init data
+const unsigned int gen9_avc_mbenc_curbe_i_frame_dist_init_data[GEN9_AVC_MBENC_CURBE_SIZE] =
+{
+ 0x00000082, 0x00200008, 0x001e3910, 0x00a83000, 0x90000000, 0x28300000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100,
+ 0x80800000, 0x00000000, 0x00000800, 0xffff00ff, 0x40000000, 0x00000080, 0x00003900, 0x28300000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+// AVC ME CURBE init data
+const unsigned int gen9_avc_me_curbe_init_data[39] =
+{
+ 0x00000000, 0x00200010, 0x00003939, 0x77a43000, 0x00000000, 0x28300000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+/*
+ME cost table: mv/ref/mode
+*/
+// AVC MBEnc ModeCost and MVCost tables, index [CodingType][QP] and
+const unsigned int gen75_avc_mode_mv_cost_table[3][52][8] =
+{
+ // I-Frame
+ {
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff000000, 0x00000000, 0x00000000},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff010101, 0x00000000, 0x00000000},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff020202, 0x00000000, 0x00000000},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff030303, 0x00000000, 0x00000000},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff040404, 0x00000000, 0x00000000},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff050505, 0x00000000, 0x00000000},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff060606, 0x00000000, 0x00000000},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff070707, 0x01010001, 0x01010101},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff080808, 0x01010001, 0x01010101},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff090909, 0x03030003, 0x03030303},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0a0a0a, 0x03030003, 0x03030303},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0b0b0b, 0x06060006, 0x06060606},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0c0c0c, 0x06060006, 0x06060606},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0d0d0d, 0x08080008, 0x08080808},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0e0e0e, 0x08080008, 0x08080808},
+ {0x1e03000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0f0f0f, 0x0b0b000b, 0x0b0b0b0b},
+ {0x2e06001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff101010, 0x0b0b000b, 0x0b0b0b0b},
+ {0x2e06001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff111111, 0x0d0d000d, 0x0d0d0d0d},
+ {0x2e06001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff121212, 0x0d0d000d, 0x0d0d0d0d},
+ {0x2e06001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff131313, 0x10100010, 0x10101010},
+ {0x3b09001f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff141414, 0x10100010, 0x10101010},
+ {0x3b09001f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff151515, 0x13130013, 0x13131313},
+ {0x3b09001f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff161616, 0x13130013, 0x13131313},
+ {0x3e0c002a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff171717, 0x16160016, 0x16161616},
+ {0x3e0c002a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff181818, 0x16160016, 0x16161616},
+ {0x3e0c002a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff191919, 0x1a1a001a, 0x1a1a1a1a},
+ {0x490f002d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1a1a1a, 0x1a1a001a, 0x1a1a1a1a},
+ {0x4b19002f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1b1b1b, 0x1e1e001e, 0x1e1e1e1e},
+ {0x4b19002f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1c1c1c, 0x1e1e001e, 0x1e1e1e1e},
+ {0x4c1b0039, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1d1d1d, 0x22220022, 0x22222222},
+ {0x4e1c003a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1e1e1e, 0x22220022, 0x22222222},
+ {0x581e003b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1f1f1f, 0x27270027, 0x27272727},
+ {0x591f003d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff202020, 0x27270027, 0x27272727},
+ {0x5a28003e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff212121, 0x2c2c002c, 0x2c2c2c2c},
+ {0x5b2a0048, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff222222, 0x2c2c002c, 0x2c2c2c2c},
+ {0x5c2b0049, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff232323, 0x32320032, 0x32323232},
+ {0x5e2c004a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff242424, 0x32320032, 0x32323232},
+ {0x682e004b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff252525, 0x38380038, 0x38383838},
+ {0x692f004d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff262626, 0x38380038, 0x38383838},
+ {0x6a39004e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff272727, 0x3e3e003e, 0x3e3e3e3e},
+ {0x6b390058, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff282828, 0x3e3e003e, 0x3e3e3e3e},
+ {0x6d3b0059, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff292929, 0x45450045, 0x45454545},
+ {0x6e3c005a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2a2a2a, 0x45450045, 0x45454545},
+ {0x783e005b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2b2b2b, 0x4d4d004d, 0x4d4d4d4d},
+ {0x793f005d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2c2c2c, 0x4d4d004d, 0x4d4d4d4d},
+ {0x7a48005e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2d2d2d, 0x55550055, 0x55555555},
+ {0x7b4a0068, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2e2e2e, 0x55550055, 0x55555555},
+ {0x7c4b0069, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2f2f2f, 0x5e5e005e, 0x5e5e5e5e},
+ {0x7e4c006a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff303030, 0x5e5e005e, 0x5e5e5e5e},
+ {0x884e006b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff313131, 0x68680068, 0x68686868},
+ {0x894f006d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff323232, 0x68680068, 0x68686868},
+ {0x8a59006e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff333333, 0x73730073, 0x73737373},
+ },
+ // P-Frame
+ {
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff010101, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff020202, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff030303, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff040404, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff050505, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff060606, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff070707, 0x01010001, 0x01010101},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff080808, 0x01010001, 0x01010101},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff090909, 0x03030003, 0x03030303},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0a0a0a, 0x03030003, 0x03030303},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0b0b0b, 0x06060006, 0x06060606},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0c0c0c, 0x06060006, 0x06060606},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0d0d0d, 0x08080008, 0x08080808},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0e0e0e, 0x08080008, 0x08080808},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0f0f0f, 0x0b0b000b, 0x0b0b0b0b},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff101010, 0x0b0b000b, 0x0b0b0b0b},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff111111, 0x0d0d000d, 0x0d0d0d0d},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff121212, 0x0d0d000d, 0x0d0d0d0d},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff131313, 0x10100010, 0x10101010},
+ {0x4d3b2f1b, 0x1a0d071d, 0x000c0018, 0x1e0f0c03, 0x2b2b291f, 0xff141414, 0x10100010, 0x10101010},
+ {0x4d3b2f1b, 0x1a0d071d, 0x000c0018, 0x1e0f0c03, 0x2b2b291f, 0xff151515, 0x13130013, 0x13131313},
+ {0x4d3b2f1b, 0x1a0d071d, 0x000c0018, 0x1e0f0c03, 0x2b2b291f, 0xff161616, 0x13130013, 0x13131313},
+ {0x593e3a1e, 0x1d190a29, 0x0018001b, 0x291a1804, 0x2f2e2c2a, 0xff171717, 0x16160016, 0x16161616},
+ {0x593e3a1e, 0x1d190a29, 0x0018001b, 0x291a1804, 0x2f2e2c2a, 0xff181818, 0x16160016, 0x16161616},
+ {0x593e3a1e, 0x1d190a29, 0x0018001b, 0x291a1804, 0x2f2e2c2a, 0xff191919, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5b493d29, 0x281c0d2b, 0x001a001e, 0x2b1d1a05, 0x39392f2d, 0xff1a1a1a, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5d4b3f2b, 0x2a1e0f2d, 0x001c0028, 0x2e1f1c06, 0x3b3b392f, 0xff1b1b1b, 0x1e1e001e, 0x1e1e1e1e},
+ {0x5d4b3f2b, 0x2a1e0f2d, 0x001c0028, 0x2e1f1c06, 0x3b3b392f, 0xff1c1c1c, 0x1e1e001e, 0x1e1e1e1e},
+ {0x5f4c492c, 0x2c28192f, 0x001e002a, 0x38291e07, 0x3d3c3b39, 0xff1d1d1d, 0x22220022, 0x22222222},
+ {0x694e4a2e, 0x2d291b39, 0x0028002b, 0x392a2808, 0x3f3e3c3a, 0xff1e1e1e, 0x22220022, 0x22222222},
+ {0x6a584b38, 0x2f2a1c3a, 0x0029002c, 0x3a2b2909, 0x48483e3b, 0xff1f1f1f, 0x27270027, 0x27272727},
+ {0x6b594d39, 0x382c1d3b, 0x002a002e, 0x3b2d2a0a, 0x49493f3d, 0xff202020, 0x27270027, 0x27272727},
+ {0x6c5a4e3a, 0x392d1f3c, 0x002b002f, 0x3c2e2b0b, 0x4a4a483e, 0xff212121, 0x2c2c002c, 0x2c2c2c2c},
+ {0x6e5b583b, 0x3b2f293e, 0x002d0039, 0x3f382d0d, 0x4c4b4a48, 0xff222222, 0x2c2c002c, 0x2c2c2c2c},
+ {0x6f5c593c, 0x3c38293f, 0x002e003a, 0x48392e0e, 0x4d4c4b49, 0xff232323, 0x32320032, 0x32323232},
+ {0x795e5a3e, 0x3d392b49, 0x0038003b, 0x493a3818, 0x4f4e4c4a, 0xff242424, 0x32320032, 0x32323232},
+ {0x7a685b48, 0x3f3a2c4a, 0x0039003c, 0x4a3b3919, 0x58584e4b, 0xff252525, 0x38380038, 0x38383838},
+ {0x7b695d49, 0x483c2d4b, 0x003a003e, 0x4b3d3a1a, 0x59594f4d, 0xff262626, 0x38380038, 0x38383838},
+ {0x7d6a5e4a, 0x4a3d2f4c, 0x003c0048, 0x4d3e3c1c, 0x5b5a594e, 0xff272727, 0x3e3e003e, 0x3e3e3e3e},
+ {0x7e6b684b, 0x4a3e384d, 0x003d0049, 0x4e483d1d, 0x5c5b5958, 0xff282828, 0x3e3e003e, 0x3e3e3e3e},
+ {0x886d694d, 0x4c483a4f, 0x003f004a, 0x58493f1f, 0x5e5d5b59, 0xff292929, 0x45450045, 0x45454545},
+ {0x896e6a4e, 0x4d493b59, 0x0048004b, 0x594a4828, 0x5f5e5c5a, 0xff2a2a2a, 0x45450045, 0x45454545},
+ {0x8a786b58, 0x4f4a3c5a, 0x0049004c, 0x5a4b4929, 0x68685e5b, 0xff2b2b2b, 0x4d4d004d, 0x4d4d4d4d},
+ {0x8b796d59, 0x584c3d5b, 0x004a004e, 0x5b4d4a2a, 0x69695f5d, 0xff2c2c2c, 0x4d4d004d, 0x4d4d4d4d},
+ {0x8c7a6e5a, 0x594d3f5c, 0x004b004f, 0x5d4e4b2b, 0x6b6a685e, 0xff2d2d2d, 0x55550055, 0x55555555},
+ {0x8e7b785b, 0x5b4f485e, 0x004d0059, 0x5e584d2d, 0x6c6b6a68, 0xff2e2e2e, 0x55550055, 0x55555555},
+ {0x8f7c795c, 0x5c58495f, 0x004e005a, 0x68594e2e, 0x6d6c6b69, 0xff2f2f2f, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8f7e7a5e, 0x5d594b69, 0x0058005b, 0x695a5838, 0x6f6e6c6a, 0xff303030, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8f887b68, 0x5f5a4c6a, 0x0059005c, 0x6a5b5939, 0x6f6f6e6b, 0xff313131, 0x68680068, 0x68686868},
+ {0x8f897d69, 0x685c4d6b, 0x005a005e, 0x6b5d5a3a, 0x6f6f6f6d, 0xff323232, 0x68680068, 0x68686868},
+ {0x8f8a7e6a, 0x695d4f6c, 0x005b0068, 0x6d5e5b3b, 0x6f6f6f6e, 0xff333333, 0x73730073, 0x73737373},
+ },
+ // B-Frame
+ {
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff010101, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff020202, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff030303, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff040404, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff050505, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff060606, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff070707, 0x01010001, 0x01010101},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff080808, 0x01010001, 0x01010101},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff090909, 0x03030003, 0x03030303},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0a0a0a, 0x03030003, 0x03030303},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0b0b0b, 0x06060006, 0x06060606},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0c0c0c, 0x06060006, 0x06060606},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0d0d0d, 0x08080008, 0x08080808},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0e0e0e, 0x08080008, 0x08080808},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0f0f0f, 0x0b0b000b, 0x0b0b0b0b},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff101010, 0x0b0b000b, 0x0b0b0b0b},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff111111, 0x0d0d000d, 0x0d0d0d0d},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff121212, 0x0d0d000d, 0x0d0d0d0d},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff131313, 0x10100010, 0x10101010},
+ {0x4f3f3d1b, 0x281d1a29, 0x000c0619, 0x19060600, 0x2c2b291f, 0xff141414, 0x10100010, 0x10101010},
+ {0x4f3f3d1b, 0x281d1a29, 0x000c0619, 0x19060600, 0x2c2b291f, 0xff151515, 0x13130013, 0x13131313},
+ {0x4f3f3d1b, 0x281d1a29, 0x000c0619, 0x19060600, 0x2c2b291f, 0xff161616, 0x13130013, 0x13131313},
+ {0x5a4a491e, 0x2b291d2c, 0x0018081c, 0x1c080800, 0x382e2c2a, 0xff171717, 0x16160016, 0x16161616},
+ {0x5a4a491e, 0x2b291d2c, 0x0018081c, 0x1c080800, 0x382e2c2a, 0xff181818, 0x16160016, 0x16161616},
+ {0x5a4a491e, 0x2b291d2c, 0x0018081c, 0x1c080800, 0x382e2c2a, 0xff191919, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5d4d4b29, 0x2d2b282f, 0x001a0a1f, 0x1f0a0a00, 0x3a392f2d, 0xff1a1a1a, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5f4f4d2b, 0x382d2a39, 0x001c0c29, 0x290c0c00, 0x3c3b392f, 0xff1b1b1b, 0x1e1e001e, 0x1e1e1e1e},
+ {0x5f4f4d2b, 0x382d2a39, 0x001c0c29, 0x290c0c00, 0x3c3b392f, 0xff1c1c1c, 0x1e1e001e, 0x1e1e1e1e},
+ {0x69594f2c, 0x392f2b3b, 0x001e0e2b, 0x2b0e0e00, 0x3e3c3b39, 0xff1d1d1d, 0x22220022, 0x22222222},
+ {0x6a5a592e, 0x3b392d3c, 0x0028182c, 0x2c181800, 0x483e3c3a, 0xff1e1e1e, 0x22220022, 0x22222222},
+ {0x6b5b5a38, 0x3c3a2f3e, 0x0029192e, 0x2e191900, 0x49483e3b, 0xff1f1f1f, 0x27270027, 0x27272727},
+ {0x6d5d5b39, 0x3d3b383f, 0x002a1a2f, 0x2f1a1a00, 0x4a493f3d, 0xff202020, 0x27270027, 0x27272727},
+ {0x6e5e5c3a, 0x3e3c3948, 0x002b1b38, 0x381b1b00, 0x4b4a483e, 0xff212121, 0x2c2c002c, 0x2c2c2c2c},
+ {0x78685e3b, 0x493e3b4a, 0x002d1d3a, 0x3a1d1d00, 0x4d4b4a48, 0xff222222, 0x2c2c002c, 0x2c2c2c2c},
+ {0x79695f3c, 0x493f3b4b, 0x002e1e3b, 0x3b1e1e00, 0x4e4c4b49, 0xff232323, 0x32320032, 0x32323232},
+ {0x7a6a693e, 0x4b493d4c, 0x0038283c, 0x3c282800, 0x584e4c4a, 0xff242424, 0x32320032, 0x32323232},
+ {0x7b6b6a48, 0x4c4a3f4e, 0x0039293e, 0x3e292900, 0x59584e4b, 0xff252525, 0x38380038, 0x38383838},
+ {0x7d6d6b49, 0x4d4b484f, 0x003a2a3f, 0x3f2a2a00, 0x5a594f4d, 0xff262626, 0x38380038, 0x38383838},
+ {0x7e6e6c4a, 0x4f4c4959, 0x003c2c49, 0x492c2c00, 0x5c5a594e, 0xff272727, 0x3e3e003e, 0x3e3e3e3e},
+ {0x88786d4b, 0x584d4a59, 0x003d2d49, 0x492d2d00, 0x5d5b5958, 0xff282828, 0x3e3e003e, 0x3e3e3e3e},
+ {0x89796f4d, 0x5a4f4c5b, 0x003f2f4b, 0x4b2f2f00, 0x5f5d5b59, 0xff292929, 0x45450045, 0x45454545},
+ {0x8a7a794e, 0x5b594d5c, 0x0048384c, 0x4c383800, 0x685e5c5a, 0xff2a2a2a, 0x45450045, 0x45454545},
+ {0x8b7b7a58, 0x5c5a4f5e, 0x0049394e, 0x4e393900, 0x69685e5b, 0xff2b2b2b, 0x4d4d004d, 0x4d4d4d4d},
+ {0x8d7d7b59, 0x5d5b585f, 0x004a3a4f, 0x4f3a3a00, 0x6a695f5d, 0xff2c2c2c, 0x4d4d004d, 0x4d4d4d4d},
+ {0x8e7e7c5a, 0x5f5c5968, 0x004b3b58, 0x583b3b00, 0x6b6a685e, 0xff2d2d2d, 0x55550055, 0x55555555},
+ {0x8f887e5b, 0x685e5a6a, 0x004d3d5a, 0x5a3d3d00, 0x6d6b6a68, 0xff2e2e2e, 0x55550055, 0x55555555},
+ {0x8f897f5c, 0x695f5c6b, 0x004e3e5b, 0x5b3e3e00, 0x6e6c6b69, 0xff2f2f2f, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8f8a895e, 0x6b695d6c, 0x0058485c, 0x5c484800, 0x6f6e6c6a, 0xff303030, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8f8b8a68, 0x6c6a5f6e, 0x0059495e, 0x5e494900, 0x6f6f6e6b, 0xff313131, 0x68680068, 0x68686868},
+ {0x8f8d8b69, 0x6d6b686f, 0x005a4a5f, 0x5f4a4a00, 0x6f6f6f6d, 0xff323232, 0x68680068, 0x68686868},
+ {0x8f8e8c6a, 0x6f6c6979, 0x005b4b69, 0x694b4b00, 0x6f6f6f6e, 0xff333333, 0x73730073, 0x73737373},
+ }
+};
+
+const unsigned int gen9_avc_mode_mv_cost_table[3][52][8] =
+{
+ // I-Frame
+ {
+ {0x0d000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff000000, 0x00000000, 0x00000000},
+ {0x0f000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff010101, 0x00000000, 0x00000000},
+ {0x19000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff020202, 0x00000000, 0x00000000},
+ {0x1a000005, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff030303, 0x00000000, 0x00000000},
+ {0x1b000005, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff040404, 0x00000000, 0x00000000},
+ {0x1c000006, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff050505, 0x00000000, 0x00000000},
+ {0x1e000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff060606, 0x00000000, 0x00000000},
+ {0x28000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff070707, 0x01010001, 0x01010101},
+ {0x29000009, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff080808, 0x01010001, 0x01010101},
+ {0x2a00000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff090909, 0x03030003, 0x03030303},
+ {0x2b00000b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0a0a0a, 0x03030003, 0x03030303},
+ {0x2c00000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0b0b0b, 0x06060006, 0x06060606},
+ {0x2e00000e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0c0c0c, 0x06060006, 0x06060606},
+ {0x38000018, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0d0d0d, 0x08080008, 0x08080808},
+ {0x39000019, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0e0e0e, 0x08080008, 0x08080808},
+ {0x3a00001b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0f0f0f, 0x0b0b000b, 0x0b0b0b0b},
+ {0x3b00001c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff101010, 0x0b0b000b, 0x0b0b0b0b},
+ {0x3c00001d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff111111, 0x0d0d000d, 0x0d0d0d0d},
+ {0x3e00001f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff121212, 0x0d0d000d, 0x0d0d0d0d},
+ {0x48020028, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff131313, 0x10100010, 0x10101010},
+ {0x49020029, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff141414, 0x10100010, 0x10101010},
+ {0x4a03002a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff151515, 0x13130013, 0x13131313},
+ {0x4b03002b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff161616, 0x13130013, 0x13131313},
+ {0x4c04002b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff171717, 0x16160016, 0x16161616},
+ {0x4e04002c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff181818, 0x16160016, 0x16161616},
+ {0x5805002e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff191919, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5905002f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1a1a1a, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5a06002e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1b1b1b, 0x1e1e001e, 0x1e1e1e1e},
+ {0x5b07002f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1c1c1c, 0x1e1e001e, 0x1e1e1e1e},
+ {0x5c080039, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1d1d1d, 0x22220022, 0x22222222},
+ {0x5e09003a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1e1e1e, 0x22220022, 0x22222222},
+ {0x6828003a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1f1f1f, 0x27270027, 0x27272727},
+ {0x6929003b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff202020, 0x27270027, 0x27272727},
+ {0x6a2a003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff212121, 0x2c2c002c, 0x2c2c2c2c},
+ {0x6b2c003e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff222222, 0x2c2c002c, 0x2c2c2c2c},
+ {0x6c3a003e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff232323, 0x32320032, 0x32323232},
+ {0x6e3b0048, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff242424, 0x32320032, 0x32323232},
+ {0x783c0049, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff252525, 0x38380038, 0x38383838},
+ {0x793e004a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff262626, 0x38380038, 0x38383838},
+ {0x7a3e004b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff272727, 0x3e3e003e, 0x3e3e3e3e},
+ {0x7b48004c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff282828, 0x3e3e003e, 0x3e3e3e3e},
+ {0x7c49004e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff292929, 0x45450045, 0x45454545},
+ {0x7e4a0058, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2a2a2a, 0x45450045, 0x45454545},
+ {0x884d0059, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2b2b2b, 0x4d4d004d, 0x4d4d4d4d},
+ {0x894f005a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2c2c2c, 0x4d4d004d, 0x4d4d4d4d},
+ {0x8a58005b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2d2d2d, 0x55550055, 0x55555555},
+ {0x8b59005c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2e2e2e, 0x55550055, 0x55555555},
+ {0x8c5c005b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2f2f2f, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8e5d005c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff303030, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8f5f005d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff313131, 0x68680068, 0x68686868},
+ {0x8f68005f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff323232, 0x68680068, 0x68686868},
+ {0x8f690068, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff333333, 0x73730073, 0x73737373}
+ },
+ // P-Frame
+ {
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff010101, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff020202, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff030303, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff040404, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff050505, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff060606, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff070707, 0x01010001, 0x01010101},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff080808, 0x01010001, 0x01010101},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff090909, 0x03030003, 0x03030303},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0a0a0a, 0x03030003, 0x03030303},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0b0b0b, 0x06060006, 0x06060606},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0c0c0c, 0x06060006, 0x06060606},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0d0d0d, 0x08080008, 0x08080808},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0e0e0e, 0x08080008, 0x08080808},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0f0f0f, 0x0b0b000b, 0x0b0b0b0b},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff101010, 0x0b0b000b, 0x0b0b0b0b},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff111111, 0x0d0d000d, 0x0d0d0d0d},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff121212, 0x0d0d000d, 0x0d0d0d0d},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff131313, 0x10100010, 0x10101010},
+ {0x4d3b2f1b, 0x1a0d071d, 0x000c0018, 0x1e0f0c03, 0x2b2b291f, 0xff141414, 0x10100010, 0x10101010},
+ {0x4d3b2f1b, 0x1a0d071d, 0x000c0018, 0x1e0f0c03, 0x2b2b291f, 0xff151515, 0x13130013, 0x13131313},
+ {0x4d3b2f1b, 0x1a0d071d, 0x000c0018, 0x1e0f0c03, 0x2b2b291f, 0xff161616, 0x13130013, 0x13131313},
+ {0x593e3a1e, 0x1d190a29, 0x0018001b, 0x291a1804, 0x2f2e2c2a, 0xff171717, 0x16160016, 0x16161616},
+ {0x593e3a1e, 0x1d190a29, 0x0018001b, 0x291a1804, 0x2f2e2c2a, 0xff181818, 0x16160016, 0x16161616},
+ {0x593e3a1e, 0x1d190a29, 0x0018001b, 0x291a1804, 0x2f2e2c2a, 0xff191919, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5b493d29, 0x281c0d2b, 0x001a001e, 0x2b1d1a05, 0x39392f2d, 0xff1a1a1a, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5d4b3f2b, 0x2a1e0f2d, 0x001c0028, 0x2e1f1c06, 0x3b3b392f, 0xff1b1b1b, 0x1e1e001e, 0x1e1e1e1e},
+ {0x5d4b3f2b, 0x2a1e0f2d, 0x001c0028, 0x2e1f1c06, 0x3b3b392f, 0xff1c1c1c, 0x1e1e001e, 0x1e1e1e1e},
+ {0x5f4c492c, 0x2c28192f, 0x001e002a, 0x38291e07, 0x3d3c3b39, 0xff1d1d1d, 0x22220022, 0x22222222},
+ {0x694e4a2e, 0x2d291b39, 0x0028002b, 0x392a2808, 0x3f3e3c3a, 0xff1e1e1e, 0x22220022, 0x22222222},
+ {0x6a584b38, 0x2f2a1c3a, 0x0029002c, 0x3a2b2909, 0x48483e3b, 0xff1f1f1f, 0x27270027, 0x27272727},
+ {0x6b594d39, 0x382c1d3b, 0x002a002e, 0x3b2d2a0a, 0x49493f3d, 0xff202020, 0x27270027, 0x27272727},
+ {0x6c5a4e3a, 0x392d1f3c, 0x002b002f, 0x3c2e2b0b, 0x4a4a483e, 0xff212121, 0x2c2c002c, 0x2c2c2c2c},
+ {0x6e5b583b, 0x3b2f293e, 0x002d0039, 0x3f382d0d, 0x4c4b4a48, 0xff222222, 0x2c2c002c, 0x2c2c2c2c},
+ {0x6f5c593c, 0x3c38293f, 0x002e003a, 0x48392e0e, 0x4d4c4b49, 0xff232323, 0x32320032, 0x32323232},
+ {0x795e5a3e, 0x3d392b49, 0x0038003b, 0x493a3818, 0x4f4e4c4a, 0xff242424, 0x32320032, 0x32323232},
+ {0x7a685b48, 0x3f3a2c4a, 0x0039003c, 0x4a3b3919, 0x58584e4b, 0xff252525, 0x38380038, 0x38383838},
+ {0x7b695d49, 0x483c2d4b, 0x003a003e, 0x4b3d3a1a, 0x59594f4d, 0xff262626, 0x38380038, 0x38383838},
+ {0x7d6a5e4a, 0x4a3d2f4c, 0x003c0048, 0x4d3e3c1c, 0x5b5a594e, 0xff272727, 0x3e3e003e, 0x3e3e3e3e},
+ {0x7e6b684b, 0x4a3e384d, 0x003d0049, 0x4e483d1d, 0x5c5b5958, 0xff282828, 0x3e3e003e, 0x3e3e3e3e},
+ {0x886d694d, 0x4c483a4f, 0x003f004a, 0x58493f1f, 0x5e5d5b59, 0xff292929, 0x45450045, 0x45454545},
+ {0x896e6a4e, 0x4d493b59, 0x0048004b, 0x594a4828, 0x5f5e5c5a, 0xff2a2a2a, 0x45450045, 0x45454545},
+ {0x8a786b58, 0x4f4a3c5a, 0x0049004c, 0x5a4b4929, 0x68685e5b, 0xff2b2b2b, 0x4d4d004d, 0x4d4d4d4d},
+ {0x8b796d59, 0x584c3d5b, 0x004a004e, 0x5b4d4a2a, 0x69695f5d, 0xff2c2c2c, 0x4d4d004d, 0x4d4d4d4d},
+ {0x8c7a6e5a, 0x594d3f5c, 0x004b004f, 0x5d4e4b2b, 0x6b6a685e, 0xff2d2d2d, 0x55550055, 0x55555555},
+ {0x8e7b785b, 0x5b4f485e, 0x004d0059, 0x5e584d2d, 0x6c6b6a68, 0xff2e2e2e, 0x55550055, 0x55555555},
+ {0x8f7c795c, 0x5c58495f, 0x004e005a, 0x68594e2e, 0x6d6c6b69, 0xff2f2f2f, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8f7e7a5e, 0x5d594b69, 0x0058005b, 0x695a5838, 0x6f6e6c6a, 0xff303030, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8f887b68, 0x5f5a4c6a, 0x0059005c, 0x6a5b5939, 0x6f6f6e6b, 0xff313131, 0x68680068, 0x68686868},
+ {0x8f897d69, 0x685c4d6b, 0x005a005e, 0x6b5d5a3a, 0x6f6f6f6d, 0xff323232, 0x68680068, 0x68686868},
+ {0x8f8a7e6a, 0x695d4f6c, 0x005b0068, 0x6d5e5b3b, 0x6f6f6f6e, 0xff333333, 0x73730073, 0x73737373}
+ },
+ // B-Frame
+ {
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff010101, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff020202, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff030303, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff040404, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff050505, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff060606, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff070707, 0x01010001, 0x01010101},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff080808, 0x01010001, 0x01010101},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff090909, 0x03030003, 0x03030303},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0a0a0a, 0x03030003, 0x03030303},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0b0b0b, 0x06060006, 0x06060606},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0c0c0c, 0x06060006, 0x06060606},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0d0d0d, 0x08080008, 0x08080808},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0e0e0e, 0x08080008, 0x08080808},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0f0f0f, 0x0b0b000b, 0x0b0b0b0b},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff101010, 0x0b0b000b, 0x0b0b0b0b},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff111111, 0x0d0d000d, 0x0d0d0d0d},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff121212, 0x0d0d000d, 0x0d0d0d0d},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff131313, 0x10100010, 0x10101010},
+ {0x4f3f3d1b, 0x281d1a29, 0x000c0619, 0x19060600, 0x2c2b291f, 0xff141414, 0x10100010, 0x10101010},
+ {0x4f3f3d1b, 0x281d1a29, 0x000c0619, 0x19060600, 0x2c2b291f, 0xff151515, 0x13130013, 0x13131313},
+ {0x4f3f3d1b, 0x281d1a29, 0x000c0619, 0x19060600, 0x2c2b291f, 0xff161616, 0x13130013, 0x13131313},
+ {0x5a4a491e, 0x2b291d2c, 0x0018081c, 0x1c080800, 0x382e2c2a, 0xff171717, 0x16160016, 0x16161616},
+ {0x5a4a491e, 0x2b291d2c, 0x0018081c, 0x1c080800, 0x382e2c2a, 0xff181818, 0x16160016, 0x16161616},
+ {0x5a4a491e, 0x2b291d2c, 0x0018081c, 0x1c080800, 0x382e2c2a, 0xff191919, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5d4d4b29, 0x2d2b282f, 0x001a0a1f, 0x1f0a0a00, 0x3a392f2d, 0xff1a1a1a, 0x1a1a001a, 0x1a1a1a1a},
+ {0x5f4f4d2b, 0x382d2a39, 0x001c0c29, 0x290c0c00, 0x3c3b392f, 0xff1b1b1b, 0x1e1e001e, 0x1e1e1e1e},
+ {0x5f4f4d2b, 0x382d2a39, 0x001c0c29, 0x290c0c00, 0x3c3b392f, 0xff1c1c1c, 0x1e1e001e, 0x1e1e1e1e},
+ {0x69594f2c, 0x392f2b3b, 0x001e0e2b, 0x2b0e0e00, 0x3e3c3b39, 0xff1d1d1d, 0x22220022, 0x22222222},
+ {0x6a5a592e, 0x3b392d3c, 0x0028182c, 0x2c181800, 0x483e3c3a, 0xff1e1e1e, 0x22220022, 0x22222222},
+ {0x6b5b5a38, 0x3c3a2f3e, 0x0029192e, 0x2e191900, 0x49483e3b, 0xff1f1f1f, 0x27270027, 0x27272727},
+ {0x6d5d5b39, 0x3d3b383f, 0x002a1a2f, 0x2f1a1a00, 0x4a493f3d, 0xff202020, 0x27270027, 0x27272727},
+ {0x6e5e5c3a, 0x3e3c3948, 0x002b1b38, 0x381b1b00, 0x4b4a483e, 0xff212121, 0x2c2c002c, 0x2c2c2c2c},
+ {0x78685e3b, 0x493e3b4a, 0x002d1d3a, 0x3a1d1d00, 0x4d4b4a48, 0xff222222, 0x2c2c002c, 0x2c2c2c2c},
+ {0x79695f3c, 0x493f3b4b, 0x002e1e3b, 0x3b1e1e00, 0x4e4c4b49, 0xff232323, 0x32320032, 0x32323232},
+ {0x7a6a693e, 0x4b493d4c, 0x0038283c, 0x3c282800, 0x584e4c4a, 0xff242424, 0x32320032, 0x32323232},
+ {0x7b6b6a48, 0x4c4a3f4e, 0x0039293e, 0x3e292900, 0x59584e4b, 0xff252525, 0x38380038, 0x38383838},
+ {0x7d6d6b49, 0x4d4b484f, 0x003a2a3f, 0x3f2a2a00, 0x5a594f4d, 0xff262626, 0x38380038, 0x38383838},
+ {0x7e6e6c4a, 0x4f4c4959, 0x003c2c49, 0x492c2c00, 0x5c5a594e, 0xff272727, 0x3e3e003e, 0x3e3e3e3e},
+ {0x88786d4b, 0x584d4a59, 0x003d2d49, 0x492d2d00, 0x5d5b5958, 0xff282828, 0x3e3e003e, 0x3e3e3e3e},
+ {0x89796f4d, 0x5a4f4c5b, 0x003f2f4b, 0x4b2f2f00, 0x5f5d5b59, 0xff292929, 0x45450045, 0x45454545},
+ {0x8a7a794e, 0x5b594d5c, 0x0048384c, 0x4c383800, 0x685e5c5a, 0xff2a2a2a, 0x45450045, 0x45454545},
+ {0x8b7b7a58, 0x5c5a4f5e, 0x0049394e, 0x4e393900, 0x69685e5b, 0xff2b2b2b, 0x4d4d004d, 0x4d4d4d4d},
+ {0x8d7d7b59, 0x5d5b585f, 0x004a3a4f, 0x4f3a3a00, 0x6a695f5d, 0xff2c2c2c, 0x4d4d004d, 0x4d4d4d4d},
+ {0x8e7e7c5a, 0x5f5c5968, 0x004b3b58, 0x583b3b00, 0x6b6a685e, 0xff2d2d2d, 0x55550055, 0x55555555},
+ {0x8f887e5b, 0x685e5a6a, 0x004d3d5a, 0x5a3d3d00, 0x6d6b6a68, 0xff2e2e2e, 0x55550055, 0x55555555},
+ {0x8f897f5c, 0x695f5c6b, 0x004e3e5b, 0x5b3e3e00, 0x6e6c6b69, 0xff2f2f2f, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8f8a895e, 0x6b695d6c, 0x0058485c, 0x5c484800, 0x6f6e6c6a, 0xff303030, 0x5e5e005e, 0x5e5e5e5e},
+ {0x8f8b8a68, 0x6c6a5f6e, 0x0059495e, 0x5e494900, 0x6f6f6e6b, 0xff313131, 0x68680068, 0x68686868},
+ {0x8f8d8b69, 0x6d6b686f, 0x005a4a5f, 0x5f4a4a00, 0x6f6f6f6d, 0xff323232, 0x68680068, 0x68686868},
+ {0x8f8e8c6a, 0x6f6c6979, 0x005b4b69, 0x694b4b00, 0x6f6f6f6e, 0xff333333, 0x73730073, 0x73737373}
+ }
+};
+const unsigned char gen75_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb[576] =
+{
+ 0x01, 0x02, 0x03, 0x05, 0x06, 0x01, 0x01, 0x02, 0x03, 0x05, 0x00, 0x00, 0x01, 0x02, 0x03, 0xff,
+ 0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xfe, 0xfe, 0xff, 0x00, 0x01, 0xfd, 0xfd,
+ 0xff, 0xff, 0x00, 0xfb, 0xfd, 0xfe, 0xff, 0xff, 0xfa, 0xfb, 0xfd, 0xfe, 0xff, 0x00, 0x04, 0x1e,
+ 0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x02, 0x03, 0x05, 0x06, 0x01, 0x01, 0x02, 0x03, 0x05, 0x00, 0x01, 0x01, 0x02, 0x03, 0xff,
+ 0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0x00, 0x01, 0xfe, 0xff,
+ 0xff, 0xff, 0x00, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0xfb, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x04, 0x1e,
+ 0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x04, 0x05, 0x06, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x01, 0x02, 0x04, 0x05, 0x01, 0x01, 0x01, 0x02, 0x04, 0x00, 0x00, 0x01, 0x01, 0x02, 0xff,
+ 0x00, 0x00, 0x01, 0x01, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0x01, 0xfe, 0xff,
+ 0xff, 0xff, 0x00, 0xfd, 0xfe, 0xff, 0xff, 0x00, 0xfb, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x02, 0x14,
+ 0x28, 0x46, 0x82, 0xa0, 0xc8, 0xff, 0x04, 0x04, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03,
+ 0x03, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x03, 0xff, 0xff, 0x00, 0x00, 0x00,
+ 0x01, 0x02, 0x02, 0x02, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0xfe, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe,
+ 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0xfe, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03,
+ 0x03, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x03, 0xff, 0xff, 0x00, 0x00, 0x00,
+ 0x01, 0x02, 0x02, 0x02, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0xfe, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe,
+ 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0xfe, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03,
+ 0x03, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x03, 0xff, 0xff, 0x00, 0x00, 0x00,
+ 0x01, 0x02, 0x02, 0x02, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0xfe, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe,
+ 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0xfe, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+const unsigned char gen9_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb[576] =
+{
+ 0x01, 0x02, 0x03, 0x05, 0x06, 0x01, 0x01, 0x02, 0x03, 0x05, 0x00, 0x00, 0x01, 0x02, 0x03, 0xff,
+ 0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xfe, 0xfe, 0xff, 0x00, 0x01, 0xfd, 0xfd,
+ 0xff, 0xff, 0x00, 0xfb, 0xfd, 0xfe, 0xff, 0xff, 0xfa, 0xfb, 0xfd, 0xfe, 0xff, 0x00, 0x04, 0x1e,
+ 0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x02, 0x03, 0x05, 0x06, 0x01, 0x01, 0x02, 0x03, 0x05, 0x00, 0x01, 0x01, 0x02, 0x03, 0xff,
+ 0x00, 0x00, 0x01, 0x02, 0xff, 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0x00, 0x01, 0xfe, 0xff,
+ 0xff, 0xff, 0x00, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0xfb, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x04, 0x1e,
+ 0x3c, 0x50, 0x78, 0x8c, 0xc8, 0xff, 0x04, 0x05, 0x06, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x01, 0x02, 0x04, 0x05, 0x01, 0x01, 0x01, 0x02, 0x04, 0x00, 0x00, 0x01, 0x01, 0x02, 0xff,
+ 0x00, 0x00, 0x01, 0x01, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0x01, 0xfe, 0xff,
+ 0xff, 0xff, 0x00, 0xfd, 0xfe, 0xff, 0xff, 0x00, 0xfb, 0xfc, 0xfe, 0xff, 0xff, 0x00, 0x02, 0x14,
+ 0x28, 0x46, 0x82, 0xa0, 0xc8, 0xff, 0x04, 0x04, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03,
+ 0x03, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x03, 0xff, 0xff, 0x00, 0x00, 0x00,
+ 0x01, 0x02, 0x02, 0x02, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0xfe, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe,
+ 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0xfe, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03,
+ 0x03, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x03, 0xff, 0xff, 0x00, 0x00, 0x00,
+ 0x01, 0x02, 0x02, 0x02, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0xfe, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe,
+ 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0xfe, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03,
+ 0x03, 0x04, 0xff, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x03, 0xff, 0xff, 0x00, 0x00, 0x00,
+ 0x01, 0x02, 0x02, 0x02, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0xfe, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe, 0xff, 0xff, 0xff, 0x00, 0x00, 0x01, 0x01, 0x02, 0xfe,
+ 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x01, 0xfe, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+// SkipVal (DW offset 9) in the following table needs to be changed by Driver based on the BlockbasedSkip and Transform Flag.
+// Kernel indexes this table based on the MB QP.
+const unsigned int gen9_avc_mb_brc_const_data[3][AVC_QP_MAX][16] =
+{
+ //I-slice
+ {
+ //ModeCOST(0), ModeCOST(1), ModeCOST(2), MVCOST(3), MVCOST(4), QP(5), FTQ Thds(6), FTQ Thds(7), RefCost(8), SkipVal(9), IntraSF(10) ,Zero(11), Zero(12), Zero(13), Zero(14) , Zero(15)
+ {0x0d000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x0f000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x19000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff020202, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x1a000005, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff030303, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x1b000005, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff040404, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x1c000006, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff050505, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x1e000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff060606, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x28000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff070707, 0x01010001, 0x01010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x29000009, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff080808, 0x01010001, 0x01010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x2a00000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff090909, 0x03030003, 0x03030303, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x2b00000b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0a0a0a, 0x03030003, 0x03030303, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x2c00000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0b0b0b, 0x06060006, 0x06060606, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x2e00000e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0c0c0c, 0x06060006, 0x06060606, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x38000018, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0d0d0d, 0x08080008, 0x08080808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x39000019, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0e0e0e, 0x08080008, 0x08080808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a00001b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff0f0f0f, 0x0b0b000b, 0x0b0b0b0b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3b00001c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff101010, 0x0b0b000b, 0x0b0b0b0b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3c00001d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff111111, 0x0d0d000d, 0x0d0d0d0d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3e00001f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff121212, 0x0d0d000d, 0x0d0d0d0d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x48020028, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff131313, 0x10100010, 0x10101010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x49020029, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff141414, 0x10100010, 0x10101010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4a03002a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff151515, 0x13130013, 0x13131313, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4b03002b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff161616, 0x13130013, 0x13131313, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4c04002b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff171717, 0x16160016, 0x16161616, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4e04002c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff181818, 0x16160016, 0x16161616, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5805002e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff191919, 0x1a1a001a, 0x1a1a1a1a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5905002f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1a1a1a, 0x1a1a001a, 0x1a1a1a1a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5a06002e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1b1b1b, 0x1e1e001e, 0x1e1e1e1e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5b07002f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1c1c1c, 0x1e1e001e, 0x1e1e1e1e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5c080039, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1d1d1d, 0x22220022, 0x22222222, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5e09003a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1e1e1e, 0x22220022, 0x22222222, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6828003a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff1f1f1f, 0x27270027, 0x27272727, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6929003b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff202020, 0x27270027, 0x27272727, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6a2a003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff212121, 0x2c2c002c, 0x2c2c2c2c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6b2c003e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff222222, 0x2c2c002c, 0x2c2c2c2c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6c3a003e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff232323, 0x32320032, 0x32323232, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6e3b0048, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff242424, 0x32320032, 0x32323232, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x783c0049, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff252525, 0x38380038, 0x38383838, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x793e004a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff262626, 0x38380038, 0x38383838, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7a3e004b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff272727, 0x3e3e003e, 0x3e3e3e3e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7b48004c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff282828, 0x3e3e003e, 0x3e3e3e3e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7c49004e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff292929, 0x45450045, 0x45454545, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7e4a0058, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2a2a2a, 0x45450045, 0x45454545, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x884d0059, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2b2b2b, 0x4d4d004d, 0x4d4d4d4d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x894f005a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2c2c2c, 0x4d4d004d, 0x4d4d4d4d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8a58005b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2d2d2d, 0x55550055, 0x55555555, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8b59005c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2e2e2e, 0x55550055, 0x55555555, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8c5c005b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff2f2f2f, 0x5e5e005e, 0x5e5e5e5e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8e5d005c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff303030, 0x5e5e005e, 0x5e5e5e5e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f5f005d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff313131, 0x68680068, 0x68686868, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f68005f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff323232, 0x68680068, 0x68686868, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f690068, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff333333, 0x73730073, 0x73737373, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
+ },
+ //P-slice
+ {
+ //ModeCOST(0), ModeCOST(1), ModeCOST(2), MVCOST(3), MVCOST(4), QP(5), FTQ Thds(6), FTQ Thds(7), RefCost(8), SkipVal(9), IntraSF(10) ,Zero(11), Zero(12), Zero(13), Zero(14) , Zero(15)
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff020202, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff030303, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff040404, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff050505, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff060606, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff070707, 0x01010001, 0x01010101, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff080808, 0x01010001, 0x01010101, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff090909, 0x03030003, 0x03030303, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0a0a0a, 0x03030003, 0x03030303, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0b0b0b, 0x06060006, 0x06060606, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0c0c0c, 0x06060006, 0x06060606, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0d0d0d, 0x08080008, 0x08080808, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0e0e0e, 0x08080008, 0x08080808, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x391e1a07, 0x06040208, 0x00040005, 0x09050401, 0x0f0e0c0a, 0xff0f0f0f, 0x0b0b000b, 0x0b0b0b0b, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff101010, 0x0b0b000b, 0x0b0b0b0b, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff111111, 0x0d0d000d, 0x0d0d0d0d, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff121212, 0x0d0d000d, 0x0d0d0d0d, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x492e2a0e, 0x0d090519, 0x0008000b, 0x190a0802, 0x1f1e1c1a, 0xff131313, 0x10100010, 0x10101010, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4d3b2f1b, 0x1a0d071d, 0x000c0018, 0x1e0f0c03, 0x2b2b291f, 0xff141414, 0x10100010, 0x10101010, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4d3b2f1b, 0x1a0d071d, 0x000c0018, 0x1e0f0c03, 0x2b2b291f, 0xff151515, 0x13130013, 0x13131313, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4d3b2f1b, 0x1a0d071d, 0x000c0018, 0x1e0f0c03, 0x2b2b291f, 0xff161616, 0x13130013, 0x13131313, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x593e3a1e, 0x1d190a29, 0x0018001b, 0x291a1804, 0x2f2e2c2a, 0xff171717, 0x16160016, 0x16161616, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x593e3a1e, 0x1d190a29, 0x0018001b, 0x291a1804, 0x2f2e2c2a, 0xff181818, 0x16160016, 0x16161616, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x593e3a1e, 0x1d190a29, 0x0018001b, 0x291a1804, 0x2f2e2c2a, 0xff191919, 0x1a1a001a, 0x1a1a1a1a, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5b493d29, 0x281c0d2b, 0x001a001e, 0x2b1d1a05, 0x39392f2d, 0xff1a1a1a, 0x1a1a001a, 0x1a1a1a1a, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5d4b3f2b, 0x2a1e0f2d, 0x001c0028, 0x2e1f1c06, 0x3b3b392f, 0xff1b1b1b, 0x1e1e001e, 0x1e1e1e1e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5d4b3f2b, 0x2a1e0f2d, 0x001c0028, 0x2e1f1c06, 0x3b3b392f, 0xff1c1c1c, 0x1e1e001e, 0x1e1e1e1e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5f4c492c, 0x2c28192f, 0x001e002a, 0x38291e07, 0x3d3c3b39, 0xff1d1d1d, 0x22220022, 0x22222222, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x694e4a2e, 0x2d291b39, 0x0028002b, 0x392a2808, 0x3f3e3c3a, 0xff1e1e1e, 0x22220022, 0x22222222, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6a584b38, 0x2f2a1c3a, 0x0029002c, 0x3a2b2909, 0x48483e3b, 0xff1f1f1f, 0x27270027, 0x27272727, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6b594d39, 0x382c1d3b, 0x002a002e, 0x3b2d2a0a, 0x49493f3d, 0xff202020, 0x27270027, 0x27272727, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6c5a4e3a, 0x392d1f3c, 0x002b002f, 0x3c2e2b0b, 0x4a4a483e, 0xff212121, 0x2c2c002c, 0x2c2c2c2c, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6e5b583b, 0x3b2f293e, 0x002d0039, 0x3f382d0d, 0x4c4b4a48, 0xff222222, 0x2c2c002c, 0x2c2c2c2c, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6f5c593c, 0x3c38293f, 0x002e003a, 0x48392e0e, 0x4d4c4b49, 0xff232323, 0x32320032, 0x32323232, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x795e5a3e, 0x3d392b49, 0x0038003b, 0x493a3818, 0x4f4e4c4a, 0xff242424, 0x32320032, 0x32323232, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7a685b48, 0x3f3a2c4a, 0x0039003c, 0x4a3b3919, 0x58584e4b, 0xff252525, 0x38380038, 0x38383838, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7b695d49, 0x483c2d4b, 0x003a003e, 0x4b3d3a1a, 0x59594f4d, 0xff262626, 0x38380038, 0x38383838, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7d6a5e4a, 0x4a3d2f4c, 0x003c0048, 0x4d3e3c1c, 0x5b5a594e, 0xff272727, 0x3e3e003e, 0x3e3e3e3e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7e6b684b, 0x4a3e384d, 0x003d0049, 0x4e483d1d, 0x5c5b5958, 0xff282828, 0x3e3e003e, 0x3e3e3e3e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x886d694d, 0x4c483a4f, 0x003f004a, 0x58493f1f, 0x5e5d5b59, 0xff292929, 0x45450045, 0x45454545, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x896e6a4e, 0x4d493b59, 0x0048004b, 0x594a4828, 0x5f5e5c5a, 0xff2a2a2a, 0x45450045, 0x45454545, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8a786b58, 0x4f4a3c5a, 0x0049004c, 0x5a4b4929, 0x68685e5b, 0xff2b2b2b, 0x4d4d004d, 0x4d4d4d4d, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8b796d59, 0x584c3d5b, 0x004a004e, 0x5b4d4a2a, 0x69695f5d, 0xff2c2c2c, 0x4d4d004d, 0x4d4d4d4d, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8c7a6e5a, 0x594d3f5c, 0x004b004f, 0x5d4e4b2b, 0x6b6a685e, 0xff2d2d2d, 0x55550055, 0x55555555, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8e7b785b, 0x5b4f485e, 0x004d0059, 0x5e584d2d, 0x6c6b6a68, 0xff2e2e2e, 0x55550055, 0x55555555, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f7c795c, 0x5c58495f, 0x004e005a, 0x68594e2e, 0x6d6c6b69, 0xff2f2f2f, 0x5e5e005e, 0x5e5e5e5e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f7e7a5e, 0x5d594b69, 0x0058005b, 0x695a5838, 0x6f6e6c6a, 0xff303030, 0x5e5e005e, 0x5e5e5e5e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f887b68, 0x5f5a4c6a, 0x0059005c, 0x6a5b5939, 0x6f6f6e6b, 0xff313131, 0x68680068, 0x68686868, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f897d69, 0x685c4d6b, 0x005a005e, 0x6b5d5a3a, 0x6f6f6f6d, 0xff323232, 0x68680068, 0x68686868, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f8a7e6a, 0x695d4f6c, 0x005b0068, 0x6d5e5b3b, 0x6f6f6f6e, 0xff333333, 0x73730073, 0x73737373, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
+ },
+ //B-slice
+ {
+ //ModeCOST(0), ModeCOST(1), ModeCOST(2), MVCOST(3), MVCOST(4), QP(5), FTQ Thds(6), FTQ Thds(7), RefCost(8), SkipVal(9), IntraSF(10) ,Zero(11), Zero(12), Zero(13), Zero(14) , Zero(15)
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff020202, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff030303, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff040404, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff050505, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff060606, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff070707, 0x01010001, 0x01010101, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff080808, 0x01010001, 0x01010101, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff090909, 0x03030003, 0x03030303, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0a0a0a, 0x03030003, 0x03030303, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0b0b0b, 0x06060006, 0x06060606, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0c0c0c, 0x06060006, 0x06060606, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0d0d0d, 0x08080008, 0x08080808, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0e0e0e, 0x08080008, 0x08080808, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x3a2a2907, 0x0a08060c, 0x00040206, 0x06020200, 0x180e0c0a, 0xff0f0f0f, 0x0b0b000b, 0x0b0b0b0b, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff101010, 0x0b0b000b, 0x0b0b0b0b, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff111111, 0x0d0d000d, 0x0d0d0d0d, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff121212, 0x0d0d000d, 0x0d0d0d0d, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4a3a390e, 0x1b190d1c, 0x0008040c, 0x0c040400, 0x281e1c1a, 0xff131313, 0x10100010, 0x10101010, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4f3f3d1b, 0x281d1a29, 0x000c0619, 0x19060600, 0x2c2b291f, 0xff141414, 0x10100010, 0x10101010, 0x00000000, 0x00000000, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4f3f3d1b, 0x281d1a29, 0x000c0619, 0x19060600, 0x2c2b291f, 0xff151515, 0x13130013, 0x13131313, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x4f3f3d1b, 0x281d1a29, 0x000c0619, 0x19060600, 0x2c2b291f, 0xff161616, 0x13130013, 0x13131313, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5a4a491e, 0x2b291d2c, 0x0018081c, 0x1c080800, 0x382e2c2a, 0xff171717, 0x16160016, 0x16161616, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5a4a491e, 0x2b291d2c, 0x0018081c, 0x1c080800, 0x382e2c2a, 0xff181818, 0x16160016, 0x16161616, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5a4a491e, 0x2b291d2c, 0x0018081c, 0x1c080800, 0x382e2c2a, 0xff191919, 0x1a1a001a, 0x1a1a1a1a, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5d4d4b29, 0x2d2b282f, 0x001a0a1f, 0x1f0a0a00, 0x3a392f2d, 0xff1a1a1a, 0x1a1a001a, 0x1a1a1a1a, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5f4f4d2b, 0x382d2a39, 0x001c0c29, 0x290c0c00, 0x3c3b392f, 0xff1b1b1b, 0x1e1e001e, 0x1e1e1e1e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x5f4f4d2b, 0x382d2a39, 0x001c0c29, 0x290c0c00, 0x3c3b392f, 0xff1c1c1c, 0x1e1e001e, 0x1e1e1e1e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x69594f2c, 0x392f2b3b, 0x001e0e2b, 0x2b0e0e00, 0x3e3c3b39, 0xff1d1d1d, 0x22220022, 0x22222222, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6a5a592e, 0x3b392d3c, 0x0028182c, 0x2c181800, 0x483e3c3a, 0xff1e1e1e, 0x22220022, 0x22222222, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6b5b5a38, 0x3c3a2f3e, 0x0029192e, 0x2e191900, 0x49483e3b, 0xff1f1f1f, 0x27270027, 0x27272727, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6d5d5b39, 0x3d3b383f, 0x002a1a2f, 0x2f1a1a00, 0x4a493f3d, 0xff202020, 0x27270027, 0x27272727, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x6e5e5c3a, 0x3e3c3948, 0x002b1b38, 0x381b1b00, 0x4b4a483e, 0xff212121, 0x2c2c002c, 0x2c2c2c2c, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x78685e3b, 0x493e3b4a, 0x002d1d3a, 0x3a1d1d00, 0x4d4b4a48, 0xff222222, 0x2c2c002c, 0x2c2c2c2c, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x79695f3c, 0x493f3b4b, 0x002e1e3b, 0x3b1e1e00, 0x4e4c4b49, 0xff232323, 0x32320032, 0x32323232, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7a6a693e, 0x4b493d4c, 0x0038283c, 0x3c282800, 0x584e4c4a, 0xff242424, 0x32320032, 0x32323232, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7b6b6a48, 0x4c4a3f4e, 0x0039293e, 0x3e292900, 0x59584e4b, 0xff252525, 0x38380038, 0x38383838, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7d6d6b49, 0x4d4b484f, 0x003a2a3f, 0x3f2a2a00, 0x5a594f4d, 0xff262626, 0x38380038, 0x38383838, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x7e6e6c4a, 0x4f4c4959, 0x003c2c49, 0x492c2c00, 0x5c5a594e, 0xff272727, 0x3e3e003e, 0x3e3e3e3e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x88786d4b, 0x584d4a59, 0x003d2d49, 0x492d2d00, 0x5d5b5958, 0xff282828, 0x3e3e003e, 0x3e3e3e3e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x89796f4d, 0x5a4f4c5b, 0x003f2f4b, 0x4b2f2f00, 0x5f5d5b59, 0xff292929, 0x45450045, 0x45454545, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8a7a794e, 0x5b594d5c, 0x0048384c, 0x4c383800, 0x685e5c5a, 0xff2a2a2a, 0x45450045, 0x45454545, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8b7b7a58, 0x5c5a4f5e, 0x0049394e, 0x4e393900, 0x69685e5b, 0xff2b2b2b, 0x4d4d004d, 0x4d4d4d4d, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8d7d7b59, 0x5d5b585f, 0x004a3a4f, 0x4f3a3a00, 0x6a695f5d, 0xff2c2c2c, 0x4d4d004d, 0x4d4d4d4d, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8e7e7c5a, 0x5f5c5968, 0x004b3b58, 0x583b3b00, 0x6b6a685e, 0xff2d2d2d, 0x55550055, 0x55555555, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f887e5b, 0x685e5a6a, 0x004d3d5a, 0x5a3d3d00, 0x6d6b6a68, 0xff2e2e2e, 0x55550055, 0x55555555, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f897f5c, 0x695f5c6b, 0x004e3e5b, 0x5b3e3e00, 0x6e6c6b69, 0xff2f2f2f, 0x5e5e005e, 0x5e5e5e5e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f8a895e, 0x6b695d6c, 0x0058485c, 0x5c484800, 0x6f6e6c6a, 0xff303030, 0x5e5e005e, 0x5e5e5e5e, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f8b8a68, 0x6c6a5f6e, 0x0059495e, 0x5e494900, 0x6f6f6e6b, 0xff313131, 0x68680068, 0x68686868, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f8d8b69, 0x6d6b686f, 0x005a4a5f, 0x5f4a4a00, 0x6f6f6f6d, 0xff323232, 0x68680068, 0x68686868, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+ {0x8f8e8c6a, 0x6f6c6979, 0x005b4b69, 0x694b4b00, 0x6f6f6f6e, 0xff333333, 0x73730073, 0x73737373, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
+ }
+};
+
+// AVC MBEnc RefCost tables, index [CodingType][QP]
+// QP is from 0 - 51, pad it to 64 since BRC needs each subarray size to be 128bytes
+const unsigned short gen9_avc_ref_cost[3][64] =
+{
+ // I-frame
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000
+ },
+ // P-slice
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000
+ },
+ //B-slice
+ {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000
+ }
+};
+
+const bool gen9_avc_mbbrc_enable[PRESET_NUM] =
+{
+ false, true, true, false, false, false, false, false
+};
+
+const unsigned int gen9_avc_super_hme[PRESET_NUM] =
+{
+ 0, 1, 1, 1, 1, 1, 1, 1
+};
+
+const unsigned int gen9_avc_ultra_hme[PRESET_NUM] =
+{
+ 0, 1, 1, 1, 1, 1, 1, 0
+};
+
+// 1 for P, 3 for P & B
+const unsigned int gen9_avc_all_fractional[PRESET_NUM] =
+{
+ 0, 3, 3, 3, 3, 3, 3, 0
+};
+
+const unsigned char gen9_avc_max_ref_id0_progressive_4k[PRESET_NUM] =
+{
+ 0, 3, 3, 2, 2, 2, 0, 0
+};
+
+const unsigned char gen9_avc_max_ref_id0[PRESET_NUM] =
+{
+ 0, 7, 5, 2, 2, 2, 0, 0
+};
+
+const unsigned char gen9_avc_max_b_ref_id0[PRESET_NUM] =
+{
+ 0, 3, 3, 1, 1, 1, 0, 0
+};
+
+const unsigned char gen9_avc_max_ref_id1[PRESET_NUM] =
+{
+ 0, 1, 1, 1, 1, 1, 0, 0
+};
+
+const unsigned int gen9_avc_inter_rounding_p[PRESET_NUM] =
+{
+ 0, 3, 3, 3, 3, 3, 3, 3
+};
+
+const unsigned int gen9_avc_inter_rounding_b_ref[PRESET_NUM] =
+{
+ 0, 2, 2, 2, 2, 2, 2, 2
+};
+
+const unsigned int gen9_avc_inter_rounding_b[PRESET_NUM] =
+{
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+// This applies only for progressive pictures. For interlaced, CAF is currently not disabled.
+const unsigned int gen9_avc_disable_all_fractional_check_for_high_res[PRESET_NUM] =
+{
+ 0, 0, 0, 1, 1, 1, 1, 1
+};
+
+unsigned char gen9_avc_adaptive_inter_rounding_p[AVC_QP_MAX] =
+{
+//QP = 0 1 2 3 4 5 6 7 8 9 10 11 12
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, //QP=[0~12]
+ 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, //QP=[13~25]
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, //QP=[26~38]
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 //QP=[39~51]
+};
+
+unsigned char gen9_avc_adaptive_inter_rounding_b[AVC_QP_MAX] =
+{
+//QP = 0 1 2 3 4 5 6 7 8 9 10 11 12
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, //QP=[0~12]
+ 4, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, //QP=[13~25]
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26~38]
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39~51]
+};
+
+unsigned char gen9_avc_adaptive_inter_rounding_p_without_b[AVC_QP_MAX] =
+{
+//QP = 0 1 2 3 4 5 6 7 8 9 10 11 12
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, //QP=[0~12]
+ 3, 3, 3, 3, 3, 3, 3, 3, 1, 0, 0, 0, 0, //QP=[13~25]
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26~38]
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39~51]
+};
+
+const unsigned int gen9_avc_trellis_quantization_enable[PRESET_NUM] =
+{
+ 0, 1, 0, 0, 0, 0, 0, 0
+};
+
+const unsigned int gen9_avc_trellis_quantization_rounding[PRESET_NUM] =
+{
+ 0, 6, 0, 0, 0, 0, 0, 0
+};
+
+const unsigned int gen9_avc_enable_adaptive_trellis_quantization[PRESET_NUM] =
+{
+ 0, 1, 0, 0, 0, 0, 0, 0
+};
+
+const unsigned int gen9_avc_super_combine_dist[PRESET_NUM + 1] =
+{
+ 0, 1, 1, 5, 5, 5, 9, 9, 0
+};
+
+const unsigned char gen9_avc_b_me_method[PRESET_NUM + 1] =
+{
+ 0, 4, 4, 6, 6, 6, 6, 4, 7
+};
+
+const unsigned char gen9_avc_p_me_method[PRESET_NUM + 1] =
+{
+ 0, 4, 4, 6, 6, 6, 6, 4, 7
+};
+
+const unsigned int gen9_avc_enable_adaptive_search[PRESET_NUM] =
+{
+ 0, 1, 1, 1, 1, 1, 0, 0
+};
+
+const unsigned int gen9_avc_max_len_sp[PRESET_NUM] =
+{
+ 0, 57, 57, 25, 25, 25, 16, 9
+};
+
+const unsigned int gen9_avc_max_ftq_based_skip[PRESET_NUM] =
+{
+ 0, 3, 3, 3, 3, 3, 3, 0
+};
+
+const unsigned int gen9_avc_mr_disable_qp_check[PRESET_NUM] =
+{
+ 0, 1, 0, 0, 0, 0, 0, 0
+};
+
+const unsigned int gen9_avc_multi_pred[PRESET_NUM] =
+{
+ 0, 3, 3, 0, 0, 0, 0, 0
+};
+
+const unsigned int gen9_avc_hme_b_combine_len[PRESET_NUM] =
+{
+ 0, 8, 8, 8, 8, 8, 8, 8
+};
+const unsigned int gen9_avc_hme_combine_len[PRESET_NUM] =
+{
+ 0, 8, 8, 8, 8, 8, 16, 8
+};
+
+const unsigned int gen9_avc_search_x[PRESET_NUM] =
+{
+ 0, 48, 48, 48, 48, 48, 48, 28
+};
+const unsigned int gen9_avc_search_y[PRESET_NUM] =
+{
+ 0, 40, 40, 40, 40, 40, 40, 28
+};
+
+const unsigned int gen9_avc_b_search_x[PRESET_NUM] =
+{
+ 0, 32, 32, 32, 32, 32, 32, 24
+};
+const unsigned int gen9_avc_b_search_y[PRESET_NUM] =
+{
+ 0, 32, 32, 32, 32, 32, 32, 24
+};
+
+const unsigned char gen9_avc_enable_adaptive_tx_decision[PRESET_NUM] =
+{
+ 0, 1, 1, 1, 1, 1, 1, 0
+};
+
+const char gen9_avc_kernel_mode[PRESET_NUM] =
+{
+ 1, 0, 0, 1, 1, 1, 1, 2
+};
diff --git a/src/gen9_avc_const_def.h b/src/gen9_avc_const_def.h
new file mode 100755
index 0000000..51e7809
--- /dev/null
+++ b/src/gen9_avc_const_def.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu <***@intel.com>
+ *
+ */
+
+#ifndef GEN9_AVC_const_DEF_H
+#define GEN9_AVC_const_DEF_H
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define GEN9_AVC_NUM_REF_CHECK_WIDTH 3840
+#define GEN9_AVC_NUM_REF_CHECK_HEIGHT 2160
+#define GEN9_AVC_MBENC_CURBE_SIZE 88
+#define AVC_QP_MAX 52
+#define PRESET_NUM 8
+
+extern const char gen9_avc_sfd_cost_table_p_frame[AVC_QP_MAX];
+extern const char gen9_avc_sfd_cost_table_b_frame[AVC_QP_MAX];
+
+extern const unsigned int gen9_avc_old_intra_mode_cost[AVC_QP_MAX];
+extern const unsigned int gen9_avc_mv_cost_p_skip_adjustment[AVC_QP_MAX];
+extern const unsigned short gen9_avc_skip_value_p[2][2][64];
+extern const unsigned short gen9_avc_skip_value_b[2][2][64];
+
+// QP is from 0 - 51, pad it to 64 since BRC needs array size to be 64 bytes
+extern const unsigned char gen9_avc_adaptive_intra_scaling_factor[64];
+extern const unsigned char gen9_avc_intra_scaling_factor[64];
+// AVC MBEnc CURBE init data
+extern const unsigned int gen9_avc_mbenc_curbe_normal_i_frame_init_data[GEN9_AVC_MBENC_CURBE_SIZE];
+extern const unsigned int gen9_avc_mbenc_curbe_normal_p_frame_init_data[GEN9_AVC_MBENC_CURBE_SIZE];
+extern const unsigned int gen9_avc_mbenc_curbe_normal_b_frame_init_data[GEN9_AVC_MBENC_CURBE_SIZE];
+// AVC I_DIST CURBE init data
+extern const unsigned int gen9_avc_mbenc_curbe_i_frame_dist_init_data[GEN9_AVC_MBENC_CURBE_SIZE];
+// AVC ME CURBE init data
+extern const unsigned int gen9_avc_me_curbe_init_data[39];
+//extern const unsigned int gen9_avc_brc_init_reset_curbe_init_data[24];
+//extern const unsigned int gen9_avc_frame_brc_update_curbe_init_data[16];
+//extern const unsigned int gen9_avc_mb_brc_update_curbe_init_data[7];
+extern const unsigned int gen75_avc_mode_mv_cost_table[3][52][8];
+extern const unsigned int gen9_avc_mode_mv_cost_table[3][52][8];
+extern const unsigned char gen75_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb[576];
+extern const unsigned char gen9_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb[576];
+// SkipVal (DW offset 9) in the following table needs to be changed by Driver based on the BlockbasedSkip and Transform Flag.
+// Kernel indexes this table based on the MB QP.
+extern const unsigned int gen9_avc_mb_brc_const_data[3][AVC_QP_MAX][16];
+extern const unsigned short gen9_avc_ref_cost[3][64];
+
+//
+extern const bool gen9_avc_mbbrc_enable[PRESET_NUM];
+extern const unsigned int gen9_avc_super_hme[PRESET_NUM];
+extern const unsigned int gen9_avc_ultra_hme[PRESET_NUM];
+
+// 1 for P, 3 for P & B
+extern const unsigned int gen9_avc_all_fractional[PRESET_NUM];
+extern const unsigned char gen9_avc_max_ref_id0_progressive_4k[PRESET_NUM];
+extern const unsigned char gen9_avc_max_ref_id0[PRESET_NUM];
+extern const unsigned char gen9_avc_max_b_ref_id0[PRESET_NUM];
+extern const unsigned char gen9_avc_max_ref_id1[PRESET_NUM];
+extern const unsigned int gen9_avc_inter_rounding_p[PRESET_NUM];
+extern const unsigned int gen9_avc_inter_rounding_b_ref[PRESET_NUM];
+extern const unsigned int gen9_avc_inter_rounding_b[PRESET_NUM];
+// This applies only for progressive pictures. For interlaced, CAF is currently not disabled.
+extern const unsigned int gen9_avc_disable_all_fractional_check_for_high_res[PRESET_NUM];
+extern unsigned char gen9_avc_adaptive_inter_rounding_p[AVC_QP_MAX];
+extern unsigned char gen9_avc_adaptive_inter_rounding_b[AVC_QP_MAX];
+extern unsigned char gen9_avc_adaptive_inter_rounding_p_without_b[AVC_QP_MAX];
+extern const unsigned int gen9_avc_trellis_quantization_enable[PRESET_NUM];
+extern const unsigned int gen9_avc_trellis_quantization_rounding[PRESET_NUM];
+extern const unsigned int gen9_avc_enable_adaptive_trellis_quantization[PRESET_NUM];
+
+//new add
+extern const unsigned int gen9_avc_super_combine_dist[PRESET_NUM + 1];
+extern const unsigned char gen9_avc_p_me_method[PRESET_NUM + 1];
+extern const unsigned char gen9_avc_b_me_method[PRESET_NUM + 1];
+extern const unsigned int gen9_avc_enable_adaptive_search[PRESET_NUM];
+extern const unsigned int gen9_avc_max_len_sp[PRESET_NUM];
+extern const unsigned int gen9_avc_max_ftq_based_skip[PRESET_NUM];
+extern const unsigned int gen9_avc_mr_disable_qp_check[PRESET_NUM];
+extern const unsigned int gen9_avc_multi_pred[PRESET_NUM];
+extern const unsigned int gen9_avc_hme_b_combine_len[PRESET_NUM];
+extern const unsigned int gen9_avc_hme_combine_len[PRESET_NUM];
+
+extern const unsigned int gen9_avc_search_x[PRESET_NUM];
+extern const unsigned int gen9_avc_search_y[PRESET_NUM];
+extern const unsigned int gen9_avc_b_search_x[PRESET_NUM];
+extern const unsigned int gen9_avc_b_search_y[PRESET_NUM];
+extern const unsigned char gen9_avc_enable_adaptive_tx_decision[PRESET_NUM];
+extern const char gen9_avc_kernel_mode[PRESET_NUM];
+#endif //GEN9_AVC_const_DEF_H
--
2.7.4
Pengfei Qu
2017-01-13 09:24:08 UTC
Permalink
v1:add kernel pointer for different platform

Signed-off-by: Pengfei Qu <***@intel.com>
Reviewed-by: Sean V Kelley<***@posteo.de>
---
src/i965_avc_encoder_common.c | 319 ++++++++++++++++++++++++++++++++++++++++++
src/i965_avc_encoder_common.h | 305 ++++++++++++++++++++++++++++++++++++++++
src/i965_encoder_common.h | 30 ++--
3 files changed, 643 insertions(+), 11 deletions(-)
create mode 100755 src/i965_avc_encoder_common.c
create mode 100755 src/i965_avc_encoder_common.h

diff --git a/src/i965_avc_encoder_common.c b/src/i965_avc_encoder_common.c
new file mode 100755
index 0000000..3fc2b54
--- /dev/null
+++ b/src/i965_avc_encoder_common.c
@@ -0,0 +1,319 @@
+
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu <***@intel.com>
+ *
+ */
+
+#include "i965_avc_encoder_common.h"
+int
+i965_avc_get_max_mbps(int level_idc)
+{
+ int max_mbps = 11880;
+
+ switch (level_idc) {
+ case INTEL_AVC_LEVEL_2:
+ max_mbps = 11880;
+ break;
+
+ case INTEL_AVC_LEVEL_21:
+ max_mbps = 19800;
+ break;
+
+ case INTEL_AVC_LEVEL_22:
+ max_mbps = 20250;
+ break;
+
+ case INTEL_AVC_LEVEL_3:
+ max_mbps = 40500;
+ break;
+
+ case INTEL_AVC_LEVEL_31:
+ max_mbps = 108000;
+ break;
+
+ case INTEL_AVC_LEVEL_32:
+ max_mbps = 216000;
+ break;
+
+ case INTEL_AVC_LEVEL_4:
+ case INTEL_AVC_LEVEL_41:
+ max_mbps = 245760;
+ break;
+
+ case INTEL_AVC_LEVEL_42:
+ max_mbps = 522240;
+ break;
+
+ case INTEL_AVC_LEVEL_5:
+ max_mbps = 589824;
+ break;
+
+ case INTEL_AVC_LEVEL_51:
+ max_mbps = 983040;
+ break;
+
+ case INTEL_AVC_LEVEL_52:
+ max_mbps = 2073600;
+ break;
+
+ default:
+ break;
+ }
+
+ return max_mbps;
+};
+
+unsigned int
+i965_avc_get_profile_level_max_frame(struct avc_param * param,
+ int level_idc)
+{
+ double bits_per_mb, tmpf;
+ int max_mbps, num_mb_per_frame;
+ uint64_t max_byte_per_frame0, max_byte_per_frame1;
+ unsigned int ret;
+ unsigned int scale_factor = 4;
+
+
+ if (level_idc >= INTEL_AVC_LEVEL_31 && level_idc <= INTEL_AVC_LEVEL_4)
+ bits_per_mb = 96.0;
+ else
+ {
+ bits_per_mb = 192.0;
+ scale_factor = 2;
+
+ }
+
+ max_mbps = i965_avc_get_max_mbps(level_idc);
+ num_mb_per_frame = param->frame_width_in_mbs * param->frame_height_in_mbs;
+
+ tmpf = (double)num_mb_per_frame;
+
+ if (tmpf < max_mbps / 172.0)
+ tmpf = max_mbps / 172.0;
+
+ max_byte_per_frame0 = (uint64_t)(tmpf * bits_per_mb);
+ max_byte_per_frame1 = (uint64_t)(((double)max_mbps * 100) / param->frames_per_100s *bits_per_mb);
+
+ /* TODO: check VAEncMiscParameterTypeMaxFrameSize */
+ ret = (unsigned int)MIN(max_byte_per_frame0, max_byte_per_frame1);
+ ret = (unsigned int)MIN(ret, param->frame_width_in_pixel * param->frame_height_in_pixel *3 /(2*scale_factor));
+
+ return ret;
+}
+
+int
+i965_avc_calculate_initial_qp(struct avc_param * param)
+{
+ float x0 = 0, y0 = 1.19f, x1 = 1.75f, y1 = 1.75f;
+ unsigned frame_size;
+ int qp, delat_qp;
+
+ frame_size = (param->frame_width_in_pixel * param->frame_height_in_pixel * 3 / 2);
+ qp = (int)(1.0 / 1.2 * pow(10.0,
+ (log10(frame_size * 2.0 / 3.0 * ((float)param->frames_per_100s) /
+ ((float)(param->target_bit_rate * 1000) * 100)) - x0) *
+ (y1 - y0) / (x1 - x0) + y0) + 0.5);
+ qp += 2;
+ delat_qp = (int)(9 - (param->vbv_buffer_size_in_bit * ((float)param->frames_per_100s) /
+ ((float)(param->target_bit_rate * 1000) * 100)));
+ if (delat_qp > 0)
+ qp += delat_qp;
+
+ qp = CLAMP(1, 51, qp);
+ qp--;
+
+ if (qp < 0)
+ qp = 1;
+
+ return qp;
+}
+
+int
+i965_avc_get_max_v_mv_r(int level_idc)
+{
+ int max_v_mv_r = 128 * 4;
+
+ // See JVT Spec Annex A Table A-1 Level limits for below mapping
+ // MaxVmvR is in luma quarter pel unit
+ switch (level_idc)
+ {
+ case INTEL_AVC_LEVEL_1:
+ max_v_mv_r = 64 * 4;
+ break;
+ case INTEL_AVC_LEVEL_11:
+ case INTEL_AVC_LEVEL_12:
+ case INTEL_AVC_LEVEL_13:
+ case INTEL_AVC_LEVEL_2:
+ max_v_mv_r = 128 * 4;
+ break;
+ case INTEL_AVC_LEVEL_21:
+ case INTEL_AVC_LEVEL_22:
+ case INTEL_AVC_LEVEL_3:
+ max_v_mv_r = 256 * 4;
+ break;
+ case INTEL_AVC_LEVEL_31:
+ case INTEL_AVC_LEVEL_32:
+ case INTEL_AVC_LEVEL_4:
+ case INTEL_AVC_LEVEL_41:
+ case INTEL_AVC_LEVEL_42:
+ case INTEL_AVC_LEVEL_5:
+ case INTEL_AVC_LEVEL_51:
+ case INTEL_AVC_LEVEL_52:
+ max_v_mv_r = 512 * 4;
+ break;
+ default:
+ assert(0);
+ break;
+ }
+
+ return max_v_mv_r;
+}
+
+int
+i965_avc_get_max_mv_len(int level_idc)
+{
+ int max_mv_len = 127;
+
+ // See JVT Spec Annex A Table A-1 Level limits for below mapping
+ // MaxVmvR is in luma quarter pel unit
+ switch (level_idc)
+ {
+ case INTEL_AVC_LEVEL_1:
+ max_mv_len = 63;
+ break;
+ case INTEL_AVC_LEVEL_11:
+ case INTEL_AVC_LEVEL_12:
+ case INTEL_AVC_LEVEL_13:
+ case INTEL_AVC_LEVEL_2:
+ max_mv_len = 127;
+ break;
+ case INTEL_AVC_LEVEL_21:
+ case INTEL_AVC_LEVEL_22:
+ case INTEL_AVC_LEVEL_3:
+ max_mv_len = 255;
+ break;
+ case INTEL_AVC_LEVEL_31:
+ case INTEL_AVC_LEVEL_32:
+ case INTEL_AVC_LEVEL_4:
+ case INTEL_AVC_LEVEL_41:
+ case INTEL_AVC_LEVEL_42:
+ case INTEL_AVC_LEVEL_5:
+ case INTEL_AVC_LEVEL_51:
+ case INTEL_AVC_LEVEL_52:
+ max_mv_len = 511;
+ break;
+ default:
+ assert(0);
+ break;
+ }
+
+ return max_mv_len;
+}
+
+int
+i965_avc_get_max_mv_per_2mb(int level_idc)
+{
+ unsigned int max_mv_per_2mb = 32;
+
+ // See JVT Spec Annex A Table A-1 Level limits for below mapping
+ switch (level_idc)
+ {
+ case INTEL_AVC_LEVEL_3:
+ max_mv_per_2mb = 32;
+ break;
+ case INTEL_AVC_LEVEL_31:
+ case INTEL_AVC_LEVEL_32:
+ case INTEL_AVC_LEVEL_4:
+ case INTEL_AVC_LEVEL_41:
+ case INTEL_AVC_LEVEL_42:
+ case INTEL_AVC_LEVEL_5:
+ case INTEL_AVC_LEVEL_51:
+ case INTEL_AVC_LEVEL_52:
+ max_mv_per_2mb = 16;
+ break;
+ default:
+ break;
+ }
+
+ return max_mv_per_2mb;
+}
+
+unsigned short
+i965_avc_calc_skip_value(unsigned int enc_block_based_sip_en, unsigned int transform_8x8_flag, unsigned short skip_value)
+{
+ if(!enc_block_based_sip_en)
+ {
+ skip_value *= 3;
+ }
+ else if(!transform_8x8_flag)
+ {
+ skip_value /= 2;
+ }
+
+ return skip_value;
+}
+
+unsigned short i965_avc_get_maxnum_slices_num(int profile_idc,int level_idc,unsigned int frames_per_100s)
+{
+ unsigned int slice_num = 0;
+
+ if ((profile_idc == VAProfileH264Main) ||
+ (profile_idc == VAProfileH264High))
+ {
+ switch (level_idc)
+ {
+ case INTEL_AVC_LEVEL_3:
+ slice_num = (unsigned int)(40500.0 * 100 / 22.0 / frames_per_100s);
+ break;
+ case INTEL_AVC_LEVEL_31:
+ slice_num = (unsigned int)(108000.0 * 100 / 60.0 / frames_per_100s);
+ break;
+ case INTEL_AVC_LEVEL_32:
+ slice_num = (unsigned int)(216000.0 * 100 / 60.0 / frames_per_100s);
+ break;
+ case INTEL_AVC_LEVEL_4:
+ case INTEL_AVC_LEVEL_41:
+ slice_num = (unsigned int)(245760.0 * 100 / 24.0 / frames_per_100s);
+ break;
+ case INTEL_AVC_LEVEL_42:
+ slice_num = (unsigned int)(522240.0 * 100 / 24.0 / frames_per_100s);
+ break;
+ case INTEL_AVC_LEVEL_5:
+ slice_num = (unsigned int)(589824.0 * 100 / 24.0 / frames_per_100s);
+ break;
+ case INTEL_AVC_LEVEL_51:
+ slice_num = (unsigned int)(983040.0 * 100 / 24.0 / frames_per_100s);
+ break;
+ case INTEL_AVC_LEVEL_52:
+ slice_num = (unsigned int)(2073600.0 * 100 / 24.0 / frames_per_100s);
+ break;
+ default:
+ slice_num = 0;
+ }
+ }
+
+ return slice_num;
+}
diff --git a/src/i965_avc_encoder_common.h b/src/i965_avc_encoder_common.h
new file mode 100755
index 0000000..80ef1b1
--- /dev/null
+++ b/src/i965_avc_encoder_common.h
@@ -0,0 +1,305 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu <***@intel.com>
+ *
+ */
+
+#ifndef _I965_AVC_ENCODER_COMMON_H
+#define _I965_AVC_ENCODER_COMMON_H
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+#include <stdint.h>
+#include <assert.h>
+#include "intel_driver.h"
+
+// SubMbPartMask defined in CURBE for AVC ENC
+#define INTEL_AVC_DISABLE_4X4_SUB_MB_PARTITION 0x40
+#define INTEL_AVC_DISABLE_4X8_SUB_MB_PARTITION 0x20
+#define INTEL_AVC_DISABLE_8X4_SUB_MB_PARTITION 0x10
+#define INTEL_AVC_MAX_BWD_REF_NUM 2
+#define INTEL_AVC_MAX_FWD_REF_NUM 8
+
+#define MAX_MFC_AVC_REFERENCE_SURFACES 16
+#define NUM_MFC_AVC_DMV_BUFFERS 34
+#define MAX_HCP_REFERENCE_SURFACES 8
+#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
+
+#define INTEL_AVC_IMAGE_STATE_CMD_SIZE 128
+#define INTEL_AVC_MIN_QP 1
+#define INTEL_AVC_MAX_QP 51
+
+#define INTEL_AVC_WP_MODE_DEFAULT 0
+#define INTEL_AVC_WP_MODE_EXPLICIT 1
+#define INTEL_AVC_WP_MODE_IMPLICIT 2
+
+struct avc_param {
+
+ // original width/height
+ uint32_t frame_width_in_pixel;
+ uint32_t frame_height_in_pixel;
+ uint32_t frame_width_in_mbs;
+ uint32_t frame_height_in_mbs;
+ uint32_t frames_per_100s;
+ uint32_t vbv_buffer_size_in_bit;
+ uint32_t target_bit_rate;
+};
+
+typedef enum
+{
+ INTEL_AVC_BASE_PROFILE = 66,
+ INTEL_AVC_MAIN_PROFILE = 77,
+ INTEL_AVC_EXTENDED_PROFILE = 88,
+ INTEL_AVC_HIGH_PROFILE = 100,
+ INTEL_AVC_HIGH10_PROFILE = 110,
+ INTEL_AVC_HIGH422_PROFILE = 122,
+ INTEL_AVC_HIGH444_PROFILE = 244,
+ INTEL_AVC_CAVLC444_INTRA_PROFILE = 44,
+ INTEL_AVC_SCALABLE_BASE_PROFILE = 83,
+ INTEL_AVC_SCALABLE_HIGH_PROFILE = 86
+} INTEL_AVC_PROFILE_IDC;
+
+typedef enum
+{
+ INTEL_AVC_LEVEL_1 = 10,
+ INTEL_AVC_LEVEL_11 = 11,
+ INTEL_AVC_LEVEL_12 = 12,
+ INTEL_AVC_LEVEL_13 = 13,
+ INTEL_AVC_LEVEL_2 = 20,
+ INTEL_AVC_LEVEL_21 = 21,
+ INTEL_AVC_LEVEL_22 = 22,
+ INTEL_AVC_LEVEL_3 = 30,
+ INTEL_AVC_LEVEL_31 = 31,
+ INTEL_AVC_LEVEL_32 = 32,
+ INTEL_AVC_LEVEL_4 = 40,
+ INTEL_AVC_LEVEL_41 = 41,
+ INTEL_AVC_LEVEL_42 = 42,
+ INTEL_AVC_LEVEL_5 = 50,
+ INTEL_AVC_LEVEL_51 = 51,
+ INTEL_AVC_LEVEL_52 = 52
+} INTEL_AVC_LEVEL_IDC;
+
+struct gen9_mfx_avc_img_state
+{
+ union {
+ struct {
+ uint32_t dword_length:12;
+ uint32_t pad0:4;
+ uint32_t sub_opcode_b:5;
+ uint32_t sub_opcode_a:3;
+ uint32_t command_opcode:3;
+ uint32_t pipeline:2;
+ uint32_t command_type:3;
+ };
+
+ uint32_t value;
+ } dw0;
+
+ struct {
+ uint32_t frame_size_in_mbs:16;//minus1
+ uint32_t pad0:16;
+ } dw1;
+
+ struct {
+ uint32_t frame_width_in_mbs_minus1:8; //minus1
+ uint32_t pad0:8;
+ uint32_t frame_height_in_mbs_minus1:8; //minus1
+ uint32_t pad1:8;
+ } dw2;
+
+ struct {
+ uint32_t pad0:8;
+ uint32_t image_structure:2;
+ uint32_t weighted_bipred_idc:2;
+ uint32_t weighted_pred_flag:1;
+ uint32_t brc_domain_rate_control_enable:1;
+ uint32_t pad1:2;
+ uint32_t chroma_qp_offset:5;
+ uint32_t pad2:3;
+ uint32_t second_chroma_qp_offset:5;
+ uint32_t pad3:3;
+ } dw3;
+
+ struct {
+ uint32_t field_picture_flag:1;
+ uint32_t mbaff_mode_active:1;
+ uint32_t frame_mb_only_flag:1;
+ uint32_t transform_8x8_idct_mode_flag:1;
+ uint32_t direct_8x8_interface_flag:1;
+ uint32_t constrained_intra_prediction_flag:1;
+ uint32_t current_img_dispoable_flag:1;
+ uint32_t entropy_coding_flag:1;
+ uint32_t mb_mv_format_flag:1;
+ uint32_t pad0:1;
+ uint32_t chroma_format_idc:2;
+ uint32_t mv_unpacked_flag:1;
+ uint32_t insert_test_flag:1;
+ uint32_t load_slice_pointer_flag:1;
+ uint32_t macroblock_stat_enable:1;
+ uint32_t minimum_frame_size:16;
+ } dw4;
+
+ struct {
+ uint32_t intra_mb_max_bit_flag:1;
+ uint32_t inter_mb_max_bit_flag:1;
+ uint32_t frame_size_over_flag:1;
+ uint32_t frame_size_under_flag:1;
+ uint32_t pad0:3;
+ uint32_t intra_mb_ipcm_flag:1;
+ uint32_t pad1:1;
+ uint32_t mb_rate_ctrl_flag:1;
+ uint32_t min_frame_size_units:2;
+ uint32_t inter_mb_zero_cbp_flag:1; //?change
+ uint32_t pad2:3;
+ uint32_t non_first_pass_flag:1;
+ uint32_t pad3:10;
+ uint32_t aq_chroma_disable:1;
+ uint32_t aq_rounding:3;
+ uint32_t aq_enable:1;
+ } dw5;
+
+ struct {
+ uint32_t intra_mb_max_size:12;
+ uint32_t pad0:4;
+ uint32_t inter_mb_max_size:12;
+ uint32_t pad1:4;
+ } dw6;
+
+ struct {
+ uint32_t vsl_top_mb_trans8x8_flag:1;
+ uint32_t pad0:31;
+ } dw7;
+
+ struct {
+ uint32_t slice_delta_qp_max0:8;
+ uint32_t slice_delta_qp_max1:8;
+ uint32_t slice_delta_qp_max2:8;
+ uint32_t slice_delta_qp_max3:8;
+ } dw8;
+
+ struct {
+ uint32_t slice_delta_qp_min0:8;
+ uint32_t slice_delta_qp_min1:8;
+ uint32_t slice_delta_qp_min2:8;
+ uint32_t slice_delta_qp_min3:8;
+ } dw9;
+
+ struct {
+ uint32_t frame_bitrate_min:14;
+ uint32_t frame_bitrate_min_unit_mode:1;
+ uint32_t frame_bitrate_min_unit:1;
+ uint32_t frame_bitrate_max:14;
+ uint32_t frame_bitrate_max_unit_mode:1;
+ uint32_t frame_bitrate_max_unit:1;
+ } dw10;
+
+ struct {
+ uint32_t frame_bitrate_min_delta:15;
+ uint32_t pad0:1;
+ uint32_t frame_bitrate_max_delta:15;
+ uint32_t slice_tsats_streamout_enable:1;
+ } dw11;
+
+ struct {
+ uint32_t pad0:16;
+ uint32_t mpeg2_old_mode_select:1;
+ uint32_t vad_noa_mux_select:1;
+ uint32_t vad_error_logic:1;
+ uint32_t pad1:1;
+ uint32_t vmd_error_logic:1;
+ uint32_t pad2:11;
+ } dw12;
+
+ struct {
+ uint32_t pic_qp_init_minus26:8;
+ uint32_t pic_num_ref_idx_l0_active_minus1:6;
+ uint32_t pad0:2;
+ uint32_t pic_num_ref_idx_l1_active_minus1:6;
+ uint32_t pad1:2;
+ uint32_t num_ref_frames:5;
+ uint32_t is_curr_pic_has_mmco5:1;
+ uint32_t pad2:2;
+ } dw13;
+
+ struct {
+ uint32_t pic_order_present_flag:1;
+ uint32_t delta_pic_order_always_zero_flag:1;
+ uint32_t pic_order_cnt_type:2;
+ uint32_t pad0:4;
+ uint32_t slice_group_map_type:3;
+ uint32_t redundant_pic_cnt_present_flag:1;
+ uint32_t num_slice_groups_minus1:3;
+ uint32_t deblock_filter_ctrl_present_flag:1;
+ uint32_t log2_max_frame_num_minus4:8;
+ uint32_t log2_max_pic_order_cnt_lsb_minus4:8;
+ } dw14;
+
+ struct {
+ uint32_t slice_group_change_rate:16;
+ uint32_t curr_pic_frame_num:16;
+ } dw15;
+
+ struct {
+ uint32_t current_frame_view_id:10;
+ uint32_t pad0:2;
+ uint32_t max_view_idx_l0:4;
+ uint32_t pad1:2;
+ uint32_t max_view_idx_l1:4;
+ uint32_t pad2:9;
+ uint32_t inter_view_order_disable:1;
+ } dw16;
+
+ struct {
+ uint32_t fqp:3; // Must be zero for SKL
+ uint32_t fqp_offset:3; // Must be zero for SKL
+ uint32_t pad0:2;
+ uint32_t ext_brc_dm_stat_en:1; // Must be zero for SKL
+ uint32_t pad1:7;
+ uint32_t brc_dm_avg_mb_qp:6; // Must be zero for SKL
+ uint32_t pad2:10;
+ } dw17;
+
+ struct {
+ uint32_t brc_domain_target_frame_size;
+ } dw18;
+
+ struct {
+ uint32_t threshold_size_in_bytes;
+ } dw19;
+
+ struct {
+ uint32_t target_slice_size_in_bytes;
+ } dw20;
+};
+
+extern int i965_avc_get_max_mbps(int level_idc);
+extern int i965_avc_calculate_initial_qp(struct avc_param * param);
+extern unsigned int i965_avc_get_profile_level_max_frame(struct avc_param * param,int level_idc);
+extern int i965_avc_get_max_v_mv_r(int level_idc);
+extern int i965_avc_get_max_mv_len(int level_idc);
+extern int i965_avc_get_max_mv_per_2mb(int level_idc);
+extern unsigned short i965_avc_calc_skip_value(unsigned int enc_block_based_sip_en, unsigned int transform_8x8_flag, unsigned short skip_value);
+#endif // _I965_AVC_ENCODER_COMMON_H
\ No newline at end of file
diff --git a/src/i965_encoder_common.h b/src/i965_encoder_common.h
index bffbd8f..637439e 100755
--- a/src/i965_encoder_common.h
+++ b/src/i965_encoder_common.h
@@ -44,7 +44,6 @@ struct intel_encoder_context;
/*
this file define the common structure for encoder, such as H264/H265/VP8/VP9
*/
-
#define INTEL_BRC_NONE 0
#define INTEL_BRC_CBR 1
#define INTEL_BRC_VBR 2
@@ -245,25 +244,31 @@ enum INTEL_ENC_PRESET_MODE
*/
struct encoder_status
{
- uint32_t bs_byte_count;
+ uint32_t image_status_mask;
uint32_t image_status_ctrl;
+ uint32_t bs_byte_count_frame;
+ uint32_t bs_byte_count_frame_nh;
+ uint32_t mfc_qp_status_count;
uint32_t media_index;
};

struct encoder_status_buffer_internal
{
- uint32_t bs_byte_count_offset;
- uint32_t reserved[15];
-
+ dri_bo *bo;
+ uint32_t image_status_mask_offset;
uint32_t image_status_ctrl_offset;
+ uint32_t bs_byte_count_frame_offset;
+ uint32_t bs_byte_count_frame_nh_offset;
+ uint32_t mfc_qp_status_count_offset;
+ uint32_t media_index_offset;

- uint32_t bs_frame_reg_offset;
+ uint32_t bs_byte_count_frame_reg_offset;
+ uint32_t bs_byte_count_frame_nh_reg_offset;
+ uint32_t image_status_mask_reg_offset;
uint32_t image_status_ctrl_reg_offset;
- dri_bo *bo;
+ uint32_t mfc_qp_status_count_reg_offset;
uint32_t status_buffer_size;
uint32_t base_offset;
-
- uint32_t media_index_offset;
};

struct {
@@ -280,6 +285,9 @@ struct {

struct generic_encoder_context
{
+ // kernel pointer
+ void * enc_kernel_ptr;
+ uint32_t enc_kernel_size;
//scoreboard
uint32_t use_hw_scoreboard;
uint32_t use_hw_non_stalling_scoreboard;
@@ -470,13 +478,13 @@ struct generic_enc_codec_state {

//BRC related
uint32_t frame_rate;
+ uint32_t internal_rate_mode;

uint32_t brc_allocated:1;
uint32_t brc_inited:1;
uint32_t brc_need_reset:1;
uint32_t is_low_delay:1;
uint32_t brc_enabled:1;
- uint32_t internal_rate_mode:4;
uint32_t curr_pak_pass:4;
uint32_t num_pak_passes:4;
uint32_t is_first_pass:1;
@@ -485,7 +493,7 @@ struct generic_enc_codec_state {
uint32_t brc_roi_enable:1;
uint32_t brc_dirty_roi_enable:1;
uint32_t skip_frame_enbale:1;
- uint32_t brc_reserved:9;
+ uint32_t brc_reserved:13;

uint32_t target_bit_rate;
uint32_t max_bit_rate;
--
2.7.4
Pengfei Qu
2017-01-13 09:24:09 UTC
Permalink
Signed-off-by: Pengfei Qu <***@intel.com>
Reviewed-by: Sean V Kelley<***@posteo.de>
---
src/gen9_avc_encoder.h | 2339 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 2339 insertions(+)
create mode 100755 src/gen9_avc_encoder.h

diff --git a/src/gen9_avc_encoder.h b/src/gen9_avc_encoder.h
new file mode 100755
index 0000000..404ee56
--- /dev/null
+++ b/src/gen9_avc_encoder.h
@@ -0,0 +1,2339 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu <***@intel.com>
+ *
+ */
+
+#ifndef GEN9_AVC_ENCODER_H
+#define GEN9_AVC_ENCODER_H
+
+#include "i965_encoder_common.h"
+/*
+common structure and define
+gen9_avc_surface structure
+*/
+#define MAX_AVC_ENCODER_SURFACES 64
+#define MAX_AVC_PAK_PASS_NUM 4
+
+#define ENCODER_AVC_CONST_SURFACE_WIDTH 64
+#define ENCODER_AVC_CONST_SURFACE_HEIGHT 44
+#define WIDTH_IN_MACROBLOCKS(width) (ALIGN(width, 16) >> 4)
+
+#define AVC_BRC_HISTORY_BUFFER_SIZE 864
+#define AVC_BRC_CONSTANTSURFACE_SIZE 1664
+#define AVC_ADAPTIVE_TX_DECISION_THRESHOLD 128
+#define AVC_MB_TEXTURE_THRESHOLD 1024
+#define AVC_SFD_COST_TABLE_BUFFER_SIZ 52
+#define AVC_INVALID_ROUNDING_VALUE 255
+
+/* BRC define */
+#define CLIP(x, min, max) \
+ { \
+ (x) = (((x) > (max)) ? (max) : (((x) < (min)) ? (min) : (x))); \
+ }
+
+typedef struct _kernel_header_
+{
+ uint32_t reserved : 6;
+ uint32_t kernel_start_pointer : 26;
+} kernel_header;
+
+struct generic_search_path_delta
+{
+ uint8_t search_path_delta_x:4;
+ uint8_t search_path_delta_y:4;
+};
+
+struct scaling_param
+{
+ VASurfaceID curr_pic;
+ void *p_scaling_bti;
+ struct object_surface *input_surface;
+ struct object_surface *output_surface;
+ uint32_t input_frame_width;
+ uint32_t input_frame_height;
+ uint32_t output_frame_width;
+ uint32_t output_frame_height;
+ uint32_t vert_line_stride;
+ uint32_t vert_line_stride_offset;
+ bool scaling_out_use_16unorm_surf_fmt;
+ bool scaling_out_use_32unorm_surf_fmt;
+ bool mbv_proc_stat_enabled;
+ bool enable_mb_flatness_check;
+ bool enable_mb_variance_output;
+ bool enable_mb_pixel_average_output;
+ bool use_4x_scaling;
+ bool use_16x_scaling;
+ bool use_32x_scaling;
+ bool blk8x8_stat_enabled;
+ struct i965_gpe_resource *pres_mbv_proc_stat_buffer;
+ struct i965_gpe_resource *pres_flatness_check_surface;
+};
+
+struct avc_surface_param{
+ uint32_t frame_width;
+ uint32_t frame_height;
+};
+struct me_param{
+ uint32_t hme_type;
+};
+struct wp_param{
+ uint32_t ref_list_idx;
+};
+
+struct brc_param{
+ struct i965_gpe_context * gpe_context_brc_frame_update;
+ struct i965_gpe_context * gpe_context_mbenc;
+};
+
+struct mbenc_param{
+ uint32_t frame_width_in_mb;
+ uint32_t frame_height_in_mb;
+ uint32_t mbenc_i_frame_dist_in_use;
+ uint32_t mad_enable;
+ uint32_t roi_enabled;
+ uint32_t brc_enabled;
+ uint32_t slice_height;
+ uint32_t mb_const_data_buffer_in_use;
+ uint32_t mb_qp_buffer_in_use;
+ uint32_t mb_vproc_stats_enable;
+};
+
+struct gen9_surface_avc
+{
+ VADriverContextP ctx;
+ VASurfaceID scaled_4x_surface_id;
+ struct object_surface *scaled_4x_surface_obj;
+ VASurfaceID scaled_16x_surface_id;
+ struct object_surface *scaled_16x_surface_obj;
+ VASurfaceID scaled_32x_surface_id;
+ struct object_surface *scaled_32x_surface_obj;
+
+ //mv code and mv data
+ struct i965_gpe_resource res_mb_code_surface;
+ struct i965_gpe_resource res_mv_data_surface;
+
+ struct i965_gpe_resource res_ref_pic_select_surface;
+ //dmv top/bottom
+ dri_bo *dmv_top;
+ dri_bo *dmv_bottom;
+
+ int dmv_bottom_flag;
+ int frame_store_id;
+ int frame_idx;
+ int is_as_ref;
+ unsigned int qp_value;
+ int top_field_order_cnt;
+};
+
+typedef struct _gen9_avc_encoder_kernel_header {
+ int nKernelCount;
+
+ // Quality mode for Frame/Field
+ kernel_header mbenc_quality_I;
+ kernel_header mbenc_quality_P;
+ kernel_header mbenc_quality_B;
+ // Normal mode for Frame/Field
+ kernel_header mbenc_normal_I;
+ kernel_header mbenc_normal_P;
+ kernel_header mbenc_normal_B;
+ // Performance modes for Frame/Field
+ kernel_header mbenc_performance_I;
+ kernel_header mbenc_performance_P;
+ kernel_header mbenc_performance_B;
+ // WiDi modes for Frame/Field
+ kernel_header mbenc_widi_I;
+ kernel_header mbenc_widi_P;
+ kernel_header mbenc_widi_B;
+
+ // HME
+ kernel_header me_p;
+ kernel_header me_b;
+
+ // DownScaling
+ kernel_header ply_dscale_ply;
+ kernel_header ply_dscale_2f_ply_2f;
+
+ // BRC Init frame
+ kernel_header frame_brc_init;
+
+ // FrameBRC Update
+ kernel_header frame_brc_update;
+
+ // BRC Reset frame
+ kernel_header frame_brc_reset;
+
+ // BRC I Frame Distortion
+ kernel_header frame_brc_i_dist;
+
+ // BRCBlockCopy
+ kernel_header brc_block_copy;
+
+ // MbBRC Update
+ kernel_header mb_brc_update;
+
+ // 2x DownScaling
+ kernel_header ply_2xdscale_ply;
+ kernel_header ply_2xdscale_2f_ply_2f;
+
+ //Motion estimation kernel for the VDENC StreamIN
+ kernel_header me_vdenc;
+
+ //Weighted Prediction Kernel
+ kernel_header wp;
+
+ // Static frame detection Kernel
+ kernel_header static_detection;
+} gen9_avc_encoder_kernel_header;
+
+/*
+ The definition for Scaling
+*/
+typedef enum _gen9_avc_binding_table_offset_scaling
+{
+ GEN9_AVC_SCALING_FRAME_SRC_Y_INDEX = 0,
+ GEN9_AVC_SCALING_FRAME_DST_Y_INDEX = 1,
+ GEN9_AVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX = 4,
+ GEN9_AVC_SCALING_NUM_SURFACES = 6
+} gen9_avc_binding_table_offset_scaling;
+
+typedef struct _gen9_avc_scaling4x_curbe_data
+{
+ struct
+ {
+ uint32_t input_picture_width :16;
+ uint32_t input_picture_height :16;
+ } dw0;
+
+ struct {
+ uint32_t input_y_bti;
+ } dw1;
+
+ struct {
+ uint32_t output_y_bti;
+ } dw2;
+
+ struct {
+ uint32_t reserved;
+ } dw3;
+
+ struct {
+ uint32_t reserved;
+ } dw4;
+
+ struct {
+ uint32_t flatness_threshold;
+ } dw5;
+
+ struct
+ {
+ uint32_t enable_mb_flatness_check;
+ } dw6;
+
+ struct {
+ uint32_t enable_mb_variance_output;
+ } dw7;
+
+ struct {
+ uint32_t enable_mb_pixel_average_output;
+ } dw8;
+
+ struct {
+ uint32_t reserved;
+ } dw9;
+
+ struct {
+ uint32_t mbv_proc_stat_bti;
+ } dw10;
+
+ struct {
+ uint32_t reserved;
+ } dw11;
+} gen9_avc_scaling4x_curbe_data;
+
+typedef struct _gen9_avc_scaling2x_curbe_data
+{
+ struct
+ {
+ uint32_t input_picture_width :16;
+ uint32_t input_picture_height :16;
+ } dw0;
+
+ /* dw1-dw7 */
+ uint32_t reserved1[7];
+
+ struct {
+ uint32_t input_y_bti;
+ } dw8;
+
+ struct {
+ uint32_t output_y_bti;
+ } dw9;
+
+ uint32_t reserved2[2];
+} gen9_avc_scaling2x_curbe_data;
+
+#define GEN9_AVC_KERNEL_SCALING_2X_IDX 0
+#define GEN9_AVC_KERNEL_SCALING_4X_IDX 1
+#define NUM_GEN9_AVC_KERNEL_SCALING 2
+
+struct gen9_avc_scaling_context
+{
+ struct i965_gpe_context gpe_contexts[NUM_GEN9_AVC_KERNEL_SCALING];
+};
+
+/*
+me structure and define
+*/
+typedef enum _gen9_avc_binding_table_offset_me
+{
+ GEN9_AVC_ME_MV_DATA_SURFACE_INDEX = 0,
+ GEN9_AVC_16XME_MV_DATA_SURFACE_INDEX = 1,
+ GEN9_AVC_32XME_MV_DATA_SURFACE_INDEX = 1,
+ GEN9_AVC_ME_DISTORTION_SURFACE_INDEX = 2,
+ GEN9_AVC_ME_BRC_DISTORTION_INDEX = 3,
+ GEN9_AVC_ME_RESERVED0_INDEX = 4,
+ GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX = 5,
+ GEN9_AVC_ME_FWD_REF_IDX0_INDEX = 6,
+ GEN9_AVC_ME_RESERVED1_INDEX = 7,
+ GEN9_AVC_ME_FWD_REF_IDX1_INDEX = 8,
+ GEN9_AVC_ME_RESERVED2_INDEX = 9,
+ GEN9_AVC_ME_FWD_REF_IDX2_INDEX = 10,
+ GEN9_AVC_ME_RESERVED3_INDEX = 11,
+ GEN9_AVC_ME_FWD_REF_IDX3_INDEX = 12,
+ GEN9_AVC_ME_RESERVED4_INDEX = 13,
+ GEN9_AVC_ME_FWD_REF_IDX4_INDEX = 14,
+ GEN9_AVC_ME_RESERVED5_INDEX = 15,
+ GEN9_AVC_ME_FWD_REF_IDX5_INDEX = 16,
+ GEN9_AVC_ME_RESERVED6_INDEX = 17,
+ GEN9_AVC_ME_FWD_REF_IDX6_INDEX = 18,
+ GEN9_AVC_ME_RESERVED7_INDEX = 19,
+ GEN9_AVC_ME_FWD_REF_IDX7_INDEX = 20,
+ GEN9_AVC_ME_RESERVED8_INDEX = 21,
+ GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX = 22,
+ GEN9_AVC_ME_BWD_REF_IDX0_INDEX = 23,
+ GEN9_AVC_ME_RESERVED9_INDEX = 24,
+ GEN9_AVC_ME_BWD_REF_IDX1_INDEX = 25,
+ GEN9_AVC_ME_VDENC_STREAMIN_INDEX = 26,
+ GEN9_AVC_ME_NUM_SURFACES_INDEX = 27
+} gen9_avc_binding_table_offset_me;
+
+typedef struct _gen9_avc_me_curbe_data
+{
+ struct
+ {
+ uint32_t skip_mode_enable:1;
+ uint32_t adaptive_enable:1;
+ uint32_t bi_mix_dis:1;
+ uint32_t reserved0:2;
+ uint32_t early_ime_success_enable:1;
+ uint32_t reserved1:1;
+ uint32_t t8x8_flag_for_inter_enable:1;
+ uint32_t reserved2:16;
+ uint32_t early_ime_stop:8;
+ } dw0;
+
+ struct {
+ uint32_t max_num_mvs:6;
+ uint32_t reserved0:10;
+ uint32_t bi_weight:6;
+ uint32_t reserved1:6;
+ uint32_t uni_mix_disable:1;
+ uint32_t reserved2:3;
+ } dw1;
+
+ struct {
+ uint32_t max_len_sp:8;
+ uint32_t max_num_su:8;
+ uint32_t reserved0:16;
+ } dw2;
+
+ struct {
+ uint32_t src_size:2;
+ uint32_t reserved0:2;
+ uint32_t mb_type_remap:2;
+ uint32_t src_access:1;
+ uint32_t ref_access:1;
+ uint32_t search_ctrl:3;
+ uint32_t dual_search_path_option:1;
+ uint32_t sub_pel_mode:2;
+ uint32_t skip_type:1;
+ uint32_t disable_field_cache_allocation:1;
+ uint32_t inter_chroma_mode:1;
+ uint32_t ft_enable:1;
+ uint32_t bme_disable_fbr:1;
+ uint32_t block_based_skip_enable:1;
+ uint32_t inter_sad:2;
+ uint32_t intra_sad:2;
+ uint32_t sub_mb_part_mask:7;
+ uint32_t reserved1:1;
+ } dw3;
+
+ struct {
+ uint32_t reserved0:8;
+ uint32_t picture_height_minus1:8;
+ uint32_t picture_width:8;
+ uint32_t reserved1:8;
+ } dw4;
+
+ struct {
+ uint32_t reserved0:8;
+ uint32_t qp_prime_y:8;
+ uint32_t ref_width:8;
+ uint32_t ref_height:8;
+ } dw5;
+
+ struct {
+ uint32_t reserved0:3;
+ uint32_t write_distortions:1;
+ uint32_t use_mv_from_prev_step:1;
+ uint32_t reserved1:3;
+ uint32_t super_combine_dist:8;
+ uint32_t max_vmvr:16;
+ } dw6;
+
+ struct {
+ uint32_t reserved0:16;
+ uint32_t mv_cost_scale_factor:2;
+ uint32_t bilinear_enable:1;
+ uint32_t src_field_polarity:1;
+ uint32_t weightedsad_harr:1;
+ uint32_t ac_only_haar:1;
+ uint32_t ref_id_cost_mode:1;
+ uint32_t reserved1:1;
+ uint32_t skip_center_mask:8;
+ } dw7;
+
+ struct {
+ uint32_t mode_0_cost:8;
+ uint32_t mode_1_cost:8;
+ uint32_t mode_2_cost:8;
+ uint32_t mode_3_cost:8;
+ } dw8;
+
+ struct {
+ uint32_t mode_4_cost:8;
+ uint32_t mode_5_cost:8;
+ uint32_t mode_6_cost:8;
+ uint32_t mode_7_cost:8;
+ } dw9;
+
+ struct {
+ uint32_t mode_8_cost:8;
+ uint32_t mode_9_cost:8;
+ uint32_t ref_id_cost:8;
+ uint32_t chroma_intra_mode_cost:8;
+ } dw10;
+
+ struct {
+ uint32_t mv_0_cost:8;
+ uint32_t mv_1_cost:8;
+ uint32_t mv_2_cost:8;
+ uint32_t mv_3_cost:8;
+ } dw11;
+
+ struct {
+ uint32_t mv_4_cost:8;
+ uint32_t mv_5_cost:8;
+ uint32_t mv_6_cost:8;
+ uint32_t mv_7_cost:8;
+ } dw12;
+
+ struct {
+ uint32_t num_ref_idx_l0_minus1:8;
+ uint32_t num_ref_idx_l1_minus1:8;
+ uint32_t ref_streamin_cost:8;
+ uint32_t roi_enable:3;
+ uint32_t reserved0:5;
+ } dw13;
+
+ struct {
+ uint32_t l0_ref_pic_polarity_bits:8;
+ uint32_t l1_ref_pic_polarity_bits:2;
+ uint32_t reserved:22;
+ } dw14;
+
+ struct {
+ uint32_t prev_mv_read_pos_factor : 8;
+ uint32_t mv_shift_factor : 8;
+ uint32_t reserved:16;
+ } dw15;
+
+ struct {
+ struct generic_search_path_delta sp_delta_0;
+ struct generic_search_path_delta sp_delta_1;
+ struct generic_search_path_delta sp_delta_2;
+ struct generic_search_path_delta sp_delta_3;
+ } dw16;
+
+ struct {
+ struct generic_search_path_delta sp_delta_4;
+ struct generic_search_path_delta sp_delta_5;
+ struct generic_search_path_delta sp_delta_6;
+ struct generic_search_path_delta sp_delta_7;
+ } dw17;
+
+ struct {
+ struct generic_search_path_delta sp_delta_8;
+ struct generic_search_path_delta sp_delta_9;
+ struct generic_search_path_delta sp_delta_10;
+ struct generic_search_path_delta sp_delta_11;
+ } dw18;
+
+ struct {
+ struct generic_search_path_delta sp_delta_12;
+ struct generic_search_path_delta sp_delta_13;
+ struct generic_search_path_delta sp_delta_14;
+ struct generic_search_path_delta sp_delta_15;
+ } dw19;
+
+ struct {
+ struct generic_search_path_delta sp_delta_16;
+ struct generic_search_path_delta sp_delta_17;
+ struct generic_search_path_delta sp_delta_18;
+ struct generic_search_path_delta sp_delta_19;
+ } dw20;
+
+ struct {
+ struct generic_search_path_delta sp_delta_20;
+ struct generic_search_path_delta sp_delta_21;
+ struct generic_search_path_delta sp_delta_22;
+ struct generic_search_path_delta sp_delta_23;
+ } dw21;
+
+ struct {
+ struct generic_search_path_delta sp_delta_24;
+ struct generic_search_path_delta sp_delta_25;
+ struct generic_search_path_delta sp_delta_26;
+ struct generic_search_path_delta sp_delta_27;
+ } dw22;
+
+ struct {
+ struct generic_search_path_delta sp_delta_28;
+ struct generic_search_path_delta sp_delta_29;
+ struct generic_search_path_delta sp_delta_30;
+ struct generic_search_path_delta sp_delta_31;
+ } dw23;
+
+ struct {
+ struct generic_search_path_delta sp_delta_32;
+ struct generic_search_path_delta sp_delta_33;
+ struct generic_search_path_delta sp_delta_34;
+ struct generic_search_path_delta sp_delta_35;
+ } dw24;
+
+ struct {
+ struct generic_search_path_delta sp_delta_36;
+ struct generic_search_path_delta sp_delta_37;
+ struct generic_search_path_delta sp_delta_38;
+ struct generic_search_path_delta sp_delta_39;
+ } dw25;
+
+ struct {
+ struct generic_search_path_delta sp_delta_40;
+ struct generic_search_path_delta sp_delta_41;
+ struct generic_search_path_delta sp_delta_42;
+ struct generic_search_path_delta sp_delta_43;
+ } dw26;
+
+ struct {
+ struct generic_search_path_delta sp_delta_44;
+ struct generic_search_path_delta sp_delta_45;
+ struct generic_search_path_delta sp_delta_46;
+ struct generic_search_path_delta sp_delta_47;
+ } dw27;
+
+ struct {
+ struct generic_search_path_delta sp_delta_48;
+ struct generic_search_path_delta sp_delta_49;
+ struct generic_search_path_delta sp_delta_50;
+ struct generic_search_path_delta sp_delta_51;
+ } dw28;
+
+ struct {
+ struct generic_search_path_delta sp_delta_52;
+ struct generic_search_path_delta sp_delta_53;
+ struct generic_search_path_delta sp_delta_54;
+ struct generic_search_path_delta sp_delta_55;
+ } dw29;
+
+ struct {
+ uint32_t actual_mb_width:16;
+ uint32_t actual_mb_height:16;
+ } dw30;
+
+ struct {
+ uint32_t reserved0;
+ } dw31;
+
+ struct {
+ uint32_t _4x_memv_output_data_surf_index;
+ } dw32;
+
+ struct {
+ uint32_t _16x_32x_memv_input_data_surf_index;
+ } dw33;
+
+ struct {
+ uint32_t _4x_me_output_dist_surf_index;
+ } dw34;
+
+ struct {
+ uint32_t _4x_me_output_brc_dist_surf_index;
+ } dw35;
+
+ struct {
+ uint32_t vme_fwd_inter_pred_surf_index;
+ } dw36;
+
+ struct {
+ uint32_t vme_bdw_inter_pred_surf_index;
+ } dw37;
+
+ /* reserved */
+ struct {
+ uint32_t reserved;
+ } dw38;
+} gen9_avc_me_curbe_data;
+
+#define GEN9_AVC_KERNEL_ME_P_IDX 0
+#define GEN9_AVC_KERNEL_ME_B_IDX 1
+#define NUM_GEN9_AVC_KERNEL_ME 2
+
+struct gen9_avc_me_context
+{
+ struct i965_gpe_context gpe_contexts[NUM_GEN9_AVC_KERNEL_ME];
+};
+
+/*
+frame/mb brc structure and define
+*/
+typedef enum _gen9_avc_binding_table_offset_brc_init_reset
+{
+ GEN9_AVC_BRC_INIT_RESET_HISTORY_INDEX = 0,
+ GEN9_AVC_BRC_INIT_RESET_DISTORTION_INDEX,
+ GEN9_AVC_BRC_INIT_RESET_NUM_SURFACES
+} gen9_avc_binding_table_offset_brc_init_reset;
+
+typedef struct _gen9_avc_brc_init_reset_curbe_data
+{
+ struct
+ {
+ uint32_t profile_level_max_frame;
+ } dw0;
+
+ struct
+ {
+ uint32_t init_buf_full_in_bits;
+ } dw1;
+
+ struct
+ {
+ uint32_t buf_size_in_bits;
+ } dw2;
+
+ struct
+ {
+ uint32_t average_bit_rate;
+ } dw3;
+
+ struct
+ {
+ uint32_t max_bit_rate;
+ } dw4;
+
+ struct
+ {
+ uint32_t min_bit_rate;
+ } dw5;
+
+ struct
+ {
+ uint32_t frame_rate_m;
+ } dw6;
+
+ struct
+ {
+ uint32_t frame_rate_d;
+ } dw7;
+
+ struct
+ {
+ uint32_t brc_flag:16;
+ uint32_t gop_p:16;
+ } dw8;
+
+ struct
+ {
+ uint32_t gop_b:16;
+ uint32_t frame_width_in_bytes:16;
+ } dw9;
+
+ struct
+ {
+ uint32_t frame_height_in_bytes:16;
+ uint32_t avbr_accuracy:16;
+ } dw10;
+
+ struct
+ {
+ uint32_t avbr_convergence:16;
+ uint32_t min_qp:16;
+ } dw11;
+
+ struct
+ {
+ uint32_t max_qp:16;
+ uint32_t no_slices:16;
+ } dw12;
+
+ struct
+ {
+ uint32_t instant_rate_threshold_0_p:8;
+ uint32_t instant_rate_threshold_1_p:8;
+ uint32_t instant_rate_threshold_2_p:8;
+ uint32_t instant_rate_threshold_3_p:8;
+ } dw13;
+
+ struct
+ {
+ uint32_t instant_rate_threshold_0_b:8;
+ uint32_t instant_rate_threshold_1_b:8;
+ uint32_t instant_rate_threshold_2_b:8;
+ uint32_t instant_rate_threshold_3_b:8;
+ } dw14;
+
+ struct
+ {
+ uint32_t instant_rate_threshold_0_i:8;
+ uint32_t instant_rate_threshold_1_i:8;
+ uint32_t instant_rate_threshold_2_i:8;
+ uint32_t instant_rate_threshold_3_i:8;
+ } dw15;
+
+ struct
+ {
+ uint32_t deviation_threshold_0_pand_b:8;
+ uint32_t deviation_threshold_1_pand_b:8;
+ uint32_t deviation_threshold_2_pand_b:8;
+ uint32_t deviation_threshold_3_pand_b:8;
+ } dw16;
+
+ struct
+ {
+ uint32_t deviation_threshold_4_pand_b:8;
+ uint32_t deviation_threshold_5_pand_b:8;
+ uint32_t deviation_threshold_6_pand_b:8;
+ uint32_t deviation_threshold_7_pand_b:8;
+ } dw17;
+
+ struct
+ {
+ uint32_t deviation_threshold_0_vbr:8;
+ uint32_t deviation_threshold_1_vbr:8;
+ uint32_t deviation_threshold_2_vbr:8;
+ uint32_t deviation_threshold_3_vbr:8;
+ } dw18;
+
+ struct
+ {
+ uint32_t deviation_threshold_4_vbr:8;
+ uint32_t deviation_threshold_5_vbr:8;
+ uint32_t deviation_threshold_6_vbr:8;
+ uint32_t deviation_threshold_7_vbr:8;
+ } dw19;
+
+ struct
+ {
+ uint32_t deviation_threshold_0_i:8;
+ uint32_t deviation_threshold_1_i:8;
+ uint32_t deviation_threshold_2_i:8;
+ uint32_t deviation_threshold_3_i:8;
+ } dw20;
+
+ struct
+ {
+ uint32_t deviation_threshold_4_i:8;
+ uint32_t deviation_threshold_5_i:8;
+ uint32_t deviation_threshold_6_i:8;
+ uint32_t deviation_threshold_7_i:8;
+ } dw21;
+
+ struct
+ {
+ uint32_t initial_qp_i:8;
+ uint32_t initial_qp_p:8;
+ uint32_t initial_qp_b:8;
+ uint32_t sliding_window_size:8;
+ } dw22;
+
+ struct
+ {
+ uint32_t acqp;
+ } dw23;
+
+}gen9_avc_brc_init_reset_curbe_data;
+
+typedef enum _gen9_avc_binding_table_offset_frame_brc_update
+{
+ GEN9_AVC_FRAME_BRC_UPDATE_HISTORY_INDEX = 0,
+ GEN9_AVC_FRAME_BRC_UPDATE_PAK_STATISTICS_OUTPUT_INDEX = 1,
+ GEN9_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_READ_INDEX = 2,
+ GEN9_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_WRITE_INDEX = 3,
+ GEN9_AVC_FRAME_BRC_UPDATE_MBENC_CURBE_READ_INDEX = 4,
+ GEN9_AVC_FRAME_BRC_UPDATE_MBENC_CURBE_WRITE_INDEX = 5,
+ GEN9_AVC_FRAME_BRC_UPDATE_DISTORTION_INDEX = 6,
+ GEN9_AVC_FRAME_BRC_UPDATE_CONSTANT_DATA_INDEX = 7,
+ GEN9_AVC_FRAME_BRC_UPDATE_MB_STATUS_INDEX = 8,
+ GEN9_AVC_FRAME_BRC_UPDATE_NUM_SURFACES_INDEX = 9
+} gen9_avc_binding_table_offset_frame_brc_update;
+
+typedef struct _gen9_avc_frame_brc_update_curbe_data
+{
+ struct
+ {
+ uint32_t target_size;
+ } dw0;
+
+ struct
+ {
+ uint32_t frame_number;
+ } dw1;
+
+ struct
+ {
+ uint32_t size_of_pic_headers;
+ } dw2;
+
+ struct
+ {
+ uint32_t start_gadj_frame0:16;
+ uint32_t start_gadj_frame1:16;
+ } dw3;
+
+ struct
+ {
+ uint32_t start_gadj_frame2:16;
+ uint32_t start_gadj_frame3:16;
+ } dw4;
+
+ struct
+ {
+ uint32_t target_size_flag:8;
+ uint32_t brc_flag:8;
+ uint32_t max_num_paks:8;
+ uint32_t cur_frame_type:8;
+ } dw5;
+
+ struct
+ {
+ uint32_t num_skip_frames:8;
+ uint32_t minimum_qp:8;
+ uint32_t maximum_qp:8;
+ uint32_t enable_force_skip:1;
+ uint32_t enable_sliding_window:1;
+ uint32_t reserved:6;
+ } dw6;
+
+ struct
+ {
+ uint32_t size_skip_frames;
+ } dw7;
+
+ struct
+ {
+ uint32_t start_global_adjust_mult_0:8;
+ uint32_t start_global_adjust_mult_1:8;
+ uint32_t start_global_adjust_mult_2:8;
+ uint32_t start_global_adjust_mult_3:8;
+ } dw8;
+
+ struct
+ {
+ uint32_t start_global_adjust_mult_4:8;
+ uint32_t start_global_adjust_div_0:8;
+ uint32_t start_global_adjust_div_1:8;
+ uint32_t start_global_adjust_div_2:8;
+ } dw9;
+
+ struct
+ {
+ uint32_t start_global_adjust_div_3:8;
+ uint32_t start_global_adjust_div_4:8;
+ uint32_t qp_threshold_0:8;
+ uint32_t qp_threshold_1:8;
+ } dw10;
+
+ struct
+ {
+ uint32_t qp_threshold_2:8;
+ uint32_t qp_threshold_3:8;
+ uint32_t g_rate_ratio_threshold_0:8;
+ uint32_t g_rate_ratio_threshold_1:8;
+ } dw11;
+
+ struct
+ {
+ uint32_t g_rate_ratio_threshold_2:8;
+ uint32_t g_rate_ratio_threshold_3:8;
+ uint32_t g_rate_ratio_threshold_4:8;
+ uint32_t g_rate_ratio_threshold_5:8;
+ } dw12;
+
+ struct
+ {
+ uint32_t g_rate_ratio_threshold_qp_0:8;
+ uint32_t g_rate_ratio_threshold_qp_1:8;
+ uint32_t g_rate_ratio_threshold_qp_2:8;
+ uint32_t g_rate_ratio_threshold_qp_3:8;
+ } dw13;
+
+ struct
+ {
+ uint32_t g_rate_ratio_threshold_qp_4:8;
+ uint32_t g_rate_ratio_threshold_qp_5:8;
+ uint32_t g_rate_ratio_threshold_qp_6:8;
+ uint32_t qp_index_of_cur_pic:8;
+ } dw14;
+
+ struct
+ {
+ uint32_t reserved0:8;
+ uint32_t enable_roi:8;
+ uint32_t reserved1:8;
+ uint32_t reserved2:8;
+ } dw15;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw16;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw17;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw18;
+
+ struct
+ {
+ uint32_t user_max_frame;
+ } dw19;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw20;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw21;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw22;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw23;
+
+}gen9_avc_frame_brc_update_curbe_data;
+
+typedef enum _gen9_avc_binding_table_offset_mb_brc_update
+{
+ GEN9_AVC_MB_BRC_UPDATE_HISTORY_INDEX = 0,
+ GEN9_AVC_MB_BRC_UPDATE_MB_QP_INDEX = 1,
+ GEN9_AVC_MB_BRC_UPDATE_ROI_INDEX = 2,
+ GEN9_AVC_MB_BRC_UPDATE_MB_STATUS_INDEX = 3,
+ GEN9_AVC_MB_BRC_UPDATE_NUM_SURFACES_INDEX = 4
+} gen9_avc_binding_table_offset_mb_brc_update;
+
+typedef struct _gen9_avc_mb_brc_curbe_data
+{
+ struct
+ {
+ uint32_t cur_frame_type:8;
+ uint32_t enable_roi:8;
+ uint32_t roi_ratio:8;
+ uint32_t reserved0:8;
+ } dw0;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw1;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw2;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw3;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw4;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw5;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw6;
+
+
+}gen9_avc_mb_brc_curbe_data;
+
+#define GEN9_AVC_KERNEL_BRC_INIT 0
+#define GEN9_AVC_KERNEL_BRC_FRAME_UPDATE 1
+#define GEN9_AVC_KERNEL_BRC_RESET 2
+#define GEN9_AVC_KERNEL_BRC_I_FRAME_DIST 3
+#define GEN9_AVC_KERNEL_BRC_BLOCK_COPY 4
+#define GEN9_AVC_KERNEL_BRC_MB_UPDATE 5
+#define NUM_GEN9_AVC_KERNEL_BRC 6
+
+struct gen9_avc_brc_context
+{
+ struct i965_gpe_context gpe_contexts[NUM_GEN9_AVC_KERNEL_BRC];
+};
+
+/*
+wp structure and define
+*/
+typedef enum _gen9_avc_binding_table_offset_wp
+{
+ GEN9_AVC_WP_INPUT_REF_SURFACE_INDEX = 0,
+ GEN9_AVC_WP_OUTPUT_SCALED_SURFACE_INDEX = 1,
+ GEN9_AVC_WP_NUM_SURFACES_INDEX = 2
+} gen9_avc_binding_table_offset_wp;
+
+typedef struct _gen9_avc_wp_curbe_data
+{
+ struct
+ {
+ uint32_t default_weight:16;
+ uint32_t default_offset:16;
+ } dw0;
+
+ struct
+ {
+ uint32_t roi_0_x_left:16;
+ uint32_t roi_0_y_top:16;
+ } dw1;
+
+ struct
+ {
+ uint32_t roi_0_x_right:16;
+ uint32_t roi_0_y_bottom:16;
+ } dw2;
+
+ struct
+ {
+ uint32_t roi_0_weight:16;
+ uint32_t roi_0_offset:16;
+ } dw3;
+
+ struct
+ {
+ uint32_t roi_1_x_left:16;
+ uint32_t roi_1_y_top:16;
+ } dw4;
+
+ struct
+ {
+ uint32_t roi_1_x_right:16;
+ uint32_t roi_1_y_bottom:16;
+ } dw5;
+
+ struct
+ {
+ uint32_t roi_1_weight:16;
+ uint32_t roi_1_offset:16;
+ } dw6;
+
+ struct
+ {
+ uint32_t roi_2_x_left:16;
+ uint32_t roi_2_y_top:16;
+ } dw7;
+
+ struct
+ {
+ uint32_t roi_2_x_right:16;
+ uint32_t roi_2_y_bottom:16;
+ } dw8;
+
+ struct
+ {
+ uint32_t roi_2_weight:16;
+ uint32_t roi_2_offset:16;
+ } dw9;
+
+ struct
+ {
+ uint32_t roi_3_x_left:16;
+ uint32_t roi_3_y_top:16;
+ } dw10;
+
+ struct
+ {
+ uint32_t roi_3_x_right:16;
+ uint32_t roi_3_y_bottom:16;
+ } dw11;
+
+ struct
+ {
+ uint32_t roi_3_weight:16;
+ uint32_t roi_3_offset:16;
+ } dw12;
+
+ struct
+ {
+ uint32_t roi_4_x_left:16;
+ uint32_t roi_4_y_top:16;
+ } dw13;
+
+ struct
+ {
+ uint32_t roi_4_x_right:16;
+ uint32_t roi_4_y_bottom:16;
+ } dw14;
+
+ struct
+ {
+ uint32_t roi_4_weight:16;
+ uint32_t roi_4_offset:16;
+ } dw15;
+
+ struct
+ {
+ uint32_t roi_5_x_left:16;
+ uint32_t roi_5_y_top:16;
+ } dw16;
+
+ struct
+ {
+ uint32_t roi_5_x_right:16;
+ uint32_t roi_5_y_bottom:16;
+ } dw17;
+
+ struct
+ {
+ uint32_t roi_5_weight:16;
+ uint32_t roi_5_offset:16;
+ } dw18;
+
+ struct
+ {
+ uint32_t roi_6_x_left:16;
+ uint32_t roi_6_y_top:16;
+ } dw19;
+
+ struct
+ {
+ uint32_t roi_6_x_right:16;
+ uint32_t roi_6_y_bottom:16;
+ } dw20;
+
+ struct
+ {
+ uint32_t roi_6_weight:16;
+ uint32_t roi_6_offset:16;
+ } dw21;
+
+ struct
+ {
+ uint32_t roi_7_x_left:16;
+ uint32_t roi_7_y_top:16;
+ } dw22;
+
+ struct
+ {
+ uint32_t roi_7_x_right:16;
+ uint32_t roi_7_y_bottom:16;
+ } dw23;
+
+ struct
+ {
+ uint32_t roi_7_weight:16;
+ uint32_t roi_7_offset:16;
+ } dw24;
+
+ struct
+ {
+ uint32_t roi_8_x_left:16;
+ uint32_t roi_8_y_top:16;
+ } dw25;
+
+ struct
+ {
+ uint32_t roi_8_x_right:16;
+ uint32_t roi_8_y_bottom:16;
+ } dw26;
+
+ struct
+ {
+ uint32_t roi_8_weight:16;
+ uint32_t roi_8_offset:16;
+ } dw27;
+
+ struct
+ {
+ uint32_t roi_9_x_left:16;
+ uint32_t roi_9_y_top:16;
+ } dw28;
+
+ struct
+ {
+ uint32_t roi_9_x_right:16;
+ uint32_t roi_9_y_bottom:16;
+ } dw29;
+
+ struct
+ {
+ uint32_t roi_9_weight:16;
+ uint32_t roi_9_offset:16;
+ } dw30;
+
+ struct
+ {
+ uint32_t roi_10_x_left:16;
+ uint32_t roi_10_y_top:16;
+ } dw31;
+
+ struct
+ {
+ uint32_t roi_10_x_right:16;
+ uint32_t roi_10_y_bottom:16;
+ } dw32;
+
+ struct
+ {
+ uint32_t roi_10_weight:16;
+ uint32_t roi_10_offset:16;
+ } dw33;
+
+ struct
+ {
+ uint32_t roi_11_x_left:16;
+ uint32_t roi_11_y_top:16;
+ } dw34;
+
+ struct
+ {
+ uint32_t roi_11_x_right:16;
+ uint32_t roi_11_y_bottom:16;
+ } dw35;
+
+ struct
+ {
+ uint32_t roi_11_weight:16;
+ uint32_t roi_11_offset:16;
+ } dw36;
+
+ struct
+ {
+ uint32_t roi_12_x_left:16;
+ uint32_t roi_12_y_top:16;
+ } dw37;
+
+ struct
+ {
+ uint32_t roi_12_x_right:16;
+ uint32_t roi_12_y_bottom:16;
+ } dw38;
+
+ struct
+ {
+ uint32_t roi_12_weight:16;
+ uint32_t roi_12_offset:16;
+ } dw39;
+
+ struct
+ {
+ uint32_t roi_13_x_left:16;
+ uint32_t roi_13_y_top:16;
+ } dw40;
+
+ struct
+ {
+ uint32_t roi_13_x_right:16;
+ uint32_t roi_13_y_bottom:16;
+ } dw41;
+
+ struct
+ {
+ uint32_t roi_13_weight:16;
+ uint32_t roi_13_offset:16;
+ } dw42;
+
+ struct
+ {
+ uint32_t roi_14_x_left:16;
+ uint32_t roi_14_y_top:16;
+ } dw43;
+
+ struct
+ {
+ uint32_t roi_14_x_right:16;
+ uint32_t roi_14_y_bottom:16;
+ } dw44;
+
+ struct
+ {
+ uint32_t roi_14_weight:16;
+ uint32_t roi_14_offset:16;
+ } dw45;
+
+ struct
+ {
+ uint32_t roi_15_x_left:16;
+ uint32_t roi_15_y_top:16;
+ } dw46;
+
+ struct
+ {
+ uint32_t roi_15_x_right:16;
+ uint32_t roi_15_y_bottom:16;
+ } dw47;
+
+ struct
+ {
+ uint32_t roi_15_weight:16;
+ uint32_t roi_15_offset:16;
+ } dw48;
+
+ struct
+ {
+ uint32_t input_surface;
+ } dw49;
+
+ struct
+ {
+ uint32_t output_surface;
+ } dw50;
+
+
+
+}gen9_avc_wp_curbe_data;
+
+struct gen9_avc_wp_context
+{
+ struct i965_gpe_context gpe_contexts;
+};
+
+/*
+mbenc structure and define
+*/
+typedef enum _gen9_avc_binding_table_offset_mbenc
+{
+ GEN9_AVC_MBENC_MFC_AVC_PAK_OBJ_INDEX = 0,
+ GEN9_AVC_MBENC_IND_MV_DATA_INDEX = 1,
+ GEN9_AVC_MBENC_BRC_DISTORTION_INDEX = 2, // FOR BRC DISTORTION FOR I
+ GEN9_AVC_MBENC_CURR_Y_INDEX = 3,
+ GEN9_AVC_MBENC_CURR_UV_INDEX = 4,
+ GEN9_AVC_MBENC_MB_SPECIFIC_DATA_INDEX = 5,
+ GEN9_AVC_MBENC_AUX_VME_OUT_INDEX = 6,
+ GEN9_AVC_MBENC_REFPICSELECT_L0_INDEX = 7,
+ GEN9_AVC_MBENC_MV_DATA_FROM_ME_INDEX = 8,
+ GEN9_AVC_MBENC_4XME_DISTORTION_INDEX = 9,
+ GEN9_AVC_MBENC_SLICEMAP_DATA_INDEX = 10,
+ GEN9_AVC_MBENC_FWD_MB_DATA_INDEX = 11,
+ GEN9_AVC_MBENC_FWD_MV_DATA_INDEX = 12,
+ GEN9_AVC_MBENC_MBQP_INDEX = 13,
+ GEN9_AVC_MBENC_MBBRC_CONST_DATA_INDEX = 14,
+ GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_INDEX = 15,
+ GEN9_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX0_INDEX = 16,
+ GEN9_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX0_0_INDEX = 17,
+ GEN9_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX1_INDEX = 18,
+ GEN9_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX1_0_INDEX = 19,
+ GEN9_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX2_INDEX = 20,
+ GEN9_AVC_MBENC_RESERVED0_INDEX = 21,
+ GEN9_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX3_INDEX = 22,
+ GEN9_AVC_MBENC_RESERVED1_INDEX = 23,
+ GEN9_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX4_INDEX = 24,
+ GEN9_AVC_MBENC_RESERVED2_INDEX = 25,
+ GEN9_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX5_INDEX = 26,
+ GEN9_AVC_MBENC_RESERVED3_INDEX = 27,
+ GEN9_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX6_INDEX = 28,
+ GEN9_AVC_MBENC_RESERVED4_INDEX = 29,
+ GEN9_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX7_INDEX = 30,
+ GEN9_AVC_MBENC_RESERVED5_INDEX = 31,
+ GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_INDEX = 32,
+ GEN9_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX0_1_INDEX = 33,
+ GEN9_AVC_MBENC_RESERVED6_INDEX = 34,
+ GEN9_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX1_1_INDEX = 35,
+ GEN9_AVC_MBENC_RESERVED7_INDEX = 36,
+ GEN9_AVC_MBENC_MB_STATS_INDEX = 37,
+ GEN9_AVC_MBENC_MAD_DATA_INDEX = 38,
+ GEN9_AVC_MBENC_FORCE_NONSKIP_MB_MAP_INDEX = 39,
+ GEN9_AVC_MBENC_WIDI_WA_INDEX = 40,
+ GEN9_AVC_MBENC_BRC_CURBE_DATA_INDEX = 41,
+ GEN9_AVC_MBENC_SFD_COST_TABLE_INDEX = 42,
+ GEN9_AVC_MBENC_MV_PREDICTOR_INDEX = 43,
+ GEN9_AVC_MBENC_NUM_SURFACES_INDEX = 44
+} gen9_avc_binding_table_offset_mbenc;
+
+typedef struct _gen9_avc_mbenc_curbe_data
+{
+ struct
+ {
+ uint32_t skip_mode_enable:1;
+ uint32_t adaptive_enable:1;
+ uint32_t bi_mix_dis:1;
+ uint32_t reserved0:2;
+ uint32_t early_ime_success_enable:1;
+ uint32_t reserved1:1;
+ uint32_t t8x8_flag_for_inter_enable:1;
+ uint32_t reserved2:16;
+ uint32_t early_ime_stop:8;
+ } dw0;
+
+ struct {
+ uint32_t max_num_mvs:6;
+ uint32_t reserved0:10;
+ uint32_t bi_weight:6;
+ uint32_t reserved1:6;
+ uint32_t uni_mix_disable:1;
+ uint32_t reserved2:3;
+ } dw1;
+
+ struct {
+ uint32_t max_len_sp:8;
+ uint32_t max_num_su:8;
+ uint32_t pitch_width:16;
+ } dw2;
+
+ struct {
+ uint32_t src_size:2;
+ uint32_t reserved0:2;
+ uint32_t mb_type_remap:2;
+ uint32_t src_access:1;
+ uint32_t ref_access:1;
+ uint32_t search_ctrl:3;
+ uint32_t dual_search_path_option:1;
+ uint32_t sub_pel_mode:2;
+ uint32_t skip_type:1;
+ uint32_t disable_field_cache_allocation:1;
+ uint32_t inter_chroma_mode:1;
+ uint32_t ftq_enable:1;
+ uint32_t bme_disable_fbr:1;
+ uint32_t block_based_skip_enable:1;
+ uint32_t inter_sad:2;
+ uint32_t intra_sad:2;
+ uint32_t sub_mb_part_mask:7;
+ uint32_t reserved1:1;
+ } dw3;
+
+ struct {
+ uint32_t picture_height_minus1:16;
+ uint32_t mv_restriction_in_slice_enable:1;
+ uint32_t delta_mv_enable:1;
+ uint32_t true_distortion_enable:1;
+ uint32_t enable_waveforont_optimization:1;
+ uint32_t enable_fbr_bypass:1;
+ uint32_t enable_intra_cost_scaling_for_static_frame:1;
+ uint32_t reserved0:1;
+ uint32_t enable_widi_wa_surf:1;
+ uint32_t enable_widi_dirty_rect:1;
+ uint32_t enable_cur_fld_idr:1;
+ uint32_t contrained_intra_pred_flag:1;
+ uint32_t field_parity_flag:1;
+ uint32_t hme_enable:1;
+ uint32_t picture_type:2;
+ uint32_t use_actual_ref_qp_value:1;
+ } dw4;
+
+ struct {
+ uint32_t slice_mb_height:16;
+ uint32_t ref_width:8;
+ uint32_t ref_height:8;
+ } dw5;
+
+ struct {
+ uint32_t batch_buffer_end;
+ } dw6;
+
+ struct {
+ uint32_t intra_part_mask:5;
+ uint32_t non_skip_zmv_added:1;
+ uint32_t non_skip_mode_added:1;
+ uint32_t luma_intra_src_corner_swap:1;
+ uint32_t reserved0:8;
+ uint32_t mv_cost_scale_factor:2;
+ uint32_t bilinear_enable:1;
+ uint32_t src_field_polarity:1;
+ uint32_t weightedsad_harr:1;
+ uint32_t ac_only_haar:1;
+ uint32_t ref_id_cost_mode:1;
+ uint32_t reserved1:1;
+ uint32_t skip_center_mask:8;
+ } dw7;
+
+ struct {
+ uint32_t mode_0_cost:8;
+ uint32_t mode_1_cost:8;
+ uint32_t mode_2_cost:8;
+ uint32_t mode_3_cost:8;
+ } dw8;
+
+ struct {
+ uint32_t mode_4_cost:8;
+ uint32_t mode_5_cost:8;
+ uint32_t mode_6_cost:8;
+ uint32_t mode_7_cost:8;
+ } dw9;
+
+ struct {
+ uint32_t mode_8_cost:8;
+ uint32_t mode_9_cost:8;
+ uint32_t ref_id_cost:8;
+ uint32_t chroma_intra_mode_cost:8;
+ } dw10;
+
+ union{
+ struct {
+ uint32_t mv_0_cost:8;
+ uint32_t mv_1_cost:8;
+ uint32_t mv_2_cost:8;
+ uint32_t mv_3_cost:8;
+ };
+ uint32_t value;
+ }dw11;
+
+ struct {
+ uint32_t mv_4_cost:8;
+ uint32_t mv_5_cost:8;
+ uint32_t mv_6_cost:8;
+ uint32_t mv_7_cost:8;
+ } dw12;
+
+ struct {
+ uint32_t qp_prime_y:8;
+ uint32_t qp_prime_cb:8;
+ uint32_t qp_prime_cr:8;
+ uint32_t target_size_in_word:8;
+ } dw13;
+
+ struct {
+ uint32_t sic_fwd_transcoeff_threshold_0:16;
+ uint32_t sic_fwd_transcoeff_threshold_1:8;
+ uint32_t sic_fwd_transcoeff_threshold_2:8;
+ } dw14;
+
+ struct {
+ uint32_t sic_fwd_transcoeff_threshold_3:8;
+ uint32_t sic_fwd_transcoeff_threshold_4:8;
+ uint32_t sic_fwd_transcoeff_threshold_5:8;
+ uint32_t sic_fwd_transcoeff_threshold_6:8;
+ } dw15;
+
+ struct {
+ struct generic_search_path_delta sp_delta_0;
+ struct generic_search_path_delta sp_delta_1;
+ struct generic_search_path_delta sp_delta_2;
+ struct generic_search_path_delta sp_delta_3;
+ } dw16;
+
+ struct {
+ struct generic_search_path_delta sp_delta_4;
+ struct generic_search_path_delta sp_delta_5;
+ struct generic_search_path_delta sp_delta_6;
+ struct generic_search_path_delta sp_delta_7;
+ } dw17;
+
+ struct {
+ struct generic_search_path_delta sp_delta_8;
+ struct generic_search_path_delta sp_delta_9;
+ struct generic_search_path_delta sp_delta_10;
+ struct generic_search_path_delta sp_delta_11;
+ } dw18;
+
+ struct {
+ struct generic_search_path_delta sp_delta_12;
+ struct generic_search_path_delta sp_delta_13;
+ struct generic_search_path_delta sp_delta_14;
+ struct generic_search_path_delta sp_delta_15;
+ } dw19;
+
+ struct {
+ struct generic_search_path_delta sp_delta_16;
+ struct generic_search_path_delta sp_delta_17;
+ struct generic_search_path_delta sp_delta_18;
+ struct generic_search_path_delta sp_delta_19;
+ } dw20;
+
+ struct {
+ struct generic_search_path_delta sp_delta_20;
+ struct generic_search_path_delta sp_delta_21;
+ struct generic_search_path_delta sp_delta_22;
+ struct generic_search_path_delta sp_delta_23;
+ } dw21;
+
+ struct {
+ struct generic_search_path_delta sp_delta_24;
+ struct generic_search_path_delta sp_delta_25;
+ struct generic_search_path_delta sp_delta_26;
+ struct generic_search_path_delta sp_delta_27;
+ } dw22;
+
+ struct {
+ struct generic_search_path_delta sp_delta_28;
+ struct generic_search_path_delta sp_delta_29;
+ struct generic_search_path_delta sp_delta_30;
+ struct generic_search_path_delta sp_delta_31;
+ } dw23;
+
+ struct {
+ struct generic_search_path_delta sp_delta_32;
+ struct generic_search_path_delta sp_delta_33;
+ struct generic_search_path_delta sp_delta_34;
+ struct generic_search_path_delta sp_delta_35;
+ } dw24;
+
+ struct {
+ struct generic_search_path_delta sp_delta_36;
+ struct generic_search_path_delta sp_delta_37;
+ struct generic_search_path_delta sp_delta_38;
+ struct generic_search_path_delta sp_delta_39;
+ } dw25;
+
+ struct {
+ struct generic_search_path_delta sp_delta_40;
+ struct generic_search_path_delta sp_delta_41;
+ struct generic_search_path_delta sp_delta_42;
+ struct generic_search_path_delta sp_delta_43;
+ } dw26;
+
+ struct {
+ struct generic_search_path_delta sp_delta_44;
+ struct generic_search_path_delta sp_delta_45;
+ struct generic_search_path_delta sp_delta_46;
+ struct generic_search_path_delta sp_delta_47;
+ } dw27;
+
+ struct {
+ struct generic_search_path_delta sp_delta_48;
+ struct generic_search_path_delta sp_delta_49;
+ struct generic_search_path_delta sp_delta_50;
+ struct generic_search_path_delta sp_delta_51;
+ } dw28;
+
+ struct {
+ struct generic_search_path_delta sp_delta_52;
+ struct generic_search_path_delta sp_delta_53;
+ struct generic_search_path_delta sp_delta_54;
+ struct generic_search_path_delta sp_delta_55;
+ } dw29;
+
+ struct {
+ uint32_t intra_4x4_mode_mask:9;
+ uint32_t reserved0:7;
+ uint32_t intra_8x8_mode_mask:9;
+ uint32_t reserved1:7;
+ } dw30;
+
+ struct {
+ uint32_t intra_16x16_mode_mask:4;
+ uint32_t intra_chroma_mode_mask:4;
+ uint32_t intra_compute_type:2;
+ uint32_t reserved0:22;
+ } dw31;
+
+ struct {
+ uint32_t skip_val:16;
+ uint32_t mult_pred_l0_disable:8;
+ uint32_t mult_pred_l1_disable:8;
+ } dw32;
+
+ struct {
+ uint32_t intra_16x16_nondc_penalty:8;
+ uint32_t intra_8x8_nondc_penalty:8;
+ uint32_t intra_4x4_nondc_penalty:8;
+ uint32_t reserved0:8;
+ } dw33;
+
+ struct {
+ uint32_t list0_ref_id0_field_parity:1;
+ uint32_t list0_ref_id1_field_parity:1;
+ uint32_t list0_ref_id2_field_parity:1;
+ uint32_t list0_ref_id3_field_parity:1;
+ uint32_t list0_ref_id4_field_parity:1;
+ uint32_t list0_ref_id5_field_parity:1;
+ uint32_t list0_ref_id6_field_parity:1;
+ uint32_t list0_ref_id7_field_parity:1;
+ uint32_t list1_ref_id0_frm_field_parity:1;
+ uint32_t list1_ref_id1_frm_field_parity:1;
+ uint32_t widi_intra_refresh_en:2;
+ uint32_t arbitray_num_mbs_per_slice:1;
+ uint32_t enable_adaptive_tx_decision:1;
+ uint32_t force_non_skip_check:1;
+ uint32_t disable_enc_skip_check:1;
+ uint32_t enable_direct_bias_adjustment:1;
+ uint32_t b_force_to_skip:1;
+ uint32_t enable_global_motion_bias_adjustment:1;
+ uint32_t enable_adaptive_search_window_size:1;
+ uint32_t enable_per_mb_static_check:1;
+ uint32_t reserved0:3;
+ uint32_t list1_ref_id0_field_parity:1;
+ uint32_t list1_ref_id1_field_parity:1;
+ uint32_t mad_enable_falg:1;
+ uint32_t roi_enable_flag:1;
+ uint32_t enable_mb_flatness_check_optimization:1;
+ uint32_t b_direct_mode:1;
+ uint32_t mb_brc_enable:1;
+ uint32_t b_original_bff:1;
+ } dw34;
+
+ struct {
+ uint32_t panic_mode_mb_threshold:16;
+ uint32_t small_mb_size_in_word:8;
+ uint32_t large_mb_size_in_word:8;
+ } dw35;
+
+ struct {
+ uint32_t num_ref_idx_l0_minus_one:8;
+ uint32_t hme_combined_extra_sus:8;
+ uint32_t num_ref_idx_l1_minus_one:8;
+ uint32_t reserved0:4;
+ uint32_t is_fwd_frame_short_term_ref:1;
+ uint32_t check_all_fractional_enable:1;
+ uint32_t hme_combine_overlap:2;
+ } dw36;
+
+ struct {
+ uint32_t skip_mode_enable:1;
+ uint32_t adaptive_enable:1;
+ uint32_t bi_mix_dis:1;
+ uint32_t reserved0:2;
+ uint32_t early_ime_success_enable:1;
+ uint32_t reserved1:1;
+ uint32_t t8x8_flag_for_inter_enable:1;
+ uint32_t reserved2:16;
+ uint32_t early_ime_stop:8;
+ } dw37;
+
+ /* reserved */
+ struct {
+ uint32_t max_len_sp:8;
+ uint32_t max_num_su:8;
+ uint32_t ref_threshold:16;
+ } dw38;
+
+ struct {
+ uint32_t reserved0:8;
+ uint32_t hme_ref_windows_comb_threshold:8;
+ uint32_t ref_width:8;
+ uint32_t ref_height:8;
+ } dw39;
+
+ struct {
+ uint32_t dist_scale_factor_ref_id0_list0:16;
+ uint32_t dist_scale_factor_ref_id1_list0:16;
+ } dw40;
+
+ struct {
+ uint32_t dist_scale_factor_ref_id2_list0:16;
+ uint32_t dist_scale_factor_ref_id3_list0:16;
+ } dw41;
+
+ struct {
+ uint32_t dist_scale_factor_ref_id4_list0:16;
+ uint32_t dist_scale_factor_ref_id5_list0:16;
+ } dw42;
+
+ struct {
+ uint32_t dist_scale_factor_ref_id6_list0:16;
+ uint32_t dist_scale_factor_ref_id7_list0:16;
+ } dw43;
+
+ struct {
+ uint32_t actual_qp_value_for_ref_id0_list0:8;
+ uint32_t actual_qp_value_for_ref_id1_list0:8;
+ uint32_t actual_qp_value_for_ref_id2_list0:8;
+ uint32_t actual_qp_value_for_ref_id3_list0:8;
+ } dw44;
+
+ struct {
+ uint32_t actual_qp_value_for_ref_id4_list0:8;
+ uint32_t actual_qp_value_for_ref_id5_list0:8;
+ uint32_t actual_qp_value_for_ref_id6_list0:8;
+ uint32_t actual_qp_value_for_ref_id7_list0:8;
+ } dw45;
+
+ struct {
+ uint32_t actual_qp_value_for_ref_id0_list1:8;
+ uint32_t actual_qp_value_for_ref_id1_list1:8;
+ uint32_t ref_cost:16;
+ } dw46;
+
+ struct {
+ uint32_t mb_qp_read_factor:8;
+ uint32_t intra_cost_sf:8;
+ uint32_t max_vmv_r:16;
+ } dw47;
+
+ struct {
+ uint32_t widi_intra_refresh_mb_num:16;
+ uint32_t widi_intra_refresh_unit_in_mb_minus1:8;
+ uint32_t widi_intra_refresh_qp_delta:8;
+ } dw48;
+
+ struct {
+ uint32_t roi_1_x_left:16;
+ uint32_t roi_1_y_top:16;
+ } dw49;
+
+ struct {
+ uint32_t roi_1_x_right:16;
+ uint32_t roi_1_y_bottom:16;
+ } dw50;
+
+ struct {
+ uint32_t roi_2_x_left:16;
+ uint32_t roi_2_y_top:16;
+ } dw51;
+
+ struct {
+ uint32_t roi_2_x_right:16;
+ uint32_t roi_2_y_bottom:16;
+ } dw52;
+
+ struct {
+ uint32_t roi_3_x_left:16;
+ uint32_t roi_3_y_top:16;
+ } dw53;
+
+ struct {
+ uint32_t roi_3_x_right:16;
+ uint32_t roi_3_y_bottom:16;
+ } dw54;
+
+ struct {
+ uint32_t roi_4_x_left:16;
+ uint32_t roi_4_y_top:16;
+ } dw55;
+
+ struct {
+ uint32_t roi_4_x_right:16;
+ uint32_t roi_4_y_bottom:16;
+ } dw56;
+
+ struct {
+ uint32_t roi_1_dqp_prime_y:8;
+ uint32_t roi_2_dqp_prime_y:8;
+ uint32_t roi_3_dqp_prime_y:8;
+ uint32_t roi_4_dqp_prime_y:8;
+ } dw57;
+
+ struct {
+ uint32_t mb_texture_threshold:16;
+ uint32_t tx_decision_threshold:16;
+ } dw58;
+
+ struct {
+ uint32_t hme_mv_cost_scaling_factor:8;
+ uint32_t reserved0:24;
+ } dw59;
+
+ struct {
+ uint32_t reserved;
+ } dw60;
+
+ struct {
+ uint32_t reserved;
+ } dw61;
+
+ struct {
+ uint32_t reserved;
+ } dw62;
+
+ struct {
+ uint32_t reserved;
+ } dw63;
+
+ struct {
+ uint32_t mb_data_surf_index;
+ } dw64;
+
+ struct {
+ uint32_t mv_data_surf_index;
+ } dw65;
+
+ struct {
+ uint32_t i_dist_surf_index;
+ } dw66;
+
+ struct {
+ uint32_t src_y_surf_index;
+ } dw67;
+
+ struct {
+ uint32_t mb_specific_data_surf_index;
+ } dw68;
+
+ struct {
+ uint32_t aux_vme_out_surf_index;
+ } dw69;
+
+ struct {
+ uint32_t curr_ref_pic_sel_surf_index;
+ } dw70;
+
+ struct {
+ uint32_t hme_mv_pred_fwd_bwd_surf_index;
+ } dw71;
+
+ struct {
+ uint32_t hme_dist_surf_index;
+ } dw72;
+
+ struct {
+ uint32_t slice_map_surf_index;
+ } dw73;
+
+ struct {
+ uint32_t fwd_frm_mb_data_surf_index;
+ } dw74;
+
+ struct {
+ uint32_t fwd_frm_mv_surf_index;
+ } dw75;
+
+ struct {
+ uint32_t mb_qp_buffer;
+ } dw76;
+
+ struct {
+ uint32_t mb_brc_lut;
+ } dw77;
+
+ struct {
+ uint32_t vme_inter_prediction_surf_index;
+ } dw78;
+
+ struct {
+ uint32_t vme_inter_prediction_mr_surf_index;
+ } dw79;
+
+ struct {
+ uint32_t mb_stats_surf_index;
+ } dw80;
+
+ struct {
+ uint32_t mad_surf_index;
+ } dw81;
+
+ struct {
+ uint32_t force_non_skip_mb_map_surface;
+ } dw82;
+
+ struct {
+ uint32_t widi_wa_surf_index;
+ } dw83;
+
+ struct {
+ uint32_t brc_curbe_surf_index;
+ } dw84;
+
+ struct {
+ uint32_t static_detection_cost_table_index;
+ } dw85;
+
+ struct {
+ uint32_t reserved0;
+ } dw86;
+
+ struct {
+ uint32_t reserved0;
+ } dw87;
+
+} gen9_avc_mbenc_curbe_data;
+
+#define GEN9_AVC_KERNEL_MBENC_QUALITY_I 0
+#define GEN9_AVC_KERNEL_MBENC_QUALITY_P 1
+#define GEN9_AVC_KERNEL_MBENC_QUALITY_B 2
+#define GEN9_AVC_KERNEL_MBENC_NORMAL_I 3
+#define GEN9_AVC_KERNEL_MBENC_NORMAL_P 4
+#define GEN9_AVC_KERNEL_MBENC_NORMAL_B 5
+#define GEN9_AVC_KERNEL_MBENC_PERFORMANCE_I 6
+#define GEN9_AVC_KERNEL_MBENC_PERFORMANCE_P 7
+#define GEN9_AVC_KERNEL_MBENC_PERFORMANCE_B 8
+#define NUM_GEN9_AVC_KERNEL_MBENC 9
+
+struct gen9_avc_mbenc_context
+{
+ struct i965_gpe_context gpe_contexts[NUM_GEN9_AVC_KERNEL_MBENC];
+};
+
+/*
+static frame detection structure and define
+*/
+typedef enum _gen9_avc_binding_table_offset_sfd
+{
+ GEN9_AVC_SFD_VDENC_INPUT_IMAGE_STATE_INDEX = 0,
+ GEN9_AVC_SFD_MV_DATA_SURFACE_INDEX = 1,
+ GEN9_AVC_SFD_INTER_DISTORTION_SURFACE_INDEX = 2,
+ GEN9_AVC_SFD_OUTPUT_DATA_SURFACE_INDEX = 3,
+ GEN9_AVC_SFD_VDENC_OUTPUT_IMAGE_STATE_INDEX = 4,
+ GEN9_AVC_SFD_NUM_SURFACES = 5
+} gen9_avc_binding_table_offset_sfd;
+
+typedef struct _gen9_avc_sfd_curbe_data
+{
+ struct
+ {
+ uint32_t vdenc_mode_disable:1;
+ uint32_t brc_mode_enable:1;
+ uint32_t slice_type:2;
+ uint32_t reserved0:1;
+ uint32_t stream_in_type:4;
+ uint32_t enable_adaptive_mv_stream_in:1;
+ uint32_t reserved1:1;
+ uint32_t enable_intra_cost_scaling_for_static_frame:1;
+ uint32_t reserved2:20;
+ } dw0;
+
+ struct
+ {
+ uint32_t qp_value:8;
+ uint32_t num_of_refs:8;
+ uint32_t hme_stream_in_ref_cost:8;
+ uint32_t reserved0:8;
+ } dw1;
+
+ struct
+ {
+ uint32_t frame_width_in_mbs:16;
+ uint32_t frame_height_in_mbs:16;
+ } dw2;
+
+ struct
+ {
+ uint32_t large_mv_threshold;
+ } dw3;
+
+ struct
+ {
+ uint32_t total_large_mv_threshold;
+ } dw4;
+
+ struct
+ {
+ uint32_t zmv_threshold;
+ } dw5;
+
+ struct
+ {
+ uint32_t total_zmv_threshold;
+ } dw6;
+
+ struct
+ {
+ uint32_t min_dist_threshold;
+ } dw7;
+
+ char cost_table[52];
+ struct
+ {
+ uint32_t actual_width_in_mb:16;
+ uint32_t actual_height_in_mb:16;
+ } dw21;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw22;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw23;
+
+ struct
+ {
+ uint32_t vdenc_input_image_state_index;
+ } dw24;
+
+ struct
+ {
+ uint32_t reserved;
+ } dw25;
+
+ struct
+ {
+ uint32_t mv_data_surface_index;
+ } dw26;
+
+ struct
+ {
+ uint32_t inter_distortion_surface_index;
+ } dw27;
+
+ struct
+ {
+ uint32_t output_data_surface_index;
+ } dw28;
+
+ struct
+ {
+ uint32_t vdenc_output_image_state_index;
+ } dw29;
+
+}gen9_avc_sfd_curbe_data;
+
+struct gen9_avc_sfd_context
+{
+ struct i965_gpe_context gpe_contexts;
+};
+
+/*
+common structure and define
+*/
+struct gen9_avc_encoder_context {
+
+ VADriverContextP ctx;
+
+ /* VME resource */
+ //mbbrc/brc:inti/reset/update
+ struct i965_gpe_resource res_brc_history_buffer;
+ struct i965_gpe_resource res_brc_dist_data_surface;
+ //brc:update
+ struct i965_gpe_resource res_brc_pre_pak_statistics_output_buffer;
+ struct i965_gpe_resource res_brc_image_state_read_buffer;
+ struct i965_gpe_resource res_brc_image_state_write_buffer;
+ struct i965_gpe_resource res_brc_mbenc_curbe_read_buffer;
+ struct i965_gpe_resource res_brc_mbenc_curbe_write_buffer;
+ struct i965_gpe_resource res_brc_const_data_buffer;
+ //brc and mbbrc
+ struct i965_gpe_resource res_mb_status_buffer;
+ //mbbrc
+ struct i965_gpe_resource res_mbbrc_mb_qp_data_surface;
+ struct i965_gpe_resource res_mbbrc_roi_surface;
+ struct i965_gpe_resource res_mbbrc_const_data_buffer;
+
+ //mbenc
+ struct i965_gpe_resource res_mbenc_slice_map_surface;
+
+ //scaling flatness check surface
+ struct i965_gpe_resource res_flatness_check_surface;
+ //me
+ struct i965_gpe_resource s4x_memv_min_distortion_brc_buffer;
+ struct i965_gpe_resource s4x_memv_distortion_buffer;
+ struct i965_gpe_resource s4x_memv_data_buffer;
+ struct i965_gpe_resource s16x_memv_data_buffer;
+ struct i965_gpe_resource s32x_memv_data_buffer;
+
+
+ struct i965_gpe_resource res_image_state_batch_buffer_2nd_level;
+ struct intel_batchbuffer *pres_slice_batch_buffer_2nd_level;
+ // mb code/data or indrirect mv data, define in private avc surface
+
+ //sfd
+ struct i965_gpe_resource res_sfd_output_buffer;
+ struct i965_gpe_resource res_sfd_cost_table_p_frame_buffer;
+ struct i965_gpe_resource res_sfd_cost_table_b_frame_buffer;
+
+ //external mb qp data,application input
+ struct i965_gpe_resource res_mb_qp_data_surface;
+
+ struct i965_gpe_resource res_mad_data_buffer;
+
+ //wp
+ VASurfaceID wp_output_pic_select_surface_id[2];
+ struct object_surface *wp_output_pic_select_surface_obj[2];
+ struct i965_gpe_resource res_wp_output_pic_select_surface_list[2];
+
+ //mb disable skip
+ struct i965_gpe_resource res_mb_disable_skip_map_surface;
+
+ /* PAK resource */
+ //internal
+ struct i965_gpe_resource res_intra_row_store_scratch_buffer;
+ struct i965_gpe_resource res_deblocking_filter_row_store_scratch_buffer;
+ struct i965_gpe_resource res_deblocking_filter_tile_col_buffer;
+ struct i965_gpe_resource res_bsd_mpc_row_store_scratch_buffer;
+ struct i965_gpe_resource res_mfc_indirect_bse_object;
+ struct i965_gpe_resource res_pak_mb_status_buffer;
+ struct i965_gpe_resource res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS];//INTERNAL: 0-31 as input,32 and 33 as output
+
+ //output
+ struct i965_gpe_resource res_post_deblocking_output;
+ struct i965_gpe_resource res_pre_deblocking_output;
+
+ //ref list
+ struct i965_gpe_resource list_reference_res[MAX_MFC_AVC_REFERENCE_SURFACES];
+
+ // kernel context
+ struct gen9_avc_scaling_context context_scaling;
+ struct gen9_avc_me_context context_me;
+ struct gen9_avc_brc_context context_brc;
+ struct gen9_avc_mbenc_context context_mbenc;
+ struct gen9_avc_wp_context context_wp;
+ struct gen9_avc_sfd_context context_sfd;
+
+ struct encoder_status_buffer_internal status_buffer;
+
+};
+
+#define MAX_AVC_SLICE_NUM 256
+struct avc_enc_state {
+
+ VAEncSequenceParameterBufferH264 *seq_param;
+ VAEncPictureParameterBufferH264 *pic_param;
+ VAEncSliceParameterBufferH264 *slice_param[MAX_AVC_SLICE_NUM];
+ VAEncMacroblockParameterBufferH264 *mb_param;
+
+ uint32_t mad_enable:1;
+ //mb skip
+ uint32_t mb_disable_skip_map_enable:1;
+ //static frame detection
+ uint32_t sfd_enable:1;
+ uint32_t sfd_mb_enable:1;
+ uint32_t adaptive_search_window_enable:1;
+ //external mb qp
+ uint32_t mb_qp_data_enable:1;
+ //rolling intra refresh
+ uint32_t intra_refresh_i_enable:1;
+ uint32_t min_max_qp_enable:1;
+ uint32_t skip_bias_adjustment_enable:1;
+
+ uint32_t non_ftq_skip_threshold_lut_input_enable:1;
+ uint32_t ftq_skip_threshold_lut_input_enable:1;
+ uint32_t ftq_override:1;
+ uint32_t direct_bias_adjustment_enable:1;
+ uint32_t global_motion_bias_adjustment_enable:1;
+ uint32_t disable_sub_mb_partion:1;
+ uint32_t arbitrary_num_mbs_in_slice:1;
+ uint32_t adaptive_transform_decision_enable:1;
+ uint32_t skip_check_disable:1;
+ uint32_t tq_enable:1;
+ uint32_t enable_avc_ildb:1;
+ uint32_t suppress_recon_enable:1;
+ uint32_t flatness_check_supported:1;
+ uint32_t transform_8x8_mode_enable:1;
+ uint32_t caf_supported:1;
+ uint32_t mb_status_enable:1;
+ uint32_t mbaff_flag:1;
+ uint32_t enable_force_skip:1;
+ uint32_t rc_panic_enable:1;
+ uint32_t reserved0:7;
+
+ //generic begin
+ uint32_t ref_pic_select_list_supported:1;
+ uint32_t mb_brc_supported:1;
+ uint32_t multi_pre_enable:1;
+ uint32_t ftq_enable:1;
+ uint32_t caf_enable:1;
+ uint32_t caf_disable_hd:1;
+ uint32_t skip_bias_adjustment_supported:1;
+
+ uint32_t adaptive_intra_scaling_enable:1;
+ uint32_t old_mode_cost_enable:1;
+ uint32_t multi_ref_qp_enable:1;
+ uint32_t weighted_ref_l0_enable:1;
+ uint32_t weighted_ref_l1_enable:1;
+ uint32_t weighted_prediction_supported:1;
+ uint32_t brc_split_enable:1;
+ uint32_t slice_level_report_supported:1;
+
+ uint32_t fbr_bypass_enable:1;
+ //mb status output in scaling kernel
+ uint32_t field_scaling_output_interleaved:1;
+ uint32_t mb_variance_output_enable:1;
+ uint32_t mb_pixel_average_output_enable:1;
+ uint32_t rolling_intra_refresh_enable:1;
+ uint32_t mbenc_curbe_set_in_brc_update:1;
+ //rounding
+ uint32_t rounding_inter_enable:1;
+ uint32_t adaptive_rounding_inter_enable:1;
+
+ uint32_t mbenc_i_frame_dist_in_use:1;
+ uint32_t mb_status_supported:1;
+ uint32_t mb_vproc_stats_enable:1;
+ uint32_t flatness_check_enable:1;
+ uint32_t block_based_skip_enable:1;
+ uint32_t use_widi_mbenc_kernel:1;
+ uint32_t kernel_trellis_enable:1;
+ uint32_t generic_reserved:1;
+ //generic end
+
+ //rounding
+ uint32_t rounding_value;
+ uint32_t rounding_inter_p;
+ uint32_t rounding_inter_b;
+ uint32_t rounding_inter_b_ref;
+
+ //min,max qp
+ uint8_t min_qp_i;
+ uint8_t max_qp_i;
+ uint8_t min_qp_p;
+ uint8_t max_qp_p;
+ uint8_t min_qp_b;
+ uint8_t max_qp_b;
+
+ uint8_t non_ftq_skip_threshold_lut[52];
+ uint8_t ftq_skip_threshold_lut[52];
+ uint8_t lamda_value_lut[52][2];
+
+
+ uint32_t intra_refresh_qp_threshold;
+ uint32_t trellis_flag;
+ uint32_t hme_mv_cost_scaling_factor;
+ uint32_t slice_height;//default 1
+ uint32_t slice_num;//default 1
+ uint32_t dist_scale_factor_list0[32];
+ uint32_t bi_weight;
+ uint32_t brc_const_data_surface_width;
+ uint32_t brc_const_data_surface_height;
+
+ uint32_t num_refs[2];
+ uint32_t list_ref_idx[2][32];
+ int32_t top_field_poc[NUM_MFC_AVC_DMV_BUFFERS];
+
+ uint32_t tq_rounding;
+
+ uint32_t zero_mv_threshold; //sfd
+
+ uint32_t slice_second_levle_batch_buffer_in_use;
+ uint32_t slice_batch_offset[MAX_AVC_SLICE_NUM];
+
+};
+
+#endif /* GEN9_AVC_ENCODER_H */
--
2.7.4
Pengfei Qu
2017-01-13 09:24:12 UTC
Permalink
Signed-off-by: Pengfei Qu <***@intel.com>
Reviewed-by: Sean V Kelley<***@posteo.de>
---
src/Makefile.am | 10 ++++++++++
src/i965_drv_video.c | 8 ++++++--
src/i965_drv_video.h | 2 ++
src/i965_encoder.c | 52 ++++++++++++++++++++++++++++++++++++++++++++--------
4 files changed, 62 insertions(+), 10 deletions(-)

diff --git a/src/Makefile.am b/src/Makefile.am
index 424812b..e0f3aec 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -101,6 +101,10 @@ source_c = \
gen9_vp9_encoder_kernels.c \
gen9_vp9_const_def.c \
gen9_vp9_encoder.c \
+ i965_avc_encoder_common.c \
+ i965_encoder_common.c \
+ gen9_avc_const_def.c \
+ gen9_avc_encoder.c \
intel_common_vpp_internal.c \
$(NULL)

@@ -154,6 +158,12 @@ source_h = \
gen9_vp9_encapi.h \
gen9_vp9_const_def.h \
gen9_vp9_encoder_kernels.h \
+ i965_encoder_api.h \
+ i965_avc_encoder_common.h \
+ i965_encoder_common.h \
+ gen9_avc_encoder.h \
+ gen9_avc_const_def.h \
+ gen9_avc_encoder_kernels.h \
intel_gen_vppapi.h \
intel_common_vpp_internal.h \
$(NULL)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index cc37190..64cc0e2 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -911,6 +911,7 @@ i965_GetConfigAttributes(VADriverContextP ctx,
VAConfigAttrib *attrib_list, /* in/out */
int num_attribs)
{
+ struct i965_driver_data * const i965 = i965_driver_data(ctx);
VAStatus va_status;
int i;

@@ -1003,8 +1004,11 @@ i965_GetConfigAttributes(VADriverContextP ctx,
attrib_list[i].value = 1;
if (profile == VAProfileH264ConstrainedBaseline ||
profile == VAProfileH264Main ||
- profile == VAProfileH264High )
- attrib_list[i].value = ENCODER_QUALITY_RANGE;
+ profile == VAProfileH264High ){
+ attrib_list[i].value = ENCODER_QUALITY_RANGE;
+ if(IS_GEN9(i965->intel.device_info))
+ attrib_list[i].value = ENCODER_QUALITY_RANGE_AVC;
+ }
break;
}
break;
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index 7cba3a3..334b788 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -69,7 +69,9 @@
#define DEFAULT_SATURATION 50

#define ENCODER_QUALITY_RANGE 2
+#define ENCODER_QUALITY_RANGE_AVC 8
#define ENCODER_DEFAULT_QUALITY 1
+#define ENCODER_DEFAULT_QUALITY_AVC 4
#define ENCODER_HIGH_QUALITY ENCODER_DEFAULT_QUALITY
#define ENCODER_LOW_QUALITY 2

diff --git a/src/i965_encoder.c b/src/i965_encoder.c
index 0a648d4..6a32a3f 100644
--- a/src/i965_encoder.c
+++ b/src/i965_encoder.c
@@ -41,6 +41,7 @@
#include "gen6_mfc.h"

#include "i965_post_processing.h"
+#include "i965_encoder_api.h"

static struct intel_fraction
reduce_fraction(struct intel_fraction f)
@@ -789,9 +790,11 @@ intel_encoder_check_temporal_layer_structure(VADriverContextP ctx,

static VAStatus
intel_encoder_check_misc_parameter(VADriverContextP ctx,
+ VAProfile profile,
struct encode_state *encode_state,
struct intel_encoder_context *encoder_context)
{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
VAStatus ret = VA_STATUS_SUCCESS;

if (encode_state->misc_param[VAEncMiscParameterTypeQualityLevel][0] &&
@@ -800,12 +803,31 @@ intel_encoder_check_misc_parameter(VADriverContextP ctx,
VAEncMiscParameterBufferQualityLevel* param_quality_level = (VAEncMiscParameterBufferQualityLevel*)pMiscParam->data;
encoder_context->quality_level = param_quality_level->quality_level;

- if (encoder_context->quality_level == 0)
- encoder_context->quality_level = ENCODER_DEFAULT_QUALITY;
- else if (encoder_context->quality_level > encoder_context->quality_range) {
- ret = VA_STATUS_ERROR_INVALID_PARAMETER;
- goto out;
+ switch (profile) {
+ case VAProfileH264ConstrainedBaseline:
+ case VAProfileH264Main:
+ case VAProfileH264High:
+ if (IS_SKL(i965->intel.device_info))
+ {
+ if (encoder_context->quality_level == 0)
+ encoder_context->quality_level = ENCODER_DEFAULT_QUALITY_AVC;
+ }
+ else
+ {
+ if (encoder_context->quality_level == 0)
+ encoder_context->quality_level = ENCODER_DEFAULT_QUALITY;
+ }
+ break;
+ default:
+ if (encoder_context->quality_level == 0)
+ encoder_context->quality_level = ENCODER_DEFAULT_QUALITY;
+ break;
}
+
+ if (encoder_context->quality_level > encoder_context->quality_range) {
+ ret = VA_STATUS_ERROR_INVALID_PARAMETER;
+ goto out;
+ }
}

ret = intel_encoder_check_temporal_layer_structure(ctx, encode_state, encoder_context);
@@ -1281,7 +1303,7 @@ intel_encoder_sanity_check_input(VADriverContextP ctx,
}

if (vaStatus == VA_STATUS_SUCCESS)
- vaStatus = intel_encoder_check_misc_parameter(ctx, encode_state, encoder_context);
+ vaStatus = intel_encoder_check_misc_parameter(ctx, profile, encode_state, encoder_context);

out:
return vaStatus;
@@ -1362,6 +1384,7 @@ intel_enc_hw_context_init(VADriverContextP ctx,
hw_init_func vme_context_init,
hw_init_func mfc_context_init)
{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
struct intel_driver_data *intel = intel_driver_data(ctx);
struct intel_encoder_context *encoder_context = calloc(1, sizeof(struct intel_encoder_context));
int i;
@@ -1394,7 +1417,9 @@ intel_enc_hw_context_init(VADriverContextP ctx,
encoder_context->codec = CODEC_H264;

if (obj_config->entrypoint == VAEntrypointEncSliceLP)
- encoder_context->quality_range = ENCODER_LP_QUALITY_RANGE;
+ encoder_context->quality_range = ENCODER_QUALITY_RANGE_AVC;
+ else if(IS_SKL(i965->intel.device_info))
+ encoder_context->quality_range = ENCODER_QUALITY_RANGE_AVC;
else
encoder_context->quality_range = ENCODER_QUALITY_RANGE;
break;
@@ -1485,5 +1510,16 @@ gen8_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
struct hw_context *
gen9_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
{
- return intel_enc_hw_context_init(ctx, obj_config, gen9_vme_context_init, gen9_mfc_context_init);
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ switch (obj_config->profile){
+ case VAProfileH264ConstrainedBaseline:
+ case VAProfileH264Main:
+ case VAProfileH264High:
+ if (IS_SKL(i965->intel.device_info))
+ return intel_enc_hw_context_init(ctx, obj_config, gen9_avc_vme_context_init, gen9_avc_pak_context_init);
+ else
+ return intel_enc_hw_context_init(ctx, obj_config, gen9_vme_context_init, gen9_mfc_context_init);
+ default:
+ return intel_enc_hw_context_init(ctx, obj_config, gen9_vme_context_init, gen9_mfc_context_init);
+ }
}
--
2.7.4
Pengfei Qu
2017-01-13 09:24:11 UTC
Permalink
MFX pipeline:
add MFX command for AVC encoder
add MFX Picture slice level command init for AVC
add MFX pipeline init prepare run for AVC encode
add VME/MFX context init for AVC encoder

Reviewed-by: Sean V Kelley<***@posteo.de>
Signed-off-by: Pengfei Qu <***@intel.com>
---
src/gen9_avc_encoder.c | 1887 +++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 1886 insertions(+), 1 deletion(-)

diff --git a/src/gen9_avc_encoder.c b/src/gen9_avc_encoder.c
index 5caa9f4..a7545f1 100755
--- a/src/gen9_avc_encoder.c
+++ b/src/gen9_avc_encoder.c
@@ -5742,4 +5742,1889 @@ gen9_avc_kernel_init(VADriverContextP ctx,
generic_ctx->pfn_send_brc_mb_update_surface = gen9_avc_send_surface_brc_mb_update;
generic_ctx->pfn_send_sfd_surface = gen9_avc_send_surface_sfd;
generic_ctx->pfn_send_wp_surface = gen9_avc_send_surface_wp;
-}
\ No newline at end of file
+}
+
+/*
+PAK pipeline related function
+*/
+extern int
+intel_avc_enc_slice_type_fixup(int slice_type);
+
+static void
+gen9_mfc_avc_pipe_mode_select(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 5);
+
+ OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
+ OUT_BCS_BATCH(batch,
+ (0 << 29) |
+ (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
+ (MFD_MODE_VLD << 15) |
+ (0 << 13) | /* VDEnc mode is 1*/
+ ((generic_state->curr_pak_pass != (generic_state->num_pak_passes -1)) << 10) | /* Stream-Out Enable */
+ ((!!avc_ctx->res_post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
+ ((!!avc_ctx->res_pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
+ (0 << 7) | /* Scaled surface enable */
+ (0 << 6) | /* Frame statistics stream out enable, always '1' in VDEnc mode */
+ (0 << 5) | /* not in stitch mode */
+ (1 << 4) | /* encoding mode */
+ (MFX_FORMAT_AVC << 0));
+ OUT_BCS_BATCH(batch,
+ (0 << 7) | /* expand NOA bus flag */
+ (0 << 6) | /* disable slice-level clock gating */
+ (0 << 5) | /* disable clock gating for NOA */
+ (0 << 4) | /* terminate if AVC motion and POC table error occurs */
+ (0 << 3) | /* terminate if AVC mbdata error occurs */
+ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
+ (0 << 1) |
+ (0 << 0));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_surface_state(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ struct i965_gpe_resource *gpe_resource,
+ int id)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 6);
+
+ OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
+ OUT_BCS_BATCH(batch, id);
+ OUT_BCS_BATCH(batch,
+ ((gpe_resource->height - 1) << 18) |
+ ((gpe_resource->width - 1) << 4));
+ OUT_BCS_BATCH(batch,
+ (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
+ (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
+ ((gpe_resource->pitch - 1) << 3) | /* pitch */
+ (0 << 2) | /* must be 0 for interleave U/V */
+ (1 << 1) | /* must be tiled */
+ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
+ OUT_BCS_BATCH(batch,
+ (0 << 16) | /* must be 0 for interleave U/V */
+ (gpe_resource->y_cb_offset)); /* y offset for U(cb) */
+ OUT_BCS_BATCH(batch,
+ (0 << 16) | /* must be 0 for interleave U/V */
+ (gpe_resource->y_cb_offset)); /* y offset for U(cb) */
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ int i;
+
+ BEGIN_BCS_BATCH(batch, 65);
+
+ OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (65 - 2));
+
+ /* the DW1-3 is for pre_deblocking */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_pre_deblocking_output.bo, 1, 0, 0);
+
+ /* the DW4-6 is for the post_deblocking */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_post_deblocking_output.bo, 1, 0, 0);
+
+ /* the DW7-9 is for the uncompressed_picture */
+ OUT_BUFFER_3DW(batch, generic_ctx->res_uncompressed_input_surface.bo, 1, 0, 0);
+
+ /* the DW10-12 is for PAK information (write) */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, 0);//?
+
+ /* the DW13-15 is for the intra_row_store_scratch */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_intra_row_store_scratch_buffer.bo, 1, 0, 0);
+
+ /* the DW16-18 is for the deblocking filter */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_deblocking_filter_row_store_scratch_buffer.bo, 1, 0, 0);
+
+ /* the DW 19-50 is for Reference pictures*/
+ for (i = 0; i < ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {
+ OUT_BUFFER_2DW(batch, avc_ctx->list_reference_res[i].bo, 1, 0);
+ }
+
+ /* DW 51, reference picture attributes */
+ OUT_BCS_BATCH(batch, 0);
+
+ /* The DW 52-54 is for PAK information (read) */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, 0);
+
+ /* the DW 55-57 is the ILDB buffer */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ /* the DW 58-60 is the second ILDB buffer */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ /* DW 61, memory compress enable & mode */
+ OUT_BCS_BATCH(batch, 0);
+
+ /* the DW 62-64 is the buffer */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_ind_obj_base_addr_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+ unsigned int size = 0;
+ unsigned int w_mb = generic_state->frame_width_in_mbs;
+ unsigned int h_mb = generic_state->frame_height_in_mbs;
+
+ obj_surface = encode_state->reconstructed_object;
+
+ if (!obj_surface || !obj_surface->private_data)
+ return;
+ avc_priv_surface = obj_surface->private_data;
+
+ BEGIN_BCS_BATCH(batch, 26);
+
+ OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
+ /* The DW1-5 is for the MFX indirect bistream offset, ignore for VDEnc mode */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+ OUT_BUFFER_2DW(batch, NULL, 0, 0);
+
+ /* the DW6-10 is for MFX Indirect MV Object Base Address, ignore for VDEnc mode */
+ size = w_mb * h_mb * 32 * 4;
+ OUT_BUFFER_3DW(batch,
+ avc_priv_surface->res_mv_data_surface.bo,
+ 1,
+ 0,
+ 0);
+ OUT_BUFFER_2DW(batch,
+ avc_priv_surface->res_mv_data_surface.bo,
+ 1,
+ ALIGN(size,0x1000));
+
+ /* The DW11-15 is for MFX IT-COFF. Not used on encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+ OUT_BUFFER_2DW(batch, NULL, 0, 0);
+
+ /* The DW16-20 is for MFX indirect DBLK. Not used on encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+ OUT_BUFFER_2DW(batch, NULL, 0, 0);
+
+ /* The DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder
+ * Note: an offset is specified in MFX_AVC_SLICE_STATE
+ */
+ OUT_BUFFER_3DW(batch,
+ generic_ctx->compressed_bitstream.res.bo,
+ 1,
+ 0,
+ 0);
+ OUT_BUFFER_2DW(batch,
+ generic_ctx->compressed_bitstream.res.bo,
+ 1,
+ generic_ctx->compressed_bitstream.end_offset);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 10);
+
+ OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
+
+ /* The DW1-3 is for bsd/mpc row store scratch buffer */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_bsd_mpc_row_store_scratch_buffer.bo, 1, 0, 0);
+
+ /* The DW4-6 is for MPR Row Store Scratch Buffer Base Address, ignore for encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ /* The DW7-9 is for Bitplane Read Buffer Base Address, ignore for encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_directmode_state(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+
+ int i;
+
+ BEGIN_BCS_BATCH(batch, 71);
+
+ OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
+
+ /* Reference frames and Current frames */
+ /* the DW1-32 is for the direct MV for reference */
+ for(i = 0; i < NUM_MFC_AVC_DMV_BUFFERS - 2; i += 2) {
+ if ( avc_ctx->res_direct_mv_buffersr[i].bo != NULL) {
+ OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[i].bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+ } else {
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ }
+ }
+
+ OUT_BCS_BATCH(batch, 0);
+
+ /* the DW34-36 is the MV for the current reference */
+ OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS - 2].bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+
+ OUT_BCS_BATCH(batch, 0);
+
+ /* POL list */
+ for(i = 0; i < 32; i++) {
+ OUT_BCS_BATCH(batch, avc_state->top_field_poc[i]);
+ }
+ OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 2]);
+ OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 1]);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_qm_state(VADriverContextP ctx,
+ int qm_type,
+ const unsigned int *qm,
+ int qm_length,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ unsigned int qm_buffer[16];
+
+ assert(qm_length <= 16);
+ assert(sizeof(*qm) == 4);
+ memset(qm_buffer,0,16*4);
+ memcpy(qm_buffer, qm, qm_length * 4);
+
+ BEGIN_BCS_BATCH(batch, 18);
+ OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
+ OUT_BCS_BATCH(batch, qm_type << 0);
+ intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_qm_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ VAEncSequenceParameterBufferH264 *seq_param = avc_state->seq_param;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+
+ /* TODO: add support for non flat matrix */
+ const unsigned int *qm_4x4_intra;
+ const unsigned int *qm_4x4_inter;
+ const unsigned int *qm_8x8_intra;
+ const unsigned int *qm_8x8_inter;
+
+ if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag
+ && !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {
+ qm_4x4_intra = qm_4x4_inter = qm_8x8_intra = qm_8x8_inter = qm_flat;
+ } else {
+ VAIQMatrixBufferH264 *qm;
+ assert(encode_state->q_matrix && encode_state->q_matrix->buffer);
+ qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
+ qm_4x4_intra = (unsigned int *)qm->ScalingList4x4[0];
+ qm_4x4_inter = (unsigned int *)qm->ScalingList4x4[3];
+ qm_8x8_intra = (unsigned int *)qm->ScalingList8x8[0];
+ qm_8x8_inter = (unsigned int *)qm->ScalingList8x8[1];
+ }
+
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm_4x4_intra, 12, encoder_context);
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm_4x4_inter, 12, encoder_context);
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm_8x8_intra, 16, encoder_context);
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm_8x8_inter, 16, encoder_context);
+}
+
+static void
+gen9_mfc_fqm_state(VADriverContextP ctx,
+ int fqm_type,
+ const unsigned int *fqm,
+ int fqm_length,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ unsigned int fqm_buffer[32];
+
+ assert(fqm_length <= 32);
+ assert(sizeof(*fqm) == 4);
+ memset(fqm_buffer,0,32*4);
+ memcpy(fqm_buffer, fqm, fqm_length * 4);
+
+ BEGIN_BCS_BATCH(batch, 34);
+ OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
+ OUT_BCS_BATCH(batch, fqm_type << 0);
+ intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_fill_fqm(uint8_t *qm, uint16_t *fqm, int len)
+{
+ int i, j;
+ for (i = 0; i < len; i++)
+ for (j = 0; j < len; j++)
+ fqm[i * len + j] = (1 << 16) / qm[j * len + i];
+}
+
+static void
+gen9_mfc_avc_fqm_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ /* TODO: add support for non flat matrix */
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ VAEncSequenceParameterBufferH264 *seq_param = avc_state->seq_param;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+
+ if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag
+ && !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm_flat, 24, encoder_context);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm_flat, 24, encoder_context);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm_flat, 32, encoder_context);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm_flat, 32, encoder_context);
+ } else {
+ int i;
+ uint32_t fqm[32];
+ VAIQMatrixBufferH264 *qm;
+ assert(encode_state->q_matrix && encode_state->q_matrix->buffer);
+ qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
+
+ for (i = 0; i < 3; i++)
+ gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * i, 4);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm, 24, encoder_context);
+
+ for (i = 3; i < 6; i++)
+ gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * (i - 3), 4);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm, 24, encoder_context);
+
+ gen9_mfc_fill_fqm(qm->ScalingList8x8[0], (uint16_t *)fqm, 8);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm, 32, encoder_context);
+
+ gen9_mfc_fill_fqm(qm->ScalingList8x8[1], (uint16_t *)fqm, 8);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm, 32, encoder_context);
+ }
+}
+
+static void
+gen9_mfc_avc_insert_object(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
+ int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
+ int slice_header_indicator,
+ struct intel_batchbuffer *batch)
+{
+ if (data_bits_in_last_dw == 0)
+ data_bits_in_last_dw = 32;
+
+ BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
+
+ OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws));
+ OUT_BCS_BATCH(batch,
+ (0 << 16) | /* always start at offset 0 */
+ (slice_header_indicator << 14) |
+ (data_bits_in_last_dw << 8) |
+ (skip_emul_byte_count << 4) |
+ (!!emulation_flag << 3) |
+ ((!!is_last_header) << 2) |
+ ((!!is_end_of_slice) << 1) |
+ (0 << 0)); /* TODO: check this flag */
+ intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_insert_slice_packed_data(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int slice_index,
+ struct intel_batchbuffer *batch)
+{
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int length_in_bits;
+ unsigned int *header_data = NULL;
+ int count, i, start_index;
+ int slice_header_index;
+
+ if (encode_state->slice_header_index[slice_index] == 0)
+ slice_header_index = -1;
+ else
+ slice_header_index = (encode_state->slice_header_index[slice_index] & SLICE_PACKED_DATA_INDEX_MASK);
+
+ count = encode_state->slice_rawdata_count[slice_index];
+ start_index = (encode_state->slice_rawdata_index[slice_index] & SLICE_PACKED_DATA_INDEX_MASK);
+
+ for (i = 0; i < count; i++) {
+ unsigned int skip_emul_byte_cnt;
+
+ header_data = (unsigned int *)encode_state->packed_header_data_ext[start_index + i]->buffer;
+
+ param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[start_index + i]->buffer);
+
+ /* skip the slice header packed data type as it is lastly inserted */
+ if (param->type == VAEncPackedHeaderSlice)
+ continue;
+
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+
+ /* as the slice header is still required, the last header flag is set to
+ * zero.
+ */
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32) >> 5,
+ length_in_bits & 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ }
+
+ if (slice_header_index == -1) {
+ VAEncSequenceParameterBufferH264 *seq_param = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+ VAEncSliceParameterBufferH264 *slice_params = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
+ unsigned char *slice_header = NULL;
+ int slice_header_length_in_bits = 0;
+
+ /* No slice header data is passed. And the driver needs to generate it */
+ /* For the Normal H264 */
+ slice_header_length_in_bits = build_avc_slice_header(seq_param,
+ pic_param,
+ slice_params,
+ &slice_header);
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ (unsigned int *)slice_header,
+ ALIGN(slice_header_length_in_bits, 32) >> 5,
+ slice_header_length_in_bits & 0x1f,
+ 5, /* first 5 bytes are start code + nal unit type */
+ 1, 0, 1,
+ 1,
+ batch);
+
+ free(slice_header);
+ } else {
+ unsigned int skip_emul_byte_cnt;
+
+ header_data = (unsigned int *)encode_state->packed_header_data_ext[slice_header_index]->buffer;
+
+ param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[slice_header_index]->buffer);
+ length_in_bits = param->bit_length;
+
+ /* as the slice header is the last header data for one slice,
+ * the last header flag is set to one.
+ */
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32) >> 5,
+ length_in_bits & 0x1f,
+ skip_emul_byte_cnt,
+ 1,
+ 0,
+ !param->has_emulation_bytes,
+ 1,
+ batch);
+ }
+
+ return;
+}
+
+static void
+gen9_mfc_avc_inset_headers(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ int slice_index,
+ struct intel_batchbuffer *batch)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SPS);
+ unsigned int internal_rate_mode = generic_state->internal_rate_mode;
+ unsigned int skip_emul_byte_cnt;
+
+ if (slice_index == 0) {
+ if (encode_state->packed_header_data[idx]) {
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
+ unsigned int length_in_bits;
+
+ assert(encode_state->packed_header_param[idx]);
+ param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32) >> 5,
+ length_in_bits & 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ }
+
+ idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_PPS);
+
+ if (encode_state->packed_header_data[idx]) {
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
+ unsigned int length_in_bits;
+
+ assert(encode_state->packed_header_param[idx]);
+ param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32) >> 5,
+ length_in_bits & 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ }
+
+ idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SEI);
+
+ if (encode_state->packed_header_data[idx]) {
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
+ unsigned int length_in_bits;
+
+ assert(encode_state->packed_header_param[idx]);
+ param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32) >> 5,
+ length_in_bits & 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ } else if (internal_rate_mode == VA_RC_CBR) {
+ /* TODO: insert others */
+ }
+ }
+
+ gen9_mfc_avc_insert_slice_packed_data(ctx,
+ encode_state,
+ encoder_context,
+ slice_index,
+ batch);
+}
+
+static void
+gen9_mfc_avc_slice_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncPictureParameterBufferH264 *pic_param,
+ VAEncSliceParameterBufferH264 *slice_param,
+ VAEncSliceParameterBufferH264 *next_slice_param,
+ struct intel_batchbuffer *batch)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
+ unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
+ unsigned char correct[6], grow, shrink;
+ int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
+ int max_qp_n, max_qp_p;
+ int i;
+ int weighted_pred_idc = 0;
+ int num_ref_l0 = 0, num_ref_l1 = 0;
+ int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+ int slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+ unsigned int rc_panic_enable = 0;
+ unsigned int rate_control_counter_enable = 0;
+ unsigned int rounding_value = 0;
+ unsigned int rounding_inter_enable = 0;
+
+ //check the inter rounding
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ if(avc_state->rounding_inter_p == AVC_INVALID_ROUNDING_VALUE)
+ {
+ if(avc_state->adaptive_rounding_inter_enable && !(generic_state->brc_enabled))
+ {
+ if(generic_state->gop_ref_distance == 1)
+ avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p_without_b[slice_qp];
+ else
+ avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p[slice_qp];
+ }
+ else
+ {
+ avc_state->rounding_value = gen9_avc_inter_rounding_p[generic_state->preset];
+ }
+
+ }else
+ {
+ avc_state->rounding_value = avc_state->rounding_inter_p;
+ }
+ }else if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ if(pic_param->pic_fields.bits.reference_pic_flag)
+ {
+ if(avc_state->rounding_inter_b_ref == AVC_INVALID_ROUNDING_VALUE)
+ avc_state->rounding_value = gen9_avc_inter_rounding_b_ref[generic_state->preset];
+ else
+ avc_state->rounding_value = avc_state->rounding_inter_b_ref;
+ }
+ else
+ {
+ if(avc_state->rounding_inter_b == AVC_INVALID_ROUNDING_VALUE)
+ {
+ if(avc_state->adaptive_rounding_inter_enable && !(generic_state->brc_enabled))
+ avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_b[slice_qp];
+ else
+ avc_state->rounding_value = gen9_avc_inter_rounding_b[generic_state->preset];
+ }else
+ {
+ avc_state->rounding_value = avc_state->rounding_inter_b;
+ }
+ }
+ }
+
+ slice_hor_pos = slice_param->macroblock_address % generic_state->frame_width_in_mbs;
+ slice_ver_pos = slice_param->macroblock_address / generic_state->frame_height_in_mbs;
+
+ if (next_slice_param) {
+ next_slice_hor_pos = next_slice_param->macroblock_address % generic_state->frame_width_in_mbs;
+ next_slice_ver_pos = next_slice_param->macroblock_address / generic_state->frame_height_in_mbs;
+ } else {
+ next_slice_hor_pos = 0;
+ next_slice_ver_pos = generic_state->frame_height_in_mbs;
+ }
+
+ if (slice_type == SLICE_TYPE_I) {
+ luma_log2_weight_denom = 0;
+ chroma_log2_weight_denom = 0;
+ } else if (slice_type == SLICE_TYPE_P) {
+ weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
+ num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
+ rounding_inter_enable = avc_state->rounding_inter_enable;
+ rounding_value = avc_state->rounding_value;
+
+ if (slice_param->num_ref_idx_active_override_flag)
+ num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
+ } else if (slice_type == SLICE_TYPE_B) {
+ weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
+ num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
+ num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
+ rounding_inter_enable = avc_state->rounding_inter_enable;
+ rounding_value = avc_state->rounding_value;
+
+ if (slice_param->num_ref_idx_active_override_flag) {
+ num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
+ num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
+ }
+
+ if (weighted_pred_idc == 2) {
+ /* 8.4.3 - Derivation process for prediction weights (8-279) */
+ luma_log2_weight_denom = 5;
+ chroma_log2_weight_denom = 5;
+ }
+ }
+
+ max_qp_n = 0; /* TODO: update it */
+ max_qp_p = 0; /* TODO: update it */
+ grow = 0; /* TODO: update it */
+ shrink = 0; /* TODO: update it */
+
+ rate_control_counter_enable = (generic_state->brc_enabled && (generic_state->curr_pak_pass != 0));
+ rc_panic_enable = (avc_state->rc_panic_enable &&
+ (!avc_state->min_max_qp_enable) &&
+ (encoder_context->rate_control_mode != VA_RC_CQP) &&
+ (generic_state->curr_pak_pass == (generic_state->num_pak_passes - 1)));
+
+ for (i = 0; i < 6; i++)
+ correct[i] = 0; /* TODO: update it */
+
+ BEGIN_BCS_BATCH(batch, 11);
+
+ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
+ OUT_BCS_BATCH(batch, slice_type);
+ OUT_BCS_BATCH(batch,
+ (num_ref_l1 << 24) |
+ (num_ref_l0 << 16) |
+ (chroma_log2_weight_denom << 8) |
+ (luma_log2_weight_denom << 0));
+ OUT_BCS_BATCH(batch,
+ (weighted_pred_idc << 30) |
+ (((slice_type == SLICE_TYPE_B)?slice_param->direct_spatial_mv_pred_flag:0) << 29) |
+ (slice_param->disable_deblocking_filter_idc << 27) |
+ (slice_param->cabac_init_idc << 24) |
+ (slice_qp << 16) |
+ ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
+ ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
+
+ OUT_BCS_BATCH(batch,
+ slice_ver_pos << 24 |
+ slice_hor_pos << 16 |
+ slice_param->macroblock_address);
+ OUT_BCS_BATCH(batch,
+ next_slice_ver_pos << 16 |
+ next_slice_hor_pos);
+
+ OUT_BCS_BATCH(batch,
+ (rate_control_counter_enable << 31) | /* TODO: ignore it for VDENC ??? */
+ (1 << 30) | /* ResetRateControlCounter */
+ (2 << 28) | /* Loose Rate Control */
+ (0 << 24) | /* RC Stable Tolerance */
+ (rc_panic_enable << 23) | /* RC Panic Enable */
+ (1 << 22) | /* CBP mode */
+ (0 << 21) | /* MB Type Direct Conversion, 0: Enable, 1: Disable */
+ (0 << 20) | /* MB Type Skip Conversion, 0: Enable, 1: Disable */
+ (!next_slice_param << 19) | /* Is Last Slice */
+ (0 << 18) | /* BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable */
+ (1 << 17) | /* HeaderPresentFlag */
+ (1 << 16) | /* SliceData PresentFlag */
+ (0 << 15) | /* TailPresentFlag, TODO: check it on VDEnc */
+ (1 << 13) | /* RBSP NAL TYPE */
+ (1 << 12)); /* CabacZeroWordInsertionEnable */
+
+ OUT_BCS_BATCH(batch, generic_ctx->compressed_bitstream.start_offset);
+
+ OUT_BCS_BATCH(batch,
+ (max_qp_n << 24) | /*Target QP - 24 is lowest QP*/
+ (max_qp_p << 16) | /*Target QP + 20 is highest QP*/
+ (shrink << 8) |
+ (grow << 0));
+ OUT_BCS_BATCH(batch,
+ (rounding_inter_enable << 31) |
+ (rounding_value << 28) |
+ (1 << 27) |
+ (5 << 24) |
+ (correct[5] << 20) |
+ (correct[4] << 16) |
+ (correct[3] << 12) |
+ (correct[2] << 8) |
+ (correct[1] << 4) |
+ (correct[0] << 0));
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static uint8_t
+gen9_mfc_avc_get_ref_idx_state(VAPictureH264 *va_pic, unsigned int frame_store_id)
+{
+ unsigned int is_long_term =
+ !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE);
+ unsigned int is_top_field =
+ !!(va_pic->flags & VA_PICTURE_H264_TOP_FIELD);
+ unsigned int is_bottom_field =
+ !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
+
+ return ((is_long_term << 6) |
+ (0 << 5) |
+ (frame_store_id << 1) |
+ ((is_top_field ^ 1) & is_bottom_field));
+}
+
+static void
+gen9_mfc_avc_ref_idx_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ struct intel_batchbuffer *batch)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ VAPictureH264 *ref_pic;
+ int i, slice_type, ref_idx_shift;
+ unsigned int fwd_ref_entry;
+ unsigned int bwd_ref_entry;
+
+ /* max 4 ref frames are allowed for l0 and l1 */
+ fwd_ref_entry = 0x80808080;
+ slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+
+ if ((slice_type == SLICE_TYPE_P) ||
+ (slice_type == SLICE_TYPE_B)) {
+ for (i = 0; i < avc_state->num_refs[0]; i++) {
+ ref_pic = &slice_param->RefPicList0[i];
+ ref_idx_shift = i * 8;
+
+ fwd_ref_entry &= ~(0xFF << ref_idx_shift);
+ fwd_ref_entry += (gen9_mfc_avc_get_ref_idx_state(ref_pic, avc_state->list_ref_idx[0][i]) << ref_idx_shift);
+ }
+ }
+
+ bwd_ref_entry = 0x80808080;
+ if (slice_type == SLICE_TYPE_B) {
+ for (i = 0; i < avc_state->num_refs[1]; i++) {
+ ref_pic = &slice_param->RefPicList1[i];
+ ref_idx_shift = i * 8;
+
+ bwd_ref_entry &= ~(0xFF << ref_idx_shift);
+ bwd_ref_entry += (gen9_mfc_avc_get_ref_idx_state(ref_pic, avc_state->list_ref_idx[1][i]) << ref_idx_shift);
+ }
+ }
+
+ if ((slice_type == SLICE_TYPE_P) ||
+ (slice_type == SLICE_TYPE_B)) {
+ BEGIN_BCS_BATCH(batch, 10);
+ OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
+ OUT_BCS_BATCH(batch, 0); // L0
+ OUT_BCS_BATCH(batch, fwd_ref_entry);
+
+ for (i = 0; i < 7; i++) {
+ OUT_BCS_BATCH(batch, 0x80808080);
+ }
+
+ ADVANCE_BCS_BATCH(batch);
+ }
+
+ if (slice_type == SLICE_TYPE_B) {
+ BEGIN_BCS_BATCH(batch, 10);
+ OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
+ OUT_BCS_BATCH(batch, 1); //Select L1
+ OUT_BCS_BATCH(batch, bwd_ref_entry); //max 4 reference allowed
+ for(i = 0; i < 7; i++) {
+ OUT_BCS_BATCH(batch, 0x80808080);
+ }
+ ADVANCE_BCS_BATCH(batch);
+ }
+}
+
+static void
+gen9_mfc_avc_weightoffset_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncPictureParameterBufferH264 *pic_param,
+ VAEncSliceParameterBufferH264 *slice_param,
+ struct intel_batchbuffer *batch)
+{
+ int i, slice_type;
+ short weightoffsets[32 * 6];
+
+ slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+
+ if (slice_type == SLICE_TYPE_P &&
+ pic_param->pic_fields.bits.weighted_pred_flag == 1) {
+ memset(weightoffsets,0,32*6 * sizeof(short));
+ for (i = 0; i < 32; i++) {
+ weightoffsets[i * 6 + 0] = slice_param->luma_weight_l0[i];
+ weightoffsets[i * 6 + 1] = slice_param->luma_offset_l0[i];
+ weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l0[i][0];
+ weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l0[i][0];
+ weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l0[i][1];
+ weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l0[i][1];
+ }
+
+ BEGIN_BCS_BATCH(batch, 98);
+ OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
+
+ ADVANCE_BCS_BATCH(batch);
+ }
+
+ if (slice_type == SLICE_TYPE_B &&
+ (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
+ memset(weightoffsets,0,32*6 * sizeof(short));
+ for (i = 0; i < 32; i++) {
+ weightoffsets[i * 6 + 0] = slice_param->luma_weight_l0[i];
+ weightoffsets[i * 6 + 1] = slice_param->luma_offset_l0[i];
+ weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l0[i][0];
+ weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l0[i][0];
+ weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l0[i][1];
+ weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l0[i][1];
+ }
+
+ BEGIN_BCS_BATCH(batch, 98);
+ OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
+ ADVANCE_BCS_BATCH(batch);
+
+ memset(weightoffsets,0,32*6 * sizeof(short));
+ for (i = 0; i < 32; i++) {
+ weightoffsets[i * 6 + 0] = slice_param->luma_weight_l1[i];
+ weightoffsets[i * 6 + 1] = slice_param->luma_offset_l1[i];
+ weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l1[i][0];
+ weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l1[i][0];
+ weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l1[i][1];
+ weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l1[i][1];
+ }
+
+ BEGIN_BCS_BATCH(batch, 98);
+ OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
+ OUT_BCS_BATCH(batch, 1);
+ intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
+ ADVANCE_BCS_BATCH(batch);
+ }
+}
+
+static void
+gen9_mfc_avc_single_slice(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ VAEncSliceParameterBufferH264 *next_slice_param,
+ int slice_index)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct intel_batchbuffer *slice_batch = avc_ctx->pres_slice_batch_buffer_2nd_level;
+ VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+ struct gpe_mi_batch_buffer_start_parameter second_level_batch;
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+
+ unsigned int slice_offset = 0;
+
+ if(generic_state->curr_pak_pass == 0)
+ {
+ slice_offset = intel_batchbuffer_used_size(slice_batch);
+ avc_state->slice_batch_offset[slice_index] = slice_offset;
+ gen9_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context, slice_param,slice_batch);
+ gen9_mfc_avc_weightoffset_state(ctx,
+ encode_state,
+ encoder_context,
+ pic_param,
+ slice_param,
+ slice_batch);
+ gen9_mfc_avc_slice_state(ctx,
+ encode_state,
+ encoder_context,
+ pic_param,
+ slice_param,
+ next_slice_param,
+ slice_batch);
+ gen9_mfc_avc_inset_headers(ctx,
+ encode_state,
+ encoder_context,
+ slice_param,
+ slice_index,
+ slice_batch);
+
+ BEGIN_BCS_BATCH(slice_batch, 2);
+ OUT_BCS_BATCH(slice_batch, 0);
+ OUT_BCS_BATCH(slice_batch, MI_BATCH_BUFFER_END);
+ ADVANCE_BCS_BATCH(slice_batch);
+
+ }else
+ {
+ slice_offset = avc_state->slice_batch_offset[slice_index];
+ }
+ /* insert slice as second levle.*/
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ second_level_batch.is_second_level = 1; /* Must be the second level batch buffer */
+ second_level_batch.offset = slice_offset;
+ second_level_batch.bo = slice_batch->buffer;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
+
+ /* insert mb code as second levle.*/
+ obj_surface = encode_state->reconstructed_object;
+ assert(obj_surface->private_data);
+ avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
+
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ second_level_batch.is_second_level = 1; /* Must be the second level batch buffer */
+ second_level_batch.offset = slice_param->macroblock_address * 16 * 4;
+ second_level_batch.bo = avc_priv_surface->res_mb_code_surface.bo;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
+
+}
+
+static void
+gen9_avc_pak_slice_level(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct gpe_mi_flush_dw_parameter mi_flush_dw_params;
+ VAEncSliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
+ int i, j;
+ int slice_index = 0;
+ int is_frame_level = 1; /* TODO: check it for SKL,now single slice per frame */
+ int has_tail = 0; /* TODO: check it later */
+
+ for (j = 0; j < encode_state->num_slice_params_ext; j++) {
+ slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
+
+ if (j == encode_state->num_slice_params_ext - 1)
+ next_slice_group_param = NULL;
+ else
+ next_slice_group_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j + 1]->buffer;
+
+ for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) {
+ if (i < encode_state->slice_params_ext[j]->num_elements - 1)
+ next_slice_param = slice_param + 1;
+ else
+ next_slice_param = next_slice_group_param;
+
+ gen9_mfc_avc_single_slice(ctx,
+ encode_state,
+ encoder_context,
+ slice_param,
+ next_slice_param,
+ slice_index);
+ slice_param++;
+ slice_index++;
+
+ if (is_frame_level)
+ break;
+ else {
+ /* TODO: remove assert(0) and add other commands here */
+ assert(0);
+ }
+ }
+
+ if (is_frame_level)
+ break;
+ }
+
+ if (has_tail) {
+ /* TODO: insert a tail if required */
+ }
+
+ memset(&mi_flush_dw_params, 0, sizeof(mi_flush_dw_params));
+ mi_flush_dw_params.video_pipeline_cache_invalidate = 1;
+ gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
+}
+static void
+gen9_avc_pak_picture_level(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct gpe_mi_batch_buffer_start_parameter second_level_batch;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ if (generic_state->brc_enabled &&
+ generic_state->curr_pak_pass) {
+ struct gpe_mi_conditional_batch_buffer_end_parameter mi_conditional_batch_buffer_end_params;
+ struct encoder_status_buffer_internal *status_buffer;
+ status_buffer = &(avc_ctx->status_buffer);
+
+ memset(&mi_conditional_batch_buffer_end_params, 0, sizeof(mi_conditional_batch_buffer_end_params));
+ mi_conditional_batch_buffer_end_params.offset = status_buffer->image_status_mask_offset;
+ mi_conditional_batch_buffer_end_params.bo = status_buffer->bo;
+ mi_conditional_batch_buffer_end_params.compare_data = 0;
+ mi_conditional_batch_buffer_end_params.compare_mask_mode_disabled = 0;
+ gen9_gpe_mi_conditional_batch_buffer_end(ctx, batch, &mi_conditional_batch_buffer_end_params);
+ }
+
+ gen9_mfc_avc_pipe_mode_select(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_surface_state(ctx,encoder_context,&(generic_ctx->res_reconstructed_surface),0);
+ gen9_mfc_avc_surface_state(ctx,encoder_context,&(generic_ctx->res_uncompressed_input_surface),4);
+ gen9_mfc_avc_pipe_buf_addr_state(ctx,encoder_context);
+ gen9_mfc_avc_ind_obj_base_addr_state(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_bsp_buf_base_addr_state(ctx,encoder_context);
+
+ if(generic_state->brc_enabled)
+ {
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ if (generic_state->curr_pak_pass == 0) {
+ second_level_batch.offset = 0;
+ } else {
+ second_level_batch.offset = generic_state->curr_pak_pass * INTEL_AVC_IMAGE_STATE_CMD_SIZE;
+ }
+ second_level_batch.is_second_level = 1;
+ second_level_batch.bo = avc_ctx->res_brc_image_state_read_buffer.bo;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
+ }else
+ {
+ /*generate a new image state */
+ gen9_avc_set_image_state_non_brc(ctx,encode_state,encoder_context,&(avc_ctx->res_image_state_batch_buffer_2nd_level));
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ second_level_batch.offset = 0;
+ second_level_batch.is_second_level = 1;
+ second_level_batch.bo = avc_ctx->res_image_state_batch_buffer_2nd_level.bo;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch, &second_level_batch);
+ }
+
+ gen9_mfc_avc_qm_state(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_fqm_state(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_directmode_state(ctx,encoder_context);
+
+}
+
+static void
+gen9_avc_read_mfc_status(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+
+ struct gpe_mi_store_register_mem_parameter mi_store_reg_mem_param;
+ struct gpe_mi_store_data_imm_parameter mi_store_data_imm_param;
+ struct gpe_mi_flush_dw_parameter mi_flush_dw_param;
+ struct encoder_status_buffer_internal *status_buffer;
+
+ status_buffer = &(avc_ctx->status_buffer);
+
+ memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
+ gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
+
+ /* read register and store into status_buffer and pak_statitistic info */
+ memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->bs_byte_count_frame_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
+
+ memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->bs_byte_count_frame_nh_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_nh_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
+
+ memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->mfc_qp_status_count_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->mfc_qp_status_count_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
+
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->image_status_mask_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->image_status_mask_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
+
+ /*update the status in the pak_statistic_surface */
+ mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_reg_mem_param.offset = 0;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
+
+ mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_reg_mem_param.offset = 4;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_nh_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
+
+ memset(&mi_store_data_imm_param, 0, sizeof(mi_store_data_imm_param));
+ mi_store_data_imm_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_data_imm_param.offset = sizeof(unsigned int) * 2;
+ mi_store_data_imm_param.dw0 = (generic_state->curr_pak_pass + 1);
+ gen8_gpe_mi_store_data_imm(ctx, batch, &mi_store_data_imm_param);
+
+ mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_reg_mem_param.offset = sizeof(unsigned int) * (4 + generic_state->curr_pak_pass) ;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->image_status_ctrl_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
+
+ memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
+ gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
+
+ return;
+}
+
+static void
+gen9_avc_pak_brc_prepare(struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ unsigned int rate_control_mode = encoder_context->rate_control_mode;
+
+ switch (rate_control_mode & 0x7f) {
+ case VA_RC_CBR:
+ generic_state->internal_rate_mode = VA_RC_CBR;
+ break;
+
+ case VA_RC_VBR:
+ generic_state->internal_rate_mode = VA_RC_VBR;//AVBR
+ break;
+
+ case VA_RC_CQP:
+ default:
+ generic_state->internal_rate_mode = VA_RC_CQP;
+ break;
+ }
+
+}
+
+static VAStatus
+gen9_avc_pak_pipeline_prepare(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus va_status;
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+
+ struct object_surface *obj_surface;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+ VAEncSliceParameterBufferH264 *slice_param = avc_state->slice_param[0];
+
+ struct gen9_surface_avc *avc_priv_surface;
+ int i, j, enable_avc_ildb = 0;
+ unsigned int allocate_flag = 1;
+ unsigned int size;
+ unsigned int w_mb = generic_state->frame_width_in_mbs;
+ unsigned int h_mb = generic_state->frame_height_in_mbs;
+ struct avc_surface_param surface_param;
+
+ /* update the parameter and check slice parameter */
+ for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb == 0; j++) {
+ assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer);
+ slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
+
+ for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) {
+ assert((slice_param->slice_type == SLICE_TYPE_I) ||
+ (slice_param->slice_type == SLICE_TYPE_SI) ||
+ (slice_param->slice_type == SLICE_TYPE_P) ||
+ (slice_param->slice_type == SLICE_TYPE_SP) ||
+ (slice_param->slice_type == SLICE_TYPE_B));
+
+ if (slice_param->disable_deblocking_filter_idc != 1) {
+ enable_avc_ildb = 1;
+ break;
+ }
+
+ slice_param++;
+ }
+ }
+ avc_state->enable_avc_ildb = enable_avc_ildb;
+
+ /* setup the all surface and buffer for PAK */
+ /* Setup current reconstruct frame */
+ obj_surface = encode_state->reconstructed_object;
+ va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
+
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ memset(&surface_param,0,sizeof(surface_param));
+ surface_param.frame_width = generic_state->frame_width_in_pixel;
+ surface_param.frame_height = generic_state->frame_height_in_pixel;
+ va_status = gen9_avc_init_check_surfaces(ctx,
+ obj_surface,encoder_context,
+ &surface_param);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ /* init the member of avc_priv_surface,frame_store_id,qp_value */
+ {
+ avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = 0;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = 0;
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2]);
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1]);
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2],avc_priv_surface->dmv_top);
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1],avc_priv_surface->dmv_bottom);
+ dri_bo_reference(avc_priv_surface->dmv_top);
+ dri_bo_reference(avc_priv_surface->dmv_bottom);
+ avc_priv_surface->qp_value = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+ avc_priv_surface->frame_store_id = 0;
+ avc_priv_surface->frame_idx = pic_param->CurrPic.frame_idx;
+ avc_priv_surface->top_field_order_cnt = pic_param->CurrPic.TopFieldOrderCnt;
+ avc_priv_surface->is_as_ref = pic_param->pic_fields.bits.reference_pic_flag;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = avc_priv_surface->top_field_order_cnt;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = avc_priv_surface->top_field_order_cnt + 1;
+ }
+ i965_free_gpe_resource(&generic_ctx->res_reconstructed_surface);
+ i965_free_gpe_resource(&avc_ctx->res_post_deblocking_output);
+ i965_free_gpe_resource(&avc_ctx->res_pre_deblocking_output);
+ i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_reconstructed_surface, obj_surface);
+
+
+ if (avc_state->enable_avc_ildb) {
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_post_deblocking_output, obj_surface);
+ } else {
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_pre_deblocking_output, obj_surface);
+ }
+ /* input YUV surface */
+ obj_surface = encode_state->input_yuv_object;
+ va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
+
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ i965_free_gpe_resource(&generic_ctx->res_uncompressed_input_surface);
+ i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_uncompressed_input_surface, obj_surface);
+
+ /* Reference surfaces */
+ for (i = 0; i < ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {
+ i965_free_gpe_resource(&avc_ctx->list_reference_res[i]);
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2]);
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1]);
+ obj_surface = encode_state->reference_objects[i];
+ avc_state->top_field_poc[2*i] = 0;
+ avc_state->top_field_poc[2*i+1] = 0;
+
+ if (obj_surface && obj_surface->bo) {
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->list_reference_res[i], obj_surface);
+
+ /* actually it should be handled when it is reconstructed surface */
+ va_status = gen9_avc_init_check_surfaces(ctx,
+ obj_surface,encoder_context,
+ &surface_param);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2],avc_priv_surface->dmv_top);
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1],avc_priv_surface->dmv_bottom);
+ dri_bo_reference(avc_priv_surface->dmv_top);
+ dri_bo_reference(avc_priv_surface->dmv_bottom);
+ avc_priv_surface->frame_store_id = i;
+ avc_state->top_field_poc[2*i] = avc_priv_surface->top_field_order_cnt;
+ avc_state->top_field_poc[2*i+1] = avc_priv_surface->top_field_order_cnt+1;
+ }else
+ {
+ break;
+ }
+ }
+
+ if (avc_ctx->pres_slice_batch_buffer_2nd_level)
+ intel_batchbuffer_free(avc_ctx->pres_slice_batch_buffer_2nd_level);
+
+ avc_ctx->pres_slice_batch_buffer_2nd_level =
+ intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
+ 4096 *
+ encode_state->num_slice_params_ext);
+ if (!avc_ctx->pres_slice_batch_buffer_2nd_level)
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+
+ for (i = 0;i < MAX_AVC_SLICE_NUM;i++) {
+ avc_state->slice_batch_offset[i] = 0;
+ }
+
+
+ size = w_mb * 64;
+ i965_free_gpe_resource(&avc_ctx->res_intra_row_store_scratch_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_intra_row_store_scratch_buffer,
+ size,
+ "PAK Intra row store scratch buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = w_mb * 4 * 64;
+ i965_free_gpe_resource(&avc_ctx->res_deblocking_filter_row_store_scratch_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_deblocking_filter_row_store_scratch_buffer,
+ size,
+ "PAK Deblocking filter row store scratch buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = w_mb * 2 * 64;
+ i965_free_gpe_resource(&avc_ctx->res_bsd_mpc_row_store_scratch_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_bsd_mpc_row_store_scratch_buffer,
+ size,
+ "PAK BSD/MPC row store scratch buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = w_mb * h_mb * 16;
+ i965_free_gpe_resource(&avc_ctx->res_pak_mb_status_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_pak_mb_status_buffer,
+ size,
+ "PAK MB status buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ return VA_STATUS_SUCCESS;
+
+failed_allocation:
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
+
+static VAStatus
+gen9_avc_encode_picture(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus va_status;
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ va_status = gen9_avc_pak_pipeline_prepare(ctx, encode_state, encoder_context);
+
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+
+ for (generic_state->curr_pak_pass = 0;
+ generic_state->curr_pak_pass < generic_state->num_pak_passes;
+ generic_state->curr_pak_pass++) {
+
+ if (i965->intel.has_bsd2)
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+ else
+ intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
+ intel_batchbuffer_emit_mi_flush(batch);
+
+ if (generic_state->curr_pak_pass == 0) {
+ /* Initialize the avc Image Ctrl reg for the first pass,write 0 to staturs/control register, is it needed in AVC? */
+ struct gpe_mi_load_register_imm_parameter mi_load_reg_imm;
+ struct encoder_status_buffer_internal *status_buffer;
+
+ status_buffer = &(avc_ctx->status_buffer);
+ memset(&mi_load_reg_imm, 0, sizeof(mi_load_reg_imm));
+ mi_load_reg_imm.mmio_offset = status_buffer->image_status_ctrl_reg_offset;
+ mi_load_reg_imm.data = 0;
+ gen8_gpe_mi_load_register_imm(ctx, batch, &mi_load_reg_imm);
+ }
+ gen9_avc_pak_picture_level(ctx, encode_state, encoder_context);
+ gen9_avc_pak_slice_level(ctx, encode_state, encoder_context);
+ intel_batchbuffer_emit_mi_flush(batch);
+
+ gen9_avc_read_mfc_status(ctx, encoder_context);
+ intel_batchbuffer_end_atomic(batch);
+ intel_batchbuffer_flush(batch);
+
+ }
+
+ generic_state->seq_frame_number++;
+ generic_state->total_frame_number++;
+ generic_state->first_frame = 0;
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus
+gen9_avc_pak_pipeline(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus vaStatus;
+
+ switch (profile) {
+ case VAProfileH264ConstrainedBaseline:
+ case VAProfileH264Main:
+ case VAProfileH264High:
+ vaStatus = gen9_avc_encode_picture(ctx, profile, encode_state, encoder_context);
+ break;
+
+ default:
+ vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
+ break;
+ }
+
+ return vaStatus;
+}
+
+static void
+gen9_avc_pak_context_destroy(void * context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+
+ int i = 0;
+
+ if (!pak_context)
+ return;
+
+ // other things
+ i965_free_gpe_resource(&generic_ctx->res_reconstructed_surface);
+ i965_free_gpe_resource(&avc_ctx->res_post_deblocking_output);
+ i965_free_gpe_resource(&avc_ctx->res_pre_deblocking_output);
+ i965_free_gpe_resource(&generic_ctx->res_uncompressed_input_surface);
+
+ i965_free_gpe_resource(&generic_ctx->compressed_bitstream.res);
+ i965_free_gpe_resource(&avc_ctx->res_intra_row_store_scratch_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_deblocking_filter_row_store_scratch_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_bsd_mpc_row_store_scratch_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_pak_mb_status_buffer);
+
+ for(i = 0 ; i < MAX_MFC_AVC_REFERENCE_SURFACES; i++)
+ {
+ i965_free_gpe_resource(&avc_ctx->list_reference_res[i]);
+ }
+
+ for(i = 0 ; i < NUM_MFC_AVC_DMV_BUFFERS; i++)
+ {
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i]);
+ }
+
+ if (avc_ctx->pres_slice_batch_buffer_2nd_level)
+ {
+ intel_batchbuffer_free(avc_ctx->pres_slice_batch_buffer_2nd_level);
+ avc_ctx->pres_slice_batch_buffer_2nd_level = NULL;
+ }
+
+}
+
+static VAStatus
+gen9_avc_get_coded_status(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ struct i965_coded_buffer_segment *coded_buf_seg)
+{
+ struct encoder_status *avc_encode_status;
+
+ if (!encoder_context || !coded_buf_seg)
+ return VA_STATUS_ERROR_INVALID_BUFFER;
+
+ avc_encode_status = (struct encoder_status *)coded_buf_seg->codec_private_data;
+ coded_buf_seg->base.size = avc_encode_status->bs_byte_count_frame;
+
+ return VA_STATUS_SUCCESS;
+}
+
+Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ /* VME & PAK share the same context */
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = NULL;
+ struct generic_encoder_context * generic_ctx = NULL;
+ struct gen9_avc_encoder_context * avc_ctx = NULL;
+ struct generic_enc_codec_state * generic_state = NULL;
+ struct avc_enc_state * avc_state = NULL;
+ struct encoder_status_buffer_internal *status_buffer;
+ uint32_t base_offset = offsetof(struct i965_coded_buffer_segment, codec_private_data);
+
+ vme_context = calloc(1, sizeof(struct encoder_vme_mfc_context));
+ generic_ctx = calloc(1, sizeof(struct generic_encoder_context));
+ avc_ctx = calloc(1, sizeof(struct gen9_avc_encoder_context));
+ generic_state = calloc(1, sizeof(struct generic_enc_codec_state));
+ avc_state = calloc(1, sizeof(struct avc_enc_state));
+
+ if(!vme_context || !generic_ctx || !avc_ctx || !generic_state || !avc_state)
+ goto allocate_structure_failed;
+
+ memset(vme_context,0,sizeof(struct encoder_vme_mfc_context));
+ memset(generic_ctx,0,sizeof(struct generic_encoder_context));
+ memset(avc_ctx,0,sizeof(struct gen9_avc_encoder_context));
+ memset(generic_state,0,sizeof(struct generic_enc_codec_state));
+ memset(avc_state,0,sizeof(struct avc_enc_state));
+
+ encoder_context->vme_context = vme_context;
+ vme_context->generic_enc_ctx = generic_ctx;
+ vme_context->private_enc_ctx = avc_ctx;
+ vme_context->generic_enc_state = generic_state;
+ vme_context->private_enc_state = avc_state;
+
+ if (IS_SKL(i965->intel.device_info)) {
+ generic_ctx->enc_kernel_ptr = (void *)skl_avc_encoder_kernels;
+ generic_ctx->enc_kernel_size = sizeof(skl_avc_encoder_kernels);
+ }
+ else
+ goto allocate_structure_failed;
+
+ /* initialize misc ? */
+ avc_ctx->ctx = ctx;
+ generic_ctx->use_hw_scoreboard = 1;
+ generic_ctx->use_hw_non_stalling_scoreboard = 1;
+
+ /* initialize generic state */
+
+ generic_state->kernel_mode = INTEL_ENC_KERNEL_NORMAL;
+ generic_state->preset = INTEL_PRESET_RT_SPEED;
+ generic_state->seq_frame_number = 0;
+ generic_state->total_frame_number = 0;
+ generic_state->frame_type = 0;
+ generic_state->first_frame = 1;
+
+ generic_state->frame_width_in_pixel = 0;
+ generic_state->frame_height_in_pixel = 0;
+ generic_state->frame_width_in_mbs = 0;
+ generic_state->frame_height_in_mbs = 0;
+ generic_state->frame_width_4x = 0;
+ generic_state->frame_height_4x = 0;
+ generic_state->frame_width_16x = 0;
+ generic_state->frame_height_16x = 0;
+ generic_state->frame_width_32x = 0;
+ generic_state->downscaled_width_4x_in_mb = 0;
+ generic_state->downscaled_height_4x_in_mb = 0;
+ generic_state->downscaled_width_16x_in_mb = 0;
+ generic_state->downscaled_height_16x_in_mb = 0;
+ generic_state->downscaled_width_32x_in_mb = 0;
+ generic_state->downscaled_height_32x_in_mb = 0;
+
+ generic_state->hme_supported = 1;
+ generic_state->b16xme_supported = 1;
+ generic_state->b32xme_supported = 0;
+ generic_state->hme_enabled = 0;
+ generic_state->b16xme_enabled = 0;
+ generic_state->b32xme_enabled = 0;
+ generic_state->brc_distortion_buffer_supported = 1;
+ generic_state->brc_constant_buffer_supported = 0;
+
+
+ generic_state->frame_rate = 30;
+ generic_state->brc_allocated = 0;
+ generic_state->brc_inited = 0;
+ generic_state->brc_need_reset = 0;
+ generic_state->is_low_delay = 0;
+ generic_state->brc_enabled = 0;//default
+ generic_state->internal_rate_mode = 0;
+ generic_state->curr_pak_pass = 0;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ generic_state->is_first_pass = 1;
+ generic_state->is_last_pass = 0;
+ generic_state->mb_brc_enabled = 0; // enable mb brc
+ generic_state->brc_roi_enable = 0;
+ generic_state->brc_dirty_roi_enable = 0;
+ generic_state->skip_frame_enbale = 0;
+
+ generic_state->target_bit_rate = 0;
+ generic_state->max_bit_rate = 0;
+ generic_state->min_bit_rate = 0;
+ generic_state->init_vbv_buffer_fullness_in_bit = 0;
+ generic_state->vbv_buffer_size_in_bit = 0;
+ generic_state->frames_per_100s = 0;
+ generic_state->gop_size = 0;
+ generic_state->gop_ref_distance = 0;
+ generic_state->brc_target_size = 0;
+ generic_state->brc_mode = 0;
+ generic_state->brc_init_current_target_buf_full_in_bits = 0.0;
+ generic_state->brc_init_reset_input_bits_per_frame = 0.0;
+ generic_state->brc_init_reset_buf_size_in_bits = 0;
+ generic_state->brc_init_previous_target_buf_full_in_bits = 0;
+ generic_state->window_size = 0;//default
+ generic_state->target_percentage = 0;
+
+ generic_state->avbr_curracy = 0;
+ generic_state->avbr_convergence = 0;
+
+ generic_state->num_skip_frames = 0;
+ generic_state->size_skip_frames = 0;
+
+ generic_state->num_roi = 0;
+ generic_state->max_delta_qp = 0;
+ generic_state->min_delta_qp = 0;
+
+ if (encoder_context->rate_control_mode != VA_RC_NONE &&
+ encoder_context->rate_control_mode != VA_RC_CQP) {
+ generic_state->brc_enabled = 1;
+ generic_state->brc_distortion_buffer_supported = 1;
+ generic_state->brc_constant_buffer_supported = 1;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ }
+ /*avc state initialization */
+ avc_state->mad_enable = 0;
+ avc_state->mb_disable_skip_map_enable = 0;
+ avc_state->sfd_enable = 1;//default
+ avc_state->sfd_mb_enable = 1;//set it true
+ avc_state->adaptive_search_window_enable = 1;//default
+ avc_state->mb_qp_data_enable = 0;
+ avc_state->intra_refresh_i_enable = 0;
+ avc_state->min_max_qp_enable = 0;
+ avc_state->skip_bias_adjustment_enable = 0;//default,same as skip_bias_adjustment_supporte? no
+
+ //external input
+ avc_state->non_ftq_skip_threshold_lut_input_enable = 0;
+ avc_state->ftq_skip_threshold_lut_input_enable = 0;
+ avc_state->ftq_override = 0;
+
+ avc_state->direct_bias_adjustment_enable = 0;
+ avc_state->global_motion_bias_adjustment_enable = 0;
+ avc_state->disable_sub_mb_partion = 0;
+ avc_state->arbitrary_num_mbs_in_slice = 0;
+ avc_state->adaptive_transform_decision_enable = 0;//default
+ avc_state->skip_check_disable = 0;
+ avc_state->tq_enable = 0;
+ avc_state->enable_avc_ildb = 0;
+ avc_state->mbaff_flag = 0;
+ avc_state->enable_force_skip = 1;//default
+ avc_state->rc_panic_enable = 1;//default
+ avc_state->suppress_recon_enable = 1;//default
+
+ avc_state->ref_pic_select_list_supported = 1;
+ avc_state->mb_brc_supported = 1;//?,default
+ avc_state->multi_pre_enable = 1;//default
+ avc_state->ftq_enable = 1;//default
+ avc_state->caf_supported = 1; //default
+ avc_state->caf_enable = 0;
+ avc_state->caf_disable_hd = 1;//default
+ avc_state->skip_bias_adjustment_supported = 1;//default
+
+ avc_state->adaptive_intra_scaling_enable = 1;//default
+ avc_state->old_mode_cost_enable = 0;//default
+ avc_state->multi_ref_qp_enable = 1;//default
+ avc_state->weighted_ref_l0_enable = 1;//default
+ avc_state->weighted_ref_l1_enable = 1;//default
+ avc_state->weighted_prediction_supported = 0;
+ avc_state->brc_split_enable = 0;
+ avc_state->slice_level_report_supported = 0;
+
+ avc_state->fbr_bypass_enable = 1;//default
+ avc_state->field_scaling_output_interleaved = 0;
+ avc_state->mb_variance_output_enable = 0;
+ avc_state->mb_pixel_average_output_enable = 0;
+ avc_state->rolling_intra_refresh_enable = 0;// same as intra_refresh_i_enable?
+ avc_state->mbenc_curbe_set_in_brc_update = 0;
+ avc_state->rounding_inter_enable = 1; //default
+ avc_state->adaptive_rounding_inter_enable = 1;//default
+
+ avc_state->mbenc_i_frame_dist_in_use = 0;
+ avc_state->mb_status_supported = 1; //set in intialization for gen9
+ avc_state->mb_status_enable = 0;
+ avc_state->mb_vproc_stats_enable = 0;
+ avc_state->flatness_check_enable = 0;
+ avc_state->flatness_check_supported = 1;//default
+ avc_state->block_based_skip_enable = 0;
+ avc_state->use_widi_mbenc_kernel = 0;
+ avc_state->kernel_trellis_enable = 0;
+ avc_state->generic_reserved = 0;
+
+ avc_state->rounding_value = 0;
+ avc_state->rounding_inter_p = 255;//default
+ avc_state->rounding_inter_b = 255; //default
+ avc_state->rounding_inter_b_ref = 255; //default
+ avc_state->min_qp_i = INTEL_AVC_MIN_QP;
+ avc_state->min_qp_p = INTEL_AVC_MIN_QP;
+ avc_state->min_qp_b = INTEL_AVC_MIN_QP;
+ avc_state->max_qp_i = INTEL_AVC_MAX_QP;
+ avc_state->max_qp_p = INTEL_AVC_MAX_QP;
+ avc_state->max_qp_b = INTEL_AVC_MAX_QP;
+
+ memset(avc_state->non_ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
+ memset(avc_state->ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
+ memset(avc_state->lamda_value_lut,0,52*2*sizeof(uint8_t));
+
+ avc_state->intra_refresh_qp_threshold = 0;
+ avc_state->trellis_flag = 0;
+ avc_state->hme_mv_cost_scaling_factor = 0;
+ avc_state->slice_height = 1;
+ avc_state->slice_num = 1;
+ memset(avc_state->dist_scale_factor_list0,0,32*sizeof(uint32_t));
+ avc_state->bi_weight = 0;
+ avc_state->brc_const_data_surface_width = 64;
+ avc_state->brc_const_data_surface_height = 44;
+
+ avc_state->num_refs[0] = 0;
+ avc_state->num_refs[1] = 0;
+ memset(avc_state->list_ref_idx,0,32*2*sizeof(uint32_t));
+ memset(avc_state->top_field_poc,0,NUM_MFC_AVC_DMV_BUFFERS*sizeof(int32_t));
+ avc_state->tq_rounding = 0;
+ avc_state->zero_mv_threshold = 0;
+ avc_state->slice_second_levle_batch_buffer_in_use = 0;
+
+ //1. seq/pic/slice
+
+ /* the definition of status buffer offset for Encoder */
+
+ status_buffer = &avc_ctx->status_buffer;
+ memset(status_buffer, 0,sizeof(struct encoder_status_buffer_internal));
+
+ status_buffer->base_offset = base_offset;
+ status_buffer->bs_byte_count_frame_offset = base_offset + offsetof(struct encoder_status, bs_byte_count_frame);
+ status_buffer->bs_byte_count_frame_nh_offset = base_offset + offsetof(struct encoder_status, bs_byte_count_frame_nh);
+ status_buffer->image_status_mask_offset = base_offset + offsetof(struct encoder_status, image_status_mask);
+ status_buffer->image_status_ctrl_offset = base_offset + offsetof(struct encoder_status, image_status_ctrl);
+ status_buffer->mfc_qp_status_count_offset = base_offset + offsetof(struct encoder_status, mfc_qp_status_count);
+ status_buffer->media_index_offset = base_offset + offsetof(struct encoder_status, media_index);
+
+ status_buffer->status_buffer_size = sizeof(struct encoder_status);
+ status_buffer->bs_byte_count_frame_reg_offset = MFC_BITSTREAM_BYTECOUNT_FRAME_REG;
+ status_buffer->bs_byte_count_frame_nh_reg_offset = MFC_BITSTREAM_BYTECOUNT_SLICE_REG;
+ status_buffer->image_status_mask_reg_offset = MFC_IMAGE_STATUS_MASK_REG;
+ status_buffer->image_status_ctrl_reg_offset = MFC_IMAGE_STATUS_CTRL_REG;
+ status_buffer->mfc_qp_status_count_reg_offset = MFC_QP_STATUS_COUNT_REG;
+
+ gen9_avc_kernel_init(ctx,encoder_context);
+ encoder_context->vme_context = vme_context;
+ encoder_context->vme_pipeline = gen9_avc_vme_pipeline;
+ encoder_context->vme_context_destroy = gen9_avc_vme_context_destroy;
+
+ return true;
+
+allocate_structure_failed:
+
+ if(vme_context)
+ free(vme_context);
+
+ if(generic_ctx)
+ free(generic_ctx);
+
+ if(avc_ctx)
+ free(avc_ctx);
+
+ if(generic_state)
+ free(generic_state);
+
+ if(avc_state)
+ free(avc_state);
+
+ return false;
+}
+
+Bool
+gen9_avc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ /* VME & PAK share the same context */
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+
+ if (!pak_context)
+ return false;
+
+ encoder_context->mfc_context = pak_context;
+ encoder_context->mfc_context_destroy = gen9_avc_pak_context_destroy;
+ encoder_context->mfc_pipeline = gen9_avc_pak_pipeline;
+ encoder_context->mfc_brc_prepare = gen9_avc_pak_brc_prepare;
+ encoder_context->get_status = gen9_avc_get_coded_status;
+ return true;
+}
--
2.7.4
Zhao Yakui
2017-01-17 02:47:14 UTC
Permalink
Post by Pengfei Qu
add MFX command for AVC encoder
add MFX Picture slice level command init for AVC
add MFX pipeline init prepare run for AVC encode
add VME/MFX context init for AVC encoder
Please see the inline comment.
Post by Pengfei Qu
---
src/gen9_avc_encoder.c | 1887 +++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 1886 insertions(+), 1 deletion(-)
diff --git a/src/gen9_avc_encoder.c b/src/gen9_avc_encoder.c
index 5caa9f4..a7545f1 100755
--- a/src/gen9_avc_encoder.c
+++ b/src/gen9_avc_encoder.c
@@ -5742,4 +5742,1889 @@ gen9_avc_kernel_init(VADriverContextP ctx,
generic_ctx->pfn_send_brc_mb_update_surface = gen9_avc_send_surface_brc_mb_update;
generic_ctx->pfn_send_sfd_surface = gen9_avc_send_surface_sfd;
generic_ctx->pfn_send_wp_surface = gen9_avc_send_surface_wp;
-}
\ No newline at end of file
+}
+
+/*
+PAK pipeline related function
+*/
+extern int
+intel_avc_enc_slice_type_fixup(int slice_type);
+
+static void
+gen9_mfc_avc_pipe_mode_select(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 5);
+
+ OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
+ OUT_BCS_BATCH(batch,
+ (0<< 29) |
+ (MFX_LONG_MODE<< 17) | /* Must be long format for encoder */
+ (MFD_MODE_VLD<< 15) |
+ (0<< 13) | /* VDEnc mode is 1*/
+ ((generic_state->curr_pak_pass != (generic_state->num_pak_passes -1))<< 10) | /* Stream-Out Enable */
+ ((!!avc_ctx->res_post_deblocking_output.bo)<< 9) | /* Post Deblocking Output */
+ ((!!avc_ctx->res_pre_deblocking_output.bo)<< 8) | /* Pre Deblocking Output */
+ (0<< 7) | /* Scaled surface enable */
+ (0<< 6) | /* Frame statistics stream out enable, always '1' in VDEnc mode */
+ (0<< 5) | /* not in stitch mode */
+ (1<< 4) | /* encoding mode */
+ (MFX_FORMAT_AVC<< 0));
+ OUT_BCS_BATCH(batch,
+ (0<< 7) | /* expand NOA bus flag */
+ (0<< 6) | /* disable slice-level clock gating */
+ (0<< 5) | /* disable clock gating for NOA */
+ (0<< 4) | /* terminate if AVC motion and POC table error occurs */
+ (0<< 3) | /* terminate if AVC mbdata error occurs */
+ (0<< 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
+ (0<< 1) |
+ (0<< 0));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_surface_state(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ struct i965_gpe_resource *gpe_resource,
+ int id)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 6);
+
+ OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
+ OUT_BCS_BATCH(batch, id);
+ OUT_BCS_BATCH(batch,
+ ((gpe_resource->height - 1)<< 18) |
+ ((gpe_resource->width - 1)<< 4));
+ OUT_BCS_BATCH(batch,
+ (MFX_SURFACE_PLANAR_420_8<< 28) | /* 420 planar YUV surface */
+ (1<< 27) | /* must be 1 for interleave U/V, hardware requirement */
+ ((gpe_resource->pitch - 1)<< 3) | /* pitch */
+ (0<< 2) | /* must be 0 for interleave U/V */
+ (1<< 1) | /* must be tiled */
+ (I965_TILEWALK_YMAJOR<< 0)); /* tile walk, TILEWALK_YMAJOR */
+ OUT_BCS_BATCH(batch,
+ (0<< 16) | /* must be 0 for interleave U/V */
+ (gpe_resource->y_cb_offset)); /* y offset for U(cb) */
+ OUT_BCS_BATCH(batch,
+ (0<< 16) | /* must be 0 for interleave U/V */
+ (gpe_resource->y_cb_offset)); /* y offset for U(cb) */
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ int i;
+
+ BEGIN_BCS_BATCH(batch, 65);
+
+ OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (65 - 2));
+
+ /* the DW1-3 is for pre_deblocking */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_pre_deblocking_output.bo, 1, 0, 0);
+
+ /* the DW4-6 is for the post_deblocking */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_post_deblocking_output.bo, 1, 0, 0);
+
+ /* the DW7-9 is for the uncompressed_picture */
+ OUT_BUFFER_3DW(batch, generic_ctx->res_uncompressed_input_surface.bo, 1, 0, 0);
+
+ /* the DW10-12 is for PAK information (write) */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, 0);//?
+
+ /* the DW13-15 is for the intra_row_store_scratch */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_intra_row_store_scratch_buffer.bo, 1, 0, 0);
+
+ /* the DW16-18 is for the deblocking filter */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_deblocking_filter_row_store_scratch_buffer.bo, 1, 0, 0);
+
+ /* the DW 19-50 is for Reference pictures*/
+ for (i = 0; i< ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {
+ OUT_BUFFER_2DW(batch, avc_ctx->list_reference_res[i].bo, 1, 0);
+ }
+
+ /* DW 51, reference picture attributes */
+ OUT_BCS_BATCH(batch, 0);
+
+ /* The DW 52-54 is for PAK information (read) */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, 0);
+
+ /* the DW 55-57 is the ILDB buffer */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ /* the DW 58-60 is the second ILDB buffer */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ /* DW 61, memory compress enable& mode */
+ OUT_BCS_BATCH(batch, 0);
+
+ /* the DW 62-64 is the buffer */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_ind_obj_base_addr_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+ unsigned int size = 0;
+ unsigned int w_mb = generic_state->frame_width_in_mbs;
+ unsigned int h_mb = generic_state->frame_height_in_mbs;
+
+ obj_surface = encode_state->reconstructed_object;
+
+ if (!obj_surface || !obj_surface->private_data)
+ return;
+ avc_priv_surface = obj_surface->private_data;
+
+ BEGIN_BCS_BATCH(batch, 26);
+
+ OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
+ /* The DW1-5 is for the MFX indirect bistream offset, ignore for VDEnc mode */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+ OUT_BUFFER_2DW(batch, NULL, 0, 0);
+
+ /* the DW6-10 is for MFX Indirect MV Object Base Address, ignore for VDEnc mode */
+ size = w_mb * h_mb * 32 * 4;
+ OUT_BUFFER_3DW(batch,
+ avc_priv_surface->res_mv_data_surface.bo,
+ 1,
+ 0,
+ 0);
+ OUT_BUFFER_2DW(batch,
+ avc_priv_surface->res_mv_data_surface.bo,
+ 1,
+ ALIGN(size,0x1000));
+
+ /* The DW11-15 is for MFX IT-COFF. Not used on encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+ OUT_BUFFER_2DW(batch, NULL, 0, 0);
+
+ /* The DW16-20 is for MFX indirect DBLK. Not used on encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+ OUT_BUFFER_2DW(batch, NULL, 0, 0);
+
+ /* The DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder
+ * Note: an offset is specified in MFX_AVC_SLICE_STATE
+ */
+ OUT_BUFFER_3DW(batch,
+ generic_ctx->compressed_bitstream.res.bo,
+ 1,
+ 0,
+ 0);
+ OUT_BUFFER_2DW(batch,
+ generic_ctx->compressed_bitstream.res.bo,
+ 1,
+ generic_ctx->compressed_bitstream.end_offset);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 10);
+
+ OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
+
+ /* The DW1-3 is for bsd/mpc row store scratch buffer */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_bsd_mpc_row_store_scratch_buffer.bo, 1, 0, 0);
+
+ /* The DW4-6 is for MPR Row Store Scratch Buffer Base Address, ignore for encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ /* The DW7-9 is for Bitplane Read Buffer Base Address, ignore for encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_directmode_state(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+
+ int i;
+
+ BEGIN_BCS_BATCH(batch, 71);
+
+ OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
+
+ /* Reference frames and Current frames */
+ /* the DW1-32 is for the direct MV for reference */
+ for(i = 0; i< NUM_MFC_AVC_DMV_BUFFERS - 2; i += 2) {
+ if ( avc_ctx->res_direct_mv_buffersr[i].bo != NULL) {
+ OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[i].bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+ } else {
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ }
+ }
+
+ OUT_BCS_BATCH(batch, 0);
+
+ /* the DW34-36 is the MV for the current reference */
+ OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS - 2].bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+
+ OUT_BCS_BATCH(batch, 0);
+
+ /* POL list */
+ for(i = 0; i< 32; i++) {
+ OUT_BCS_BATCH(batch, avc_state->top_field_poc[i]);
+ }
+ OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 2]);
+ OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 1]);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_qm_state(VADriverContextP ctx,
+ int qm_type,
+ const unsigned int *qm,
+ int qm_length,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ unsigned int qm_buffer[16];
+
+ assert(qm_length<= 16);
+ assert(sizeof(*qm) == 4);
+ memset(qm_buffer,0,16*4);
+ memcpy(qm_buffer, qm, qm_length * 4);
+
+ BEGIN_BCS_BATCH(batch, 18);
+ OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
+ OUT_BCS_BATCH(batch, qm_type<< 0);
+ intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_qm_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ VAEncSequenceParameterBufferH264 *seq_param = avc_state->seq_param;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+
+ /* TODO: add support for non flat matrix */
+ const unsigned int *qm_4x4_intra;
+ const unsigned int *qm_4x4_inter;
+ const unsigned int *qm_8x8_intra;
+ const unsigned int *qm_8x8_inter;
+
+ if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag
+&& !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {
+ qm_4x4_intra = qm_4x4_inter = qm_8x8_intra = qm_8x8_inter = qm_flat;
+ } else {
+ VAIQMatrixBufferH264 *qm;
+ assert(encode_state->q_matrix&& encode_state->q_matrix->buffer);
+ qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
+ qm_4x4_intra = (unsigned int *)qm->ScalingList4x4[0];
+ qm_4x4_inter = (unsigned int *)qm->ScalingList4x4[3];
+ qm_8x8_intra = (unsigned int *)qm->ScalingList8x8[0];
+ qm_8x8_inter = (unsigned int *)qm->ScalingList8x8[1];
+ }
+
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm_4x4_intra, 12, encoder_context);
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm_4x4_inter, 12, encoder_context);
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm_8x8_intra, 16, encoder_context);
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm_8x8_inter, 16, encoder_context);
+}
+
+static void
+gen9_mfc_fqm_state(VADriverContextP ctx,
+ int fqm_type,
+ const unsigned int *fqm,
+ int fqm_length,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ unsigned int fqm_buffer[32];
+
+ assert(fqm_length<= 32);
+ assert(sizeof(*fqm) == 4);
+ memset(fqm_buffer,0,32*4);
+ memcpy(fqm_buffer, fqm, fqm_length * 4);
+
+ BEGIN_BCS_BATCH(batch, 34);
+ OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
+ OUT_BCS_BATCH(batch, fqm_type<< 0);
+ intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_fill_fqm(uint8_t *qm, uint16_t *fqm, int len)
+{
+ int i, j;
+ for (i = 0; i< len; i++)
+ for (j = 0; j< len; j++)
+ fqm[i * len + j] = (1<< 16) / qm[j * len + i];
+}
+
+static void
+gen9_mfc_avc_fqm_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ /* TODO: add support for non flat matrix */
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ VAEncSequenceParameterBufferH264 *seq_param = avc_state->seq_param;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+
+ if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag
+&& !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm_flat, 24, encoder_context);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm_flat, 24, encoder_context);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm_flat, 32, encoder_context);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm_flat, 32, encoder_context);
+ } else {
+ int i;
+ uint32_t fqm[32];
+ VAIQMatrixBufferH264 *qm;
+ assert(encode_state->q_matrix&& encode_state->q_matrix->buffer);
+ qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
+
+ for (i = 0; i< 3; i++)
+ gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * i, 4);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm, 24, encoder_context);
+
+ for (i = 3; i< 6; i++)
+ gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * (i - 3), 4);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm, 24, encoder_context);
+
+ gen9_mfc_fill_fqm(qm->ScalingList8x8[0], (uint16_t *)fqm, 8);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm, 32, encoder_context);
+
+ gen9_mfc_fill_fqm(qm->ScalingList8x8[1], (uint16_t *)fqm, 8);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm, 32, encoder_context);
+ }
+}
+
+static void
+gen9_mfc_avc_insert_object(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
+ int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
+ int slice_header_indicator,
+ struct intel_batchbuffer *batch)
+{
+ if (data_bits_in_last_dw == 0)
+ data_bits_in_last_dw = 32;
+
+ BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
+
+ OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws));
+ OUT_BCS_BATCH(batch,
+ (0<< 16) | /* always start at offset 0 */
+ (slice_header_indicator<< 14) |
+ (data_bits_in_last_dw<< 8) |
+ (skip_emul_byte_count<< 4) |
+ (!!emulation_flag<< 3) |
+ ((!!is_last_header)<< 2) |
+ ((!!is_end_of_slice)<< 1) |
+ (0<< 0)); /* TODO: check this flag */
+ intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_insert_slice_packed_data(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int slice_index,
+ struct intel_batchbuffer *batch)
+{
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int length_in_bits;
+ unsigned int *header_data = NULL;
+ int count, i, start_index;
+ int slice_header_index;
+
+ if (encode_state->slice_header_index[slice_index] == 0)
+ slice_header_index = -1;
+ else
+ slice_header_index = (encode_state->slice_header_index[slice_index]& SLICE_PACKED_DATA_INDEX_MASK);
+
+ count = encode_state->slice_rawdata_count[slice_index];
+ start_index = (encode_state->slice_rawdata_index[slice_index]& SLICE_PACKED_DATA_INDEX_MASK);
+
+ for (i = 0; i< count; i++) {
+ unsigned int skip_emul_byte_cnt;
+
+ header_data = (unsigned int *)encode_state->packed_header_data_ext[start_index + i]->buffer;
+
+ param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[start_index + i]->buffer);
+
+ /* skip the slice header packed data type as it is lastly inserted */
+ if (param->type == VAEncPackedHeaderSlice)
+ continue;
+
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+
+ /* as the slice header is still required, the last header flag is set to
+ * zero.
+ */
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ }
+
+ if (slice_header_index == -1) {
+ VAEncSequenceParameterBufferH264 *seq_param = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+ VAEncSliceParameterBufferH264 *slice_params = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
+ unsigned char *slice_header = NULL;
+ int slice_header_length_in_bits = 0;
+
+ /* No slice header data is passed. And the driver needs to generate it */
+ /* For the Normal H264 */
+ slice_header_length_in_bits = build_avc_slice_header(seq_param,
+ pic_param,
+ slice_params,
+&slice_header);
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ (unsigned int *)slice_header,
+ ALIGN(slice_header_length_in_bits, 32)>> 5,
+ slice_header_length_in_bits& 0x1f,
+ 5, /* first 5 bytes are start code + nal unit type */
+ 1, 0, 1,
+ 1,
+ batch);
+
+ free(slice_header);
+ } else {
+ unsigned int skip_emul_byte_cnt;
+
+ header_data = (unsigned int *)encode_state->packed_header_data_ext[slice_header_index]->buffer;
+
+ param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[slice_header_index]->buffer);
+ length_in_bits = param->bit_length;
+
+ /* as the slice header is the last header data for one slice,
+ * the last header flag is set to one.
+ */
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 1,
+ 0,
+ !param->has_emulation_bytes,
+ 1,
+ batch);
+ }
+
+ return;
+}
+
+static void
+gen9_mfc_avc_inset_headers(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ int slice_index,
+ struct intel_batchbuffer *batch)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SPS);
+ unsigned int internal_rate_mode = generic_state->internal_rate_mode;
+ unsigned int skip_emul_byte_cnt;
+
+ if (slice_index == 0) {
+ if (encode_state->packed_header_data[idx]) {
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
+ unsigned int length_in_bits;
+
+ assert(encode_state->packed_header_param[idx]);
+ param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ }
+
+ idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_PPS);
+
+ if (encode_state->packed_header_data[idx]) {
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
+ unsigned int length_in_bits;
+
+ assert(encode_state->packed_header_param[idx]);
+ param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ }
+
+ idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SEI);
+
+ if (encode_state->packed_header_data[idx]) {
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
+ unsigned int length_in_bits;
+
+ assert(encode_state->packed_header_param[idx]);
+ param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ } else if (internal_rate_mode == VA_RC_CBR) {
+ /* TODO: insert others */
+ }
+ }
+
+ gen9_mfc_avc_insert_slice_packed_data(ctx,
+ encode_state,
+ encoder_context,
+ slice_index,
+ batch);
+}
+
+static void
+gen9_mfc_avc_slice_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncPictureParameterBufferH264 *pic_param,
+ VAEncSliceParameterBufferH264 *slice_param,
+ VAEncSliceParameterBufferH264 *next_slice_param,
+ struct intel_batchbuffer *batch)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
+ unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
+ unsigned char correct[6], grow, shrink;
+ int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
+ int max_qp_n, max_qp_p;
+ int i;
+ int weighted_pred_idc = 0;
+ int num_ref_l0 = 0, num_ref_l1 = 0;
+ int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+ int slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+ unsigned int rc_panic_enable = 0;
+ unsigned int rate_control_counter_enable = 0;
+ unsigned int rounding_value = 0;
+ unsigned int rounding_inter_enable = 0;
+
+ //check the inter rounding
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ if(avc_state->rounding_inter_p == AVC_INVALID_ROUNDING_VALUE)
+ {
+ if(avc_state->adaptive_rounding_inter_enable&& !(generic_state->brc_enabled))
+ {
+ if(generic_state->gop_ref_distance == 1)
+ avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p_without_b[slice_qp];
+ else
+ avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p[slice_qp];
+ }
+ else
+ {
+ avc_state->rounding_value = gen9_avc_inter_rounding_p[generic_state->preset];
+ }
+
+ }else
+ {
+ avc_state->rounding_value = avc_state->rounding_inter_p;
+ }
+ }else if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ if(pic_param->pic_fields.bits.reference_pic_flag)
+ {
+ if(avc_state->rounding_inter_b_ref == AVC_INVALID_ROUNDING_VALUE)
+ avc_state->rounding_value = gen9_avc_inter_rounding_b_ref[generic_state->preset];
+ else
+ avc_state->rounding_value = avc_state->rounding_inter_b_ref;
+ }
+ else
+ {
+ if(avc_state->rounding_inter_b == AVC_INVALID_ROUNDING_VALUE)
+ {
+ if(avc_state->adaptive_rounding_inter_enable&& !(generic_state->brc_enabled))
+ avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_b[slice_qp];
+ else
+ avc_state->rounding_value = gen9_avc_inter_rounding_b[generic_state->preset];
+ }else
+ {
+ avc_state->rounding_value = avc_state->rounding_inter_b;
+ }
+ }
+ }
+
+ slice_hor_pos = slice_param->macroblock_address % generic_state->frame_width_in_mbs;
+ slice_ver_pos = slice_param->macroblock_address / generic_state->frame_height_in_mbs;
+
+ if (next_slice_param) {
+ next_slice_hor_pos = next_slice_param->macroblock_address % generic_state->frame_width_in_mbs;
+ next_slice_ver_pos = next_slice_param->macroblock_address / generic_state->frame_height_in_mbs;
+ } else {
+ next_slice_hor_pos = 0;
+ next_slice_ver_pos = generic_state->frame_height_in_mbs;
+ }
+
+ if (slice_type == SLICE_TYPE_I) {
+ luma_log2_weight_denom = 0;
+ chroma_log2_weight_denom = 0;
+ } else if (slice_type == SLICE_TYPE_P) {
+ weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
+ num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
+ rounding_inter_enable = avc_state->rounding_inter_enable;
+ rounding_value = avc_state->rounding_value;
+
+ if (slice_param->num_ref_idx_active_override_flag)
+ num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
+ } else if (slice_type == SLICE_TYPE_B) {
+ weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
+ num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
+ num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
+ rounding_inter_enable = avc_state->rounding_inter_enable;
+ rounding_value = avc_state->rounding_value;
+
+ if (slice_param->num_ref_idx_active_override_flag) {
+ num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
+ num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
+ }
+
+ if (weighted_pred_idc == 2) {
+ /* 8.4.3 - Derivation process for prediction weights (8-279) */
+ luma_log2_weight_denom = 5;
+ chroma_log2_weight_denom = 5;
+ }
+ }
+
+ max_qp_n = 0; /* TODO: update it */
+ max_qp_p = 0; /* TODO: update it */
+ grow = 0; /* TODO: update it */
+ shrink = 0; /* TODO: update it */
+
+ rate_control_counter_enable = (generic_state->brc_enabled&& (generic_state->curr_pak_pass != 0));
+ rc_panic_enable = (avc_state->rc_panic_enable&&
+ (!avc_state->min_max_qp_enable)&&
+ (encoder_context->rate_control_mode != VA_RC_CQP)&&
+ (generic_state->curr_pak_pass == (generic_state->num_pak_passes - 1)));
+
+ for (i = 0; i< 6; i++)
+ correct[i] = 0; /* TODO: update it */
+
+ BEGIN_BCS_BATCH(batch, 11);
+
+ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
+ OUT_BCS_BATCH(batch, slice_type);
+ OUT_BCS_BATCH(batch,
+ (num_ref_l1<< 24) |
+ (num_ref_l0<< 16) |
+ (chroma_log2_weight_denom<< 8) |
+ (luma_log2_weight_denom<< 0));
+ OUT_BCS_BATCH(batch,
+ (weighted_pred_idc<< 30) |
+ (((slice_type == SLICE_TYPE_B)?slice_param->direct_spatial_mv_pred_flag:0)<< 29) |
+ (slice_param->disable_deblocking_filter_idc<< 27) |
+ (slice_param->cabac_init_idc<< 24) |
+ (slice_qp<< 16) |
+ ((slice_param->slice_beta_offset_div2& 0xf)<< 8) |
+ ((slice_param->slice_alpha_c0_offset_div2& 0xf)<< 0));
+
+ OUT_BCS_BATCH(batch,
+ slice_ver_pos<< 24 |
+ slice_hor_pos<< 16 |
+ slice_param->macroblock_address);
+ OUT_BCS_BATCH(batch,
+ next_slice_ver_pos<< 16 |
+ next_slice_hor_pos);
+
+ OUT_BCS_BATCH(batch,
+ (rate_control_counter_enable<< 31) | /* TODO: ignore it for VDENC ??? */
+ (1<< 30) | /* ResetRateControlCounter */
+ (2<< 28) | /* Loose Rate Control */
+ (0<< 24) | /* RC Stable Tolerance */
+ (rc_panic_enable<< 23) | /* RC Panic Enable */
+ (1<< 22) | /* CBP mode */
+ (0<< 21) | /* MB Type Direct Conversion, 0: Enable, 1: Disable */
+ (0<< 20) | /* MB Type Skip Conversion, 0: Enable, 1: Disable */
+ (!next_slice_param<< 19) | /* Is Last Slice */
+ (0<< 18) | /* BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable */
+ (1<< 17) | /* HeaderPresentFlag */
+ (1<< 16) | /* SliceData PresentFlag */
+ (0<< 15) | /* TailPresentFlag, TODO: check it on VDEnc */
+ (1<< 13) | /* RBSP NAL TYPE */
+ (1<< 12)); /* CabacZeroWordInsertionEnable */
+
+ OUT_BCS_BATCH(batch, generic_ctx->compressed_bitstream.start_offset);
+
+ OUT_BCS_BATCH(batch,
+ (max_qp_n<< 24) | /*Target QP - 24 is lowest QP*/
+ (max_qp_p<< 16) | /*Target QP + 20 is highest QP*/
+ (shrink<< 8) |
+ (grow<< 0));
+ OUT_BCS_BATCH(batch,
+ (rounding_inter_enable<< 31) |
+ (rounding_value<< 28) |
+ (1<< 27) |
+ (5<< 24) |
+ (correct[5]<< 20) |
+ (correct[4]<< 16) |
+ (correct[3]<< 12) |
+ (correct[2]<< 8) |
+ (correct[1]<< 4) |
+ (correct[0]<< 0));
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static uint8_t
+gen9_mfc_avc_get_ref_idx_state(VAPictureH264 *va_pic, unsigned int frame_store_id)
+{
+ unsigned int is_long_term =
+ !!(va_pic->flags& VA_PICTURE_H264_LONG_TERM_REFERENCE);
+ unsigned int is_top_field =
+ !!(va_pic->flags& VA_PICTURE_H264_TOP_FIELD);
+ unsigned int is_bottom_field =
+ !!(va_pic->flags& VA_PICTURE_H264_BOTTOM_FIELD);
+
+ return ((is_long_term<< 6) |
+ (0<< 5) |
+ (frame_store_id<< 1) |
+ ((is_top_field ^ 1)& is_bottom_field));
+}
+
+static void
+gen9_mfc_avc_ref_idx_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ struct intel_batchbuffer *batch)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ VAPictureH264 *ref_pic;
+ int i, slice_type, ref_idx_shift;
+ unsigned int fwd_ref_entry;
+ unsigned int bwd_ref_entry;
+
+ /* max 4 ref frames are allowed for l0 and l1 */
+ fwd_ref_entry = 0x80808080;
+ slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+
+ if ((slice_type == SLICE_TYPE_P) ||
+ (slice_type == SLICE_TYPE_B)) {
+ for (i = 0; i< avc_state->num_refs[0]; i++) {
+ ref_pic =&slice_param->RefPicList0[i];
+ ref_idx_shift = i * 8;
+
+ fwd_ref_entry&= ~(0xFF<< ref_idx_shift);
+ fwd_ref_entry += (gen9_mfc_avc_get_ref_idx_state(ref_pic, avc_state->list_ref_idx[0][i])<< ref_idx_shift);
+ }
+ }
+
+ bwd_ref_entry = 0x80808080;
+ if (slice_type == SLICE_TYPE_B) {
+ for (i = 0; i< avc_state->num_refs[1]; i++) {
+ ref_pic =&slice_param->RefPicList1[i];
+ ref_idx_shift = i * 8;
+
+ bwd_ref_entry&= ~(0xFF<< ref_idx_shift);
+ bwd_ref_entry += (gen9_mfc_avc_get_ref_idx_state(ref_pic, avc_state->list_ref_idx[1][i])<< ref_idx_shift);
+ }
+ }
+
+ if ((slice_type == SLICE_TYPE_P) ||
+ (slice_type == SLICE_TYPE_B)) {
+ BEGIN_BCS_BATCH(batch, 10);
+ OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
+ OUT_BCS_BATCH(batch, 0); // L0
+ OUT_BCS_BATCH(batch, fwd_ref_entry);
+
+ for (i = 0; i< 7; i++) {
+ OUT_BCS_BATCH(batch, 0x80808080);
+ }
+
+ ADVANCE_BCS_BATCH(batch);
+ }
+
+ if (slice_type == SLICE_TYPE_B) {
+ BEGIN_BCS_BATCH(batch, 10);
+ OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
+ OUT_BCS_BATCH(batch, 1); //Select L1
+ OUT_BCS_BATCH(batch, bwd_ref_entry); //max 4 reference allowed
+ for(i = 0; i< 7; i++) {
+ OUT_BCS_BATCH(batch, 0x80808080);
+ }
+ ADVANCE_BCS_BATCH(batch);
+ }
+}
+
+static void
+gen9_mfc_avc_weightoffset_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncPictureParameterBufferH264 *pic_param,
+ VAEncSliceParameterBufferH264 *slice_param,
+ struct intel_batchbuffer *batch)
+{
+ int i, slice_type;
+ short weightoffsets[32 * 6];
+
+ slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+
+ if (slice_type == SLICE_TYPE_P&&
+ pic_param->pic_fields.bits.weighted_pred_flag == 1) {
+ memset(weightoffsets,0,32*6 * sizeof(short));
+ for (i = 0; i< 32; i++) {
+ weightoffsets[i * 6 + 0] = slice_param->luma_weight_l0[i];
+ weightoffsets[i * 6 + 1] = slice_param->luma_offset_l0[i];
+ weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l0[i][0];
+ weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l0[i][0];
+ weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l0[i][1];
+ weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l0[i][1];
+ }
+
+ BEGIN_BCS_BATCH(batch, 98);
+ OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
+
+ ADVANCE_BCS_BATCH(batch);
+ }
+
+ if (slice_type == SLICE_TYPE_B&&
+ (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
+ memset(weightoffsets,0,32*6 * sizeof(short));
+ for (i = 0; i< 32; i++) {
+ weightoffsets[i * 6 + 0] = slice_param->luma_weight_l0[i];
+ weightoffsets[i * 6 + 1] = slice_param->luma_offset_l0[i];
+ weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l0[i][0];
+ weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l0[i][0];
+ weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l0[i][1];
+ weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l0[i][1];
+ }
+
+ BEGIN_BCS_BATCH(batch, 98);
+ OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
+ ADVANCE_BCS_BATCH(batch);
+
+ memset(weightoffsets,0,32*6 * sizeof(short));
+ for (i = 0; i< 32; i++) {
+ weightoffsets[i * 6 + 0] = slice_param->luma_weight_l1[i];
+ weightoffsets[i * 6 + 1] = slice_param->luma_offset_l1[i];
+ weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l1[i][0];
+ weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l1[i][0];
+ weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l1[i][1];
+ weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l1[i][1];
+ }
+
+ BEGIN_BCS_BATCH(batch, 98);
+ OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
+ OUT_BCS_BATCH(batch, 1);
+ intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
+ ADVANCE_BCS_BATCH(batch);
+ }
+}
+
+static void
+gen9_mfc_avc_single_slice(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ VAEncSliceParameterBufferH264 *next_slice_param,
+ int slice_index)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct intel_batchbuffer *slice_batch = avc_ctx->pres_slice_batch_buffer_2nd_level;
+ VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+ struct gpe_mi_batch_buffer_start_parameter second_level_batch;
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+
+ unsigned int slice_offset = 0;
+
+ if(generic_state->curr_pak_pass == 0)
+ {
+ slice_offset = intel_batchbuffer_used_size(slice_batch);
+ avc_state->slice_batch_offset[slice_index] = slice_offset;
+ gen9_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context, slice_param,slice_batch);
+ gen9_mfc_avc_weightoffset_state(ctx,
+ encode_state,
+ encoder_context,
+ pic_param,
+ slice_param,
+ slice_batch);
+ gen9_mfc_avc_slice_state(ctx,
+ encode_state,
+ encoder_context,
+ pic_param,
+ slice_param,
+ next_slice_param,
+ slice_batch);
+ gen9_mfc_avc_inset_headers(ctx,
+ encode_state,
+ encoder_context,
+ slice_param,
+ slice_index,
+ slice_batch);
+
+ BEGIN_BCS_BATCH(slice_batch, 2);
+ OUT_BCS_BATCH(slice_batch, 0);
+ OUT_BCS_BATCH(slice_batch, MI_BATCH_BUFFER_END);
+ ADVANCE_BCS_BATCH(slice_batch);
+
+ }else
+ {
+ slice_offset = avc_state->slice_batch_offset[slice_index];
+ }
+ /* insert slice as second levle.*/
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ second_level_batch.is_second_level = 1; /* Must be the second level batch buffer */
+ second_level_batch.offset = slice_offset;
+ second_level_batch.bo = slice_batch->buffer;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch,&second_level_batch);
+
+ /* insert mb code as second levle.*/
+ obj_surface = encode_state->reconstructed_object;
+ assert(obj_surface->private_data);
+ avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
+
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ second_level_batch.is_second_level = 1; /* Must be the second level batch buffer */
+ second_level_batch.offset = slice_param->macroblock_address * 16 * 4;
+ second_level_batch.bo = avc_priv_surface->res_mb_code_surface.bo;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch,&second_level_batch);
+
+}
+
+static void
+gen9_avc_pak_slice_level(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct gpe_mi_flush_dw_parameter mi_flush_dw_params;
+ VAEncSliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
+ int i, j;
+ int slice_index = 0;
+ int is_frame_level = 1; /* TODO: check it for SKL,now single slice per frame */
+ int has_tail = 0; /* TODO: check it later */
+
+ for (j = 0; j< encode_state->num_slice_params_ext; j++) {
+ slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
+
+ if (j == encode_state->num_slice_params_ext - 1)
+ next_slice_group_param = NULL;
+ else
+ next_slice_group_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j + 1]->buffer;
+
+ for (i = 0; i< encode_state->slice_params_ext[j]->num_elements; i++) {
+ if (i< encode_state->slice_params_ext[j]->num_elements - 1)
+ next_slice_param = slice_param + 1;
+ else
+ next_slice_param = next_slice_group_param;
+
+ gen9_mfc_avc_single_slice(ctx,
+ encode_state,
+ encoder_context,
+ slice_param,
+ next_slice_param,
+ slice_index);
+ slice_param++;
+ slice_index++;
+
+ if (is_frame_level)
+ break;
+ else {
+ /* TODO: remove assert(0) and add other commands here */
+ assert(0);
+ }
+ }
+
+ if (is_frame_level)
+ break;
+ }
+
+ if (has_tail) {
+ /* TODO: insert a tail if required */
+ }
+
+ memset(&mi_flush_dw_params, 0, sizeof(mi_flush_dw_params));
+ mi_flush_dw_params.video_pipeline_cache_invalidate = 1;
+ gen8_gpe_mi_flush_dw(ctx, batch,&mi_flush_dw_params);
+}
+static void
+gen9_avc_pak_picture_level(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct gpe_mi_batch_buffer_start_parameter second_level_batch;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ if (generic_state->brc_enabled&&
+ generic_state->curr_pak_pass) {
+ struct gpe_mi_conditional_batch_buffer_end_parameter mi_conditional_batch_buffer_end_params;
+ struct encoder_status_buffer_internal *status_buffer;
+ status_buffer =&(avc_ctx->status_buffer);
+
+ memset(&mi_conditional_batch_buffer_end_params, 0, sizeof(mi_conditional_batch_buffer_end_params));
+ mi_conditional_batch_buffer_end_params.offset = status_buffer->image_status_mask_offset;
+ mi_conditional_batch_buffer_end_params.bo = status_buffer->bo;
+ mi_conditional_batch_buffer_end_params.compare_data = 0;
+ mi_conditional_batch_buffer_end_params.compare_mask_mode_disabled = 0;
+ gen9_gpe_mi_conditional_batch_buffer_end(ctx, batch,&mi_conditional_batch_buffer_end_params);
+ }
+
+ gen9_mfc_avc_pipe_mode_select(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_surface_state(ctx,encoder_context,&(generic_ctx->res_reconstructed_surface),0);
+ gen9_mfc_avc_surface_state(ctx,encoder_context,&(generic_ctx->res_uncompressed_input_surface),4);
+ gen9_mfc_avc_pipe_buf_addr_state(ctx,encoder_context);
+ gen9_mfc_avc_ind_obj_base_addr_state(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_bsp_buf_base_addr_state(ctx,encoder_context);
+
+ if(generic_state->brc_enabled)
+ {
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ if (generic_state->curr_pak_pass == 0) {
+ second_level_batch.offset = 0;
+ } else {
+ second_level_batch.offset = generic_state->curr_pak_pass * INTEL_AVC_IMAGE_STATE_CMD_SIZE;
+ }
+ second_level_batch.is_second_level = 1;
+ second_level_batch.bo = avc_ctx->res_brc_image_state_read_buffer.bo;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch,&second_level_batch);
+ }else
+ {
+ /*generate a new image state */
+ gen9_avc_set_image_state_non_brc(ctx,encode_state,encoder_context,&(avc_ctx->res_image_state_batch_buffer_2nd_level));
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ second_level_batch.offset = 0;
+ second_level_batch.is_second_level = 1;
+ second_level_batch.bo = avc_ctx->res_image_state_batch_buffer_2nd_level.bo;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch,&second_level_batch);
+ }
+
+ gen9_mfc_avc_qm_state(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_fqm_state(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_directmode_state(ctx,encoder_context);
+
+}
+
+static void
+gen9_avc_read_mfc_status(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+
+ struct gpe_mi_store_register_mem_parameter mi_store_reg_mem_param;
+ struct gpe_mi_store_data_imm_parameter mi_store_data_imm_param;
+ struct gpe_mi_flush_dw_parameter mi_flush_dw_param;
+ struct encoder_status_buffer_internal *status_buffer;
+
+ status_buffer =&(avc_ctx->status_buffer);
+
+ memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
+ gen8_gpe_mi_flush_dw(ctx, batch,&mi_flush_dw_param);
+
+ /* read register and store into status_buffer and pak_statitistic info */
+ memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->bs_byte_count_frame_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->bs_byte_count_frame_nh_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_nh_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->mfc_qp_status_count_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->mfc_qp_status_count_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->image_status_mask_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->image_status_mask_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ /*update the status in the pak_statistic_surface */
+ mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_reg_mem_param.offset = 0;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_reg_mem_param.offset = 4;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_nh_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ memset(&mi_store_data_imm_param, 0, sizeof(mi_store_data_imm_param));
+ mi_store_data_imm_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_data_imm_param.offset = sizeof(unsigned int) * 2;
+ mi_store_data_imm_param.dw0 = (generic_state->curr_pak_pass + 1);
+ gen8_gpe_mi_store_data_imm(ctx, batch,&mi_store_data_imm_param);
+
+ mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_reg_mem_param.offset = sizeof(unsigned int) * (4 + generic_state->curr_pak_pass) ;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->image_status_ctrl_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
+ gen8_gpe_mi_flush_dw(ctx, batch,&mi_flush_dw_param);
+
+ return;
+}
+
+static void
+gen9_avc_pak_brc_prepare(struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ unsigned int rate_control_mode = encoder_context->rate_control_mode;
+
+ switch (rate_control_mode& 0x7f) {
+ generic_state->internal_rate_mode = VA_RC_CBR;
+ break;
+
+ generic_state->internal_rate_mode = VA_RC_VBR;//AVBR
+ break;
+
+ generic_state->internal_rate_mode = VA_RC_CQP;
+ break;
+ }
+
+}
+
+static VAStatus
+gen9_avc_pak_pipeline_prepare(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus va_status;
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+
+ struct object_surface *obj_surface;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+ VAEncSliceParameterBufferH264 *slice_param = avc_state->slice_param[0];
+
+ struct gen9_surface_avc *avc_priv_surface;
+ int i, j, enable_avc_ildb = 0;
+ unsigned int allocate_flag = 1;
+ unsigned int size;
+ unsigned int w_mb = generic_state->frame_width_in_mbs;
+ unsigned int h_mb = generic_state->frame_height_in_mbs;
+ struct avc_surface_param surface_param;
+
+ /* update the parameter and check slice parameter */
+ for (j = 0; j< encode_state->num_slice_params_ext&& enable_avc_ildb == 0; j++) {
+ assert(encode_state->slice_params_ext&& encode_state->slice_params_ext[j]->buffer);
+ slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
+
+ for (i = 0; i< encode_state->slice_params_ext[j]->num_elements; i++) {
+ assert((slice_param->slice_type == SLICE_TYPE_I) ||
+ (slice_param->slice_type == SLICE_TYPE_SI) ||
+ (slice_param->slice_type == SLICE_TYPE_P) ||
+ (slice_param->slice_type == SLICE_TYPE_SP) ||
+ (slice_param->slice_type == SLICE_TYPE_B));
+
+ if (slice_param->disable_deblocking_filter_idc != 1) {
+ enable_avc_ildb = 1;
+ break;
+ }
+
+ slice_param++;
+ }
+ }
+ avc_state->enable_avc_ildb = enable_avc_ildb;
+
+ /* setup the all surface and buffer for PAK */
+ /* Setup current reconstruct frame */
+ obj_surface = encode_state->reconstructed_object;
+ va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
+
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ memset(&surface_param,0,sizeof(surface_param));
+ surface_param.frame_width = generic_state->frame_width_in_pixel;
+ surface_param.frame_height = generic_state->frame_height_in_pixel;
+ va_status = gen9_avc_init_check_surfaces(ctx,
+ obj_surface,encoder_context,
+&surface_param);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ /* init the member of avc_priv_surface,frame_store_id,qp_value */
+ {
+ avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = 0;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = 0;
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2]);
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1]);
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2],avc_priv_surface->dmv_top);
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1],avc_priv_surface->dmv_bottom);
+ dri_bo_reference(avc_priv_surface->dmv_top);
+ dri_bo_reference(avc_priv_surface->dmv_bottom);
+ avc_priv_surface->qp_value = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+ avc_priv_surface->frame_store_id = 0;
+ avc_priv_surface->frame_idx = pic_param->CurrPic.frame_idx;
+ avc_priv_surface->top_field_order_cnt = pic_param->CurrPic.TopFieldOrderCnt;
+ avc_priv_surface->is_as_ref = pic_param->pic_fields.bits.reference_pic_flag;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = avc_priv_surface->top_field_order_cnt;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = avc_priv_surface->top_field_order_cnt + 1;
+ }
+ i965_free_gpe_resource(&generic_ctx->res_reconstructed_surface);
+ i965_free_gpe_resource(&avc_ctx->res_post_deblocking_output);
+ i965_free_gpe_resource(&avc_ctx->res_pre_deblocking_output);
+ i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_reconstructed_surface, obj_surface);
+
+
+ if (avc_state->enable_avc_ildb) {
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_post_deblocking_output, obj_surface);
+ } else {
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_pre_deblocking_output, obj_surface);
+ }
+ /* input YUV surface */
+ obj_surface = encode_state->input_yuv_object;
+ va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
+
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ i965_free_gpe_resource(&generic_ctx->res_uncompressed_input_surface);
+ i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_uncompressed_input_surface, obj_surface);
+
+ /* Reference surfaces */
+ for (i = 0; i< ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {
+ i965_free_gpe_resource(&avc_ctx->list_reference_res[i]);
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2]);
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1]);
+ obj_surface = encode_state->reference_objects[i];
+ avc_state->top_field_poc[2*i] = 0;
+ avc_state->top_field_poc[2*i+1] = 0;
+
+ if (obj_surface&& obj_surface->bo) {
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->list_reference_res[i], obj_surface);
+
+ /* actually it should be handled when it is reconstructed surface */
+ va_status = gen9_avc_init_check_surfaces(ctx,
+ obj_surface,encoder_context,
+&surface_param);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2],avc_priv_surface->dmv_top);
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1],avc_priv_surface->dmv_bottom);
+ dri_bo_reference(avc_priv_surface->dmv_top);
+ dri_bo_reference(avc_priv_surface->dmv_bottom);
+ avc_priv_surface->frame_store_id = i;
+ avc_state->top_field_poc[2*i] = avc_priv_surface->top_field_order_cnt;
+ avc_state->top_field_poc[2*i+1] = avc_priv_surface->top_field_order_cnt+1;
+ }else
+ {
+ break;
+ }
+ }
+
+ if (avc_ctx->pres_slice_batch_buffer_2nd_level)
+ intel_batchbuffer_free(avc_ctx->pres_slice_batch_buffer_2nd_level);
+
+ avc_ctx->pres_slice_batch_buffer_2nd_level =
+ intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
+ 4096 *
+ encode_state->num_slice_params_ext);
+ if (!avc_ctx->pres_slice_batch_buffer_2nd_level)
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+
+ for (i = 0;i< MAX_AVC_SLICE_NUM;i++) {
+ avc_state->slice_batch_offset[i] = 0;
+ }
+
+
+ size = w_mb * 64;
+ i965_free_gpe_resource(&avc_ctx->res_intra_row_store_scratch_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_intra_row_store_scratch_buffer,
+ size,
+ "PAK Intra row store scratch buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = w_mb * 4 * 64;
+ i965_free_gpe_resource(&avc_ctx->res_deblocking_filter_row_store_scratch_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_deblocking_filter_row_store_scratch_buffer,
+ size,
+ "PAK Deblocking filter row store scratch buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = w_mb * 2 * 64;
+ i965_free_gpe_resource(&avc_ctx->res_bsd_mpc_row_store_scratch_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_bsd_mpc_row_store_scratch_buffer,
+ size,
+ "PAK BSD/MPC row store scratch buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = w_mb * h_mb * 16;
+ i965_free_gpe_resource(&avc_ctx->res_pak_mb_status_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_pak_mb_status_buffer,
+ size,
+ "PAK MB status buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ return VA_STATUS_SUCCESS;
+
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
+
+static VAStatus
+gen9_avc_encode_picture(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus va_status;
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ va_status = gen9_avc_pak_pipeline_prepare(ctx, encode_state, encoder_context);
+
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+
Please check whether the below logic is correct.
It seems that it uses the GPU command of conditional end for the
subsequent pass. In such case all the commands should be put into one
batch buffer and it is submitted only once.
But the current logic causes that it is submitted multiple times.
Post by Pengfei Qu
+ for (generic_state->curr_pak_pass = 0;
+ generic_state->curr_pak_pass< generic_state->num_pak_passes;
+ generic_state->curr_pak_pass++) {
+
+ if (i965->intel.has_bsd2)
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+ else
+ intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
+ intel_batchbuffer_emit_mi_flush(batch);
+
+ if (generic_state->curr_pak_pass == 0) {
+ /* Initialize the avc Image Ctrl reg for the first pass,write 0 to staturs/control register, is it needed in AVC? */
+ struct gpe_mi_load_register_imm_parameter mi_load_reg_imm;
+ struct encoder_status_buffer_internal *status_buffer;
+
+ status_buffer =&(avc_ctx->status_buffer);
+ memset(&mi_load_reg_imm, 0, sizeof(mi_load_reg_imm));
+ mi_load_reg_imm.mmio_offset = status_buffer->image_status_ctrl_reg_offset;
+ mi_load_reg_imm.data = 0;
+ gen8_gpe_mi_load_register_imm(ctx, batch,&mi_load_reg_imm);
+ }
+ gen9_avc_pak_picture_level(ctx, encode_state, encoder_context);
+ gen9_avc_pak_slice_level(ctx, encode_state, encoder_context);
+ intel_batchbuffer_emit_mi_flush(batch);
+
+ gen9_avc_read_mfc_status(ctx, encoder_context);
+ intel_batchbuffer_end_atomic(batch);
+ intel_batchbuffer_flush(batch);
+
+ }
+
+ generic_state->seq_frame_number++;
+ generic_state->total_frame_number++;
+ generic_state->first_frame = 0;
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus
+gen9_avc_pak_pipeline(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus vaStatus;
+
+ switch (profile) {
+ vaStatus = gen9_avc_encode_picture(ctx, profile, encode_state, encoder_context);
+ break;
+
+ vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
+ break;
+ }
+
+ return vaStatus;
+}
+
+static void
+gen9_avc_pak_context_destroy(void * context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+
+ int i = 0;
+
+ if (!pak_context)
+ return;
+
+ // other things
+ i965_free_gpe_resource(&generic_ctx->res_reconstructed_surface);
+ i965_free_gpe_resource(&avc_ctx->res_post_deblocking_output);
+ i965_free_gpe_resource(&avc_ctx->res_pre_deblocking_output);
+ i965_free_gpe_resource(&generic_ctx->res_uncompressed_input_surface);
+
+ i965_free_gpe_resource(&generic_ctx->compressed_bitstream.res);
+ i965_free_gpe_resource(&avc_ctx->res_intra_row_store_scratch_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_deblocking_filter_row_store_scratch_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_bsd_mpc_row_store_scratch_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_pak_mb_status_buffer);
+
+ for(i = 0 ; i< MAX_MFC_AVC_REFERENCE_SURFACES; i++)
+ {
+ i965_free_gpe_resource(&avc_ctx->list_reference_res[i]);
+ }
+
+ for(i = 0 ; i< NUM_MFC_AVC_DMV_BUFFERS; i++)
+ {
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i]);
+ }
+
+ if (avc_ctx->pres_slice_batch_buffer_2nd_level)
+ {
+ intel_batchbuffer_free(avc_ctx->pres_slice_batch_buffer_2nd_level);
+ avc_ctx->pres_slice_batch_buffer_2nd_level = NULL;
+ }
+
+}
+
+static VAStatus
+gen9_avc_get_coded_status(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ struct i965_coded_buffer_segment *coded_buf_seg)
+{
+ struct encoder_status *avc_encode_status;
+
+ if (!encoder_context || !coded_buf_seg)
+ return VA_STATUS_ERROR_INVALID_BUFFER;
+
+ avc_encode_status = (struct encoder_status *)coded_buf_seg->codec_private_data;
+ coded_buf_seg->base.size = avc_encode_status->bs_byte_count_frame;
+
+ return VA_STATUS_SUCCESS;
+}
+
It will be better that this function is defined in Patch_07.
Post by Pengfei Qu
Add VME pipeline for H264 encoder
+Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ /* VME& PAK share the same context */
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = NULL;
+ struct generic_encoder_context * generic_ctx = NULL;
+ struct gen9_avc_encoder_context * avc_ctx = NULL;
+ struct generic_enc_codec_state * generic_state = NULL;
+ struct avc_enc_state * avc_state = NULL;
+ struct encoder_status_buffer_internal *status_buffer;
+ uint32_t base_offset = offsetof(struct i965_coded_buffer_segment, codec_private_data);
+
+ vme_context = calloc(1, sizeof(struct encoder_vme_mfc_context));
+ generic_ctx = calloc(1, sizeof(struct generic_encoder_context));
+ avc_ctx = calloc(1, sizeof(struct gen9_avc_encoder_context));
+ generic_state = calloc(1, sizeof(struct generic_enc_codec_state));
+ avc_state = calloc(1, sizeof(struct avc_enc_state));
+
+ if(!vme_context || !generic_ctx || !avc_ctx || !generic_state || !avc_state)
+ goto allocate_structure_failed;
+
+ memset(vme_context,0,sizeof(struct encoder_vme_mfc_context));
+ memset(generic_ctx,0,sizeof(struct generic_encoder_context));
+ memset(avc_ctx,0,sizeof(struct gen9_avc_encoder_context));
+ memset(generic_state,0,sizeof(struct generic_enc_codec_state));
+ memset(avc_state,0,sizeof(struct avc_enc_state));
+
+ encoder_context->vme_context = vme_context;
+ vme_context->generic_enc_ctx = generic_ctx;
+ vme_context->private_enc_ctx = avc_ctx;
+ vme_context->generic_enc_state = generic_state;
+ vme_context->private_enc_state = avc_state;
+
+ if (IS_SKL(i965->intel.device_info)) {
+ generic_ctx->enc_kernel_ptr = (void *)skl_avc_encoder_kernels;
+ generic_ctx->enc_kernel_size = sizeof(skl_avc_encoder_kernels);
+ }
+ else
+ goto allocate_structure_failed;
+
+ /* initialize misc ? */
+ avc_ctx->ctx = ctx;
+ generic_ctx->use_hw_scoreboard = 1;
+ generic_ctx->use_hw_non_stalling_scoreboard = 1;
+
+ /* initialize generic state */
+
+ generic_state->kernel_mode = INTEL_ENC_KERNEL_NORMAL;
+ generic_state->preset = INTEL_PRESET_RT_SPEED;
+ generic_state->seq_frame_number = 0;
+ generic_state->total_frame_number = 0;
+ generic_state->frame_type = 0;
+ generic_state->first_frame = 1;
+
+ generic_state->frame_width_in_pixel = 0;
+ generic_state->frame_height_in_pixel = 0;
+ generic_state->frame_width_in_mbs = 0;
+ generic_state->frame_height_in_mbs = 0;
+ generic_state->frame_width_4x = 0;
+ generic_state->frame_height_4x = 0;
+ generic_state->frame_width_16x = 0;
+ generic_state->frame_height_16x = 0;
+ generic_state->frame_width_32x = 0;
+ generic_state->downscaled_width_4x_in_mb = 0;
+ generic_state->downscaled_height_4x_in_mb = 0;
+ generic_state->downscaled_width_16x_in_mb = 0;
+ generic_state->downscaled_height_16x_in_mb = 0;
+ generic_state->downscaled_width_32x_in_mb = 0;
+ generic_state->downscaled_height_32x_in_mb = 0;
+
+ generic_state->hme_supported = 1;
+ generic_state->b16xme_supported = 1;
+ generic_state->b32xme_supported = 0;
+ generic_state->hme_enabled = 0;
+ generic_state->b16xme_enabled = 0;
+ generic_state->b32xme_enabled = 0;
+ generic_state->brc_distortion_buffer_supported = 1;
+ generic_state->brc_constant_buffer_supported = 0;
+
+
+ generic_state->frame_rate = 30;
+ generic_state->brc_allocated = 0;
+ generic_state->brc_inited = 0;
+ generic_state->brc_need_reset = 0;
+ generic_state->is_low_delay = 0;
+ generic_state->brc_enabled = 0;//default
+ generic_state->internal_rate_mode = 0;
+ generic_state->curr_pak_pass = 0;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ generic_state->is_first_pass = 1;
+ generic_state->is_last_pass = 0;
+ generic_state->mb_brc_enabled = 0; // enable mb brc
+ generic_state->brc_roi_enable = 0;
+ generic_state->brc_dirty_roi_enable = 0;
+ generic_state->skip_frame_enbale = 0;
+
+ generic_state->target_bit_rate = 0;
+ generic_state->max_bit_rate = 0;
+ generic_state->min_bit_rate = 0;
+ generic_state->init_vbv_buffer_fullness_in_bit = 0;
+ generic_state->vbv_buffer_size_in_bit = 0;
+ generic_state->frames_per_100s = 0;
+ generic_state->gop_size = 0;
+ generic_state->gop_ref_distance = 0;
+ generic_state->brc_target_size = 0;
+ generic_state->brc_mode = 0;
+ generic_state->brc_init_current_target_buf_full_in_bits = 0.0;
+ generic_state->brc_init_reset_input_bits_per_frame = 0.0;
+ generic_state->brc_init_reset_buf_size_in_bits = 0;
+ generic_state->brc_init_previous_target_buf_full_in_bits = 0;
+ generic_state->window_size = 0;//default
+ generic_state->target_percentage = 0;
+
+ generic_state->avbr_curracy = 0;
+ generic_state->avbr_convergence = 0;
+
+ generic_state->num_skip_frames = 0;
+ generic_state->size_skip_frames = 0;
+
+ generic_state->num_roi = 0;
+ generic_state->max_delta_qp = 0;
+ generic_state->min_delta_qp = 0;
+
+ if (encoder_context->rate_control_mode != VA_RC_NONE&&
+ encoder_context->rate_control_mode != VA_RC_CQP) {
+ generic_state->brc_enabled = 1;
+ generic_state->brc_distortion_buffer_supported = 1;
+ generic_state->brc_constant_buffer_supported = 1;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ }
+ /*avc state initialization */
+ avc_state->mad_enable = 0;
+ avc_state->mb_disable_skip_map_enable = 0;
+ avc_state->sfd_enable = 1;//default
+ avc_state->sfd_mb_enable = 1;//set it true
+ avc_state->adaptive_search_window_enable = 1;//default
+ avc_state->mb_qp_data_enable = 0;
+ avc_state->intra_refresh_i_enable = 0;
+ avc_state->min_max_qp_enable = 0;
+ avc_state->skip_bias_adjustment_enable = 0;//default,same as skip_bias_adjustment_supporte? no
+
+ //external input
+ avc_state->non_ftq_skip_threshold_lut_input_enable = 0;
+ avc_state->ftq_skip_threshold_lut_input_enable = 0;
+ avc_state->ftq_override = 0;
+
+ avc_state->direct_bias_adjustment_enable = 0;
+ avc_state->global_motion_bias_adjustment_enable = 0;
+ avc_state->disable_sub_mb_partion = 0;
+ avc_state->arbitrary_num_mbs_in_slice = 0;
+ avc_state->adaptive_transform_decision_enable = 0;//default
+ avc_state->skip_check_disable = 0;
+ avc_state->tq_enable = 0;
+ avc_state->enable_avc_ildb = 0;
+ avc_state->mbaff_flag = 0;
+ avc_state->enable_force_skip = 1;//default
+ avc_state->rc_panic_enable = 1;//default
+ avc_state->suppress_recon_enable = 1;//default
+
+ avc_state->ref_pic_select_list_supported = 1;
+ avc_state->mb_brc_supported = 1;//?,default
+ avc_state->multi_pre_enable = 1;//default
+ avc_state->ftq_enable = 1;//default
+ avc_state->caf_supported = 1; //default
+ avc_state->caf_enable = 0;
+ avc_state->caf_disable_hd = 1;//default
+ avc_state->skip_bias_adjustment_supported = 1;//default
+
+ avc_state->adaptive_intra_scaling_enable = 1;//default
+ avc_state->old_mode_cost_enable = 0;//default
+ avc_state->multi_ref_qp_enable = 1;//default
+ avc_state->weighted_ref_l0_enable = 1;//default
+ avc_state->weighted_ref_l1_enable = 1;//default
+ avc_state->weighted_prediction_supported = 0;
+ avc_state->brc_split_enable = 0;
+ avc_state->slice_level_report_supported = 0;
+
+ avc_state->fbr_bypass_enable = 1;//default
+ avc_state->field_scaling_output_interleaved = 0;
+ avc_state->mb_variance_output_enable = 0;
+ avc_state->mb_pixel_average_output_enable = 0;
+ avc_state->rolling_intra_refresh_enable = 0;// same as intra_refresh_i_enable?
+ avc_state->mbenc_curbe_set_in_brc_update = 0;
+ avc_state->rounding_inter_enable = 1; //default
+ avc_state->adaptive_rounding_inter_enable = 1;//default
+
+ avc_state->mbenc_i_frame_dist_in_use = 0;
+ avc_state->mb_status_supported = 1; //set in intialization for gen9
+ avc_state->mb_status_enable = 0;
+ avc_state->mb_vproc_stats_enable = 0;
+ avc_state->flatness_check_enable = 0;
+ avc_state->flatness_check_supported = 1;//default
+ avc_state->block_based_skip_enable = 0;
+ avc_state->use_widi_mbenc_kernel = 0;
+ avc_state->kernel_trellis_enable = 0;
+ avc_state->generic_reserved = 0;
+
+ avc_state->rounding_value = 0;
+ avc_state->rounding_inter_p = 255;//default
+ avc_state->rounding_inter_b = 255; //default
+ avc_state->rounding_inter_b_ref = 255; //default
+ avc_state->min_qp_i = INTEL_AVC_MIN_QP;
+ avc_state->min_qp_p = INTEL_AVC_MIN_QP;
+ avc_state->min_qp_b = INTEL_AVC_MIN_QP;
+ avc_state->max_qp_i = INTEL_AVC_MAX_QP;
+ avc_state->max_qp_p = INTEL_AVC_MAX_QP;
+ avc_state->max_qp_b = INTEL_AVC_MAX_QP;
+
+ memset(avc_state->non_ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
+ memset(avc_state->ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
+ memset(avc_state->lamda_value_lut,0,52*2*sizeof(uint8_t));
+
+ avc_state->intra_refresh_qp_threshold = 0;
+ avc_state->trellis_flag = 0;
+ avc_state->hme_mv_cost_scaling_factor = 0;
+ avc_state->slice_height = 1;
+ avc_state->slice_num = 1;
+ memset(avc_state->dist_scale_factor_list0,0,32*sizeof(uint32_t));
+ avc_state->bi_weight = 0;
+ avc_state->brc_const_data_surface_width = 64;
+ avc_state->brc_const_data_surface_height = 44;
+
+ avc_state->num_refs[0] = 0;
+ avc_state->num_refs[1] = 0;
+ memset(avc_state->list_ref_idx,0,32*2*sizeof(uint32_t));
+ memset(avc_state->top_field_poc,0,NUM_MFC_AVC_DMV_BUFFERS*sizeof(int32_t));
+ avc_state->tq_rounding = 0;
+ avc_state->zero_mv_threshold = 0;
+ avc_state->slice_second_levle_batch_buffer_in_use = 0;
+
+ //1. seq/pic/slice
+
+ /* the definition of status buffer offset for Encoder */
+
+ status_buffer =&avc_ctx->status_buffer;
+ memset(status_buffer, 0,sizeof(struct encoder_status_buffer_internal));
+
+ status_buffer->base_offset = base_offset;
+ status_buffer->bs_byte_count_frame_offset = base_offset + offsetof(struct encoder_status, bs_byte_count_frame);
+ status_buffer->bs_byte_count_frame_nh_offset = base_offset + offsetof(struct encoder_status, bs_byte_count_frame_nh);
+ status_buffer->image_status_mask_offset = base_offset + offsetof(struct encoder_status, image_status_mask);
+ status_buffer->image_status_ctrl_offset = base_offset + offsetof(struct encoder_status, image_status_ctrl);
+ status_buffer->mfc_qp_status_count_offset = base_offset + offsetof(struct encoder_status, mfc_qp_status_count);
+ status_buffer->media_index_offset = base_offset + offsetof(struct encoder_status, media_index);
+
+ status_buffer->status_buffer_size = sizeof(struct encoder_status);
+ status_buffer->bs_byte_count_frame_reg_offset = MFC_BITSTREAM_BYTECOUNT_FRAME_REG;
+ status_buffer->bs_byte_count_frame_nh_reg_offset = MFC_BITSTREAM_BYTECOUNT_SLICE_REG;
+ status_buffer->image_status_mask_reg_offset = MFC_IMAGE_STATUS_MASK_REG;
+ status_buffer->image_status_ctrl_reg_offset = MFC_IMAGE_STATUS_CTRL_REG;
+ status_buffer->mfc_qp_status_count_reg_offset = MFC_QP_STATUS_COUNT_REG;
+
+ gen9_avc_kernel_init(ctx,encoder_context);
+ encoder_context->vme_context = vme_context;
+ encoder_context->vme_pipeline = gen9_avc_vme_pipeline;
+ encoder_context->vme_context_destroy = gen9_avc_vme_context_destroy;
+
+ return true;
+
+
+ if(vme_context)
+ free(vme_context);
+
+ if(generic_ctx)
+ free(generic_ctx);
+
+ if(avc_ctx)
+ free(avc_ctx);
+
+ if(generic_state)
+ free(generic_state);
+
+ if(avc_state)
+ free(avc_state);
+
+ return false;
+}
+
+Bool
+gen9_avc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ /* VME& PAK share the same context */
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+
+ if (!pak_context)
+ return false;
+
+ encoder_context->mfc_context = pak_context;
+ encoder_context->mfc_context_destroy = gen9_avc_pak_context_destroy;
+ encoder_context->mfc_pipeline = gen9_avc_pak_pipeline;
+ encoder_context->mfc_brc_prepare = gen9_avc_pak_brc_prepare;
+ encoder_context->get_status = gen9_avc_get_coded_status;
+ return true;
+}
Qu, Pengfei
2017-01-18 11:43:20 UTC
Permalink
-----Original Message-----
From: Zhao, Yakui
Sent: Tuesday, January 17, 2017 10:47 AM
To: Qu, Pengfei <***@intel.com>
Cc: ***@lists.freedesktop.org
Subject: Re: [Libva] [PATCH v1 8/9] ENC: add MFX pipeline for AVC encoder
Post by Pengfei Qu
add MFX command for AVC encoder
add MFX Picture slice level command init for AVC
add MFX pipeline init prepare run for AVC encode
add VME/MFX context init for AVC encoder
Please see the inline comment.
Post by Pengfei Qu
---
src/gen9_avc_encoder.c | 1887 +++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 1886 insertions(+), 1 deletion(-)
diff --git a/src/gen9_avc_encoder.c b/src/gen9_avc_encoder.c
index 5caa9f4..a7545f1 100755
--- a/src/gen9_avc_encoder.c
+++ b/src/gen9_avc_encoder.c
@@ -5742,4 +5742,1889 @@ gen9_avc_kernel_init(VADriverContextP ctx,
generic_ctx->pfn_send_brc_mb_update_surface = gen9_avc_send_surface_brc_mb_update;
generic_ctx->pfn_send_sfd_surface = gen9_avc_send_surface_sfd;
generic_ctx->pfn_send_wp_surface = gen9_avc_send_surface_wp;
-}
\ No newline at end of file
+}
+
+/*
+PAK pipeline related function
+*/
+extern int
+intel_avc_enc_slice_type_fixup(int slice_type);
+
+static void
+gen9_mfc_avc_pipe_mode_select(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 5);
+
+ OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
+ OUT_BCS_BATCH(batch,
+ (0<< 29) |
+ (MFX_LONG_MODE<< 17) | /* Must be long format for encoder */
+ (MFD_MODE_VLD<< 15) |
+ (0<< 13) | /* VDEnc mode is 1*/
+ ((generic_state->curr_pak_pass != (generic_state->num_pak_passes -1))<< 10) | /* Stream-Out Enable */
+ ((!!avc_ctx->res_post_deblocking_output.bo)<< 9) | /* Post Deblocking Output */
+ ((!!avc_ctx->res_pre_deblocking_output.bo)<< 8) | /* Pre Deblocking Output */
+ (0<< 7) | /* Scaled surface enable */
+ (0<< 6) | /* Frame statistics stream out enable, always '1' in VDEnc mode */
+ (0<< 5) | /* not in stitch mode */
+ (1<< 4) | /* encoding mode */
+ (MFX_FORMAT_AVC<< 0));
+ OUT_BCS_BATCH(batch,
+ (0<< 7) | /* expand NOA bus flag */
+ (0<< 6) | /* disable slice-level clock gating */
+ (0<< 5) | /* disable clock gating for NOA */
+ (0<< 4) | /* terminate if AVC motion and POC table error occurs */
+ (0<< 3) | /* terminate if AVC mbdata error occurs */
+ (0<< 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
+ (0<< 1) |
+ (0<< 0));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_surface_state(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ struct i965_gpe_resource *gpe_resource,
+ int id)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 6);
+
+ OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
+ OUT_BCS_BATCH(batch, id);
+ OUT_BCS_BATCH(batch,
+ ((gpe_resource->height - 1)<< 18) |
+ ((gpe_resource->width - 1)<< 4));
+ OUT_BCS_BATCH(batch,
+ (MFX_SURFACE_PLANAR_420_8<< 28) | /* 420 planar YUV surface */
+ (1<< 27) | /* must be 1 for interleave U/V, hardware requirement */
+ ((gpe_resource->pitch - 1)<< 3) | /* pitch */
+ (0<< 2) | /* must be 0 for interleave U/V */
+ (1<< 1) | /* must be tiled */
+ (I965_TILEWALK_YMAJOR<< 0)); /* tile walk, TILEWALK_YMAJOR */
+ OUT_BCS_BATCH(batch,
+ (0<< 16) | /* must be 0 for interleave U/V */
+ (gpe_resource->y_cb_offset)); /* y offset for U(cb) */
+ OUT_BCS_BATCH(batch,
+ (0<< 16) | /* must be 0 for interleave U/V */
+ (gpe_resource->y_cb_offset)); /* y offset for U(cb) */
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ int i;
+
+ BEGIN_BCS_BATCH(batch, 65);
+
+ OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (65 - 2));
+
+ /* the DW1-3 is for pre_deblocking */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_pre_deblocking_output.bo, 1, 0, 0);
+
+ /* the DW4-6 is for the post_deblocking */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_post_deblocking_output.bo, 1, 0, 0);
+
+ /* the DW7-9 is for the uncompressed_picture */
+ OUT_BUFFER_3DW(batch, generic_ctx->res_uncompressed_input_surface.bo, 1, 0, 0);
+
+ /* the DW10-12 is for PAK information (write) */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, 0);//?
+
+ /* the DW13-15 is for the intra_row_store_scratch */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_intra_row_store_scratch_buffer.bo, 1, 0, 0);
+
+ /* the DW16-18 is for the deblocking filter */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_deblocking_filter_row_store_scratch_buffer.bo, 1, 0, 0);
+
+ /* the DW 19-50 is for Reference pictures*/
+ for (i = 0; i< ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {
+ OUT_BUFFER_2DW(batch, avc_ctx->list_reference_res[i].bo, 1, 0);
+ }
+
+ /* DW 51, reference picture attributes */
+ OUT_BCS_BATCH(batch, 0);
+
+ /* The DW 52-54 is for PAK information (read) */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_pak_mb_status_buffer.bo, 1, 0, 0);
+
+ /* the DW 55-57 is the ILDB buffer */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ /* the DW 58-60 is the second ILDB buffer */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ /* DW 61, memory compress enable& mode */
+ OUT_BCS_BATCH(batch, 0);
+
+ /* the DW 62-64 is the buffer */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_ind_obj_base_addr_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+ unsigned int size = 0;
+ unsigned int w_mb = generic_state->frame_width_in_mbs;
+ unsigned int h_mb = generic_state->frame_height_in_mbs;
+
+ obj_surface = encode_state->reconstructed_object;
+
+ if (!obj_surface || !obj_surface->private_data)
+ return;
+ avc_priv_surface = obj_surface->private_data;
+
+ BEGIN_BCS_BATCH(batch, 26);
+
+ OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
+ /* The DW1-5 is for the MFX indirect bistream offset, ignore for VDEnc mode */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+ OUT_BUFFER_2DW(batch, NULL, 0, 0);
+
+ /* the DW6-10 is for MFX Indirect MV Object Base Address, ignore for VDEnc mode */
+ size = w_mb * h_mb * 32 * 4;
+ OUT_BUFFER_3DW(batch,
+ avc_priv_surface->res_mv_data_surface.bo,
+ 1,
+ 0,
+ 0);
+ OUT_BUFFER_2DW(batch,
+ avc_priv_surface->res_mv_data_surface.bo,
+ 1,
+ ALIGN(size,0x1000));
+
+ /* The DW11-15 is for MFX IT-COFF. Not used on encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+ OUT_BUFFER_2DW(batch, NULL, 0, 0);
+
+ /* The DW16-20 is for MFX indirect DBLK. Not used on encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+ OUT_BUFFER_2DW(batch, NULL, 0, 0);
+
+ /* The DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder
+ * Note: an offset is specified in MFX_AVC_SLICE_STATE
+ */
+ OUT_BUFFER_3DW(batch,
+ generic_ctx->compressed_bitstream.res.bo,
+ 1,
+ 0,
+ 0);
+ OUT_BUFFER_2DW(batch,
+ generic_ctx->compressed_bitstream.res.bo,
+ 1,
+ generic_ctx->compressed_bitstream.end_offset);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ BEGIN_BCS_BATCH(batch, 10);
+
+ OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
+
+ /* The DW1-3 is for bsd/mpc row store scratch buffer */
+ OUT_BUFFER_3DW(batch, avc_ctx->res_bsd_mpc_row_store_scratch_buffer.bo, 1, 0, 0);
+
+ /* The DW4-6 is for MPR Row Store Scratch Buffer Base Address, ignore for encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ /* The DW7-9 is for Bitplane Read Buffer Base Address, ignore for encoder */
+ OUT_BUFFER_3DW(batch, NULL, 0, 0, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_directmode_state(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+
+ int i;
+
+ BEGIN_BCS_BATCH(batch, 71);
+
+ OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
+
+ /* Reference frames and Current frames */
+ /* the DW1-32 is for the direct MV for reference */
+ for(i = 0; i< NUM_MFC_AVC_DMV_BUFFERS - 2; i += 2) {
+ if ( avc_ctx->res_direct_mv_buffersr[i].bo != NULL) {
+ OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[i].bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+ } else {
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ }
+ }
+
+ OUT_BCS_BATCH(batch, 0);
+
+ /* the DW34-36 is the MV for the current reference */
+ OUT_BCS_RELOC64(batch, avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS - 2].bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ 0);
+
+ OUT_BCS_BATCH(batch, 0);
+
+ /* POL list */
+ for(i = 0; i< 32; i++) {
+ OUT_BCS_BATCH(batch, avc_state->top_field_poc[i]);
+ }
+ OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 2]);
+ OUT_BCS_BATCH(batch, avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS - 1]);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_qm_state(VADriverContextP ctx,
+ int qm_type,
+ const unsigned int *qm,
+ int qm_length,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ unsigned int qm_buffer[16];
+
+ assert(qm_length<= 16);
+ assert(sizeof(*qm) == 4);
+ memset(qm_buffer,0,16*4);
+ memcpy(qm_buffer, qm, qm_length * 4);
+
+ BEGIN_BCS_BATCH(batch, 18);
+ OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
+ OUT_BCS_BATCH(batch, qm_type<< 0);
+ intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_qm_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ VAEncSequenceParameterBufferH264 *seq_param = avc_state->seq_param;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+
+ /* TODO: add support for non flat matrix */
+ const unsigned int *qm_4x4_intra;
+ const unsigned int *qm_4x4_inter;
+ const unsigned int *qm_8x8_intra;
+ const unsigned int *qm_8x8_inter;
+
+ if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag
+&& !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {
+ qm_4x4_intra = qm_4x4_inter = qm_8x8_intra = qm_8x8_inter = qm_flat;
+ } else {
+ VAIQMatrixBufferH264 *qm;
+ assert(encode_state->q_matrix&& encode_state->q_matrix->buffer);
+ qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
+ qm_4x4_intra = (unsigned int *)qm->ScalingList4x4[0];
+ qm_4x4_inter = (unsigned int *)qm->ScalingList4x4[3];
+ qm_8x8_intra = (unsigned int *)qm->ScalingList8x8[0];
+ qm_8x8_inter = (unsigned int *)qm->ScalingList8x8[1];
+ }
+
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm_4x4_intra, 12, encoder_context);
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm_4x4_inter, 12, encoder_context);
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm_8x8_intra, 16, encoder_context);
+ gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm_8x8_inter, 16, encoder_context);
+}
+
+static void
+gen9_mfc_fqm_state(VADriverContextP ctx,
+ int fqm_type,
+ const unsigned int *fqm,
+ int fqm_length,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ unsigned int fqm_buffer[32];
+
+ assert(fqm_length<= 32);
+ assert(sizeof(*fqm) == 4);
+ memset(fqm_buffer,0,32*4);
+ memcpy(fqm_buffer, fqm, fqm_length * 4);
+
+ BEGIN_BCS_BATCH(batch, 34);
+ OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
+ OUT_BCS_BATCH(batch, fqm_type<< 0);
+ intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_fill_fqm(uint8_t *qm, uint16_t *fqm, int len)
+{
+ int i, j;
+ for (i = 0; i< len; i++)
+ for (j = 0; j< len; j++)
+ fqm[i * len + j] = (1<< 16) / qm[j * len + i];
+}
+
+static void
+gen9_mfc_avc_fqm_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ /* TODO: add support for non flat matrix */
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ VAEncSequenceParameterBufferH264 *seq_param = avc_state->seq_param;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+
+ if (!seq_param->seq_fields.bits.seq_scaling_matrix_present_flag
+&& !pic_param->pic_fields.bits.pic_scaling_matrix_present_flag) {
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm_flat, 24, encoder_context);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm_flat, 24, encoder_context);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm_flat, 32, encoder_context);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm_flat, 32, encoder_context);
+ } else {
+ int i;
+ uint32_t fqm[32];
+ VAIQMatrixBufferH264 *qm;
+ assert(encode_state->q_matrix&& encode_state->q_matrix->buffer);
+ qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
+
+ for (i = 0; i< 3; i++)
+ gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * i, 4);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm, 24, encoder_context);
+
+ for (i = 3; i< 6; i++)
+ gen9_mfc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * (i - 3), 4);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm, 24, encoder_context);
+
+ gen9_mfc_fill_fqm(qm->ScalingList8x8[0], (uint16_t *)fqm, 8);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm, 32, encoder_context);
+
+ gen9_mfc_fill_fqm(qm->ScalingList8x8[1], (uint16_t *)fqm, 8);
+ gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm, 32, encoder_context);
+ }
+}
+
+static void
+gen9_mfc_avc_insert_object(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
+ int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
+ int slice_header_indicator,
+ struct intel_batchbuffer *batch)
+{
+ if (data_bits_in_last_dw == 0)
+ data_bits_in_last_dw = 32;
+
+ BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
+
+ OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws));
+ OUT_BCS_BATCH(batch,
+ (0<< 16) | /* always start at offset 0 */
+ (slice_header_indicator<< 14) |
+ (data_bits_in_last_dw<< 8) |
+ (skip_emul_byte_count<< 4) |
+ (!!emulation_flag<< 3) |
+ ((!!is_last_header)<< 2) |
+ ((!!is_end_of_slice)<< 1) |
+ (0<< 0)); /* TODO: check this flag */
+ intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static void
+gen9_mfc_avc_insert_slice_packed_data(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int slice_index,
+ struct intel_batchbuffer *batch)
+{
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int length_in_bits;
+ unsigned int *header_data = NULL;
+ int count, i, start_index;
+ int slice_header_index;
+
+ if (encode_state->slice_header_index[slice_index] == 0)
+ slice_header_index = -1;
+ else
+ slice_header_index = (encode_state->slice_header_index[slice_index]& SLICE_PACKED_DATA_INDEX_MASK);
+
+ count = encode_state->slice_rawdata_count[slice_index];
+ start_index = (encode_state->slice_rawdata_index[slice_index]& SLICE_PACKED_DATA_INDEX_MASK);
+
+ for (i = 0; i< count; i++) {
+ unsigned int skip_emul_byte_cnt;
+
+ header_data = (unsigned int *)encode_state->packed_header_data_ext[start_index + i]->buffer;
+
+ param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[start_index + i]->buffer);
+
+ /* skip the slice header packed data type as it is lastly inserted */
+ if (param->type == VAEncPackedHeaderSlice)
+ continue;
+
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+
+ /* as the slice header is still required, the last header flag is set to
+ * zero.
+ */
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ }
+
+ if (slice_header_index == -1) {
+ VAEncSequenceParameterBufferH264 *seq_param = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+ VAEncSliceParameterBufferH264 *slice_params = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
+ unsigned char *slice_header = NULL;
+ int slice_header_length_in_bits = 0;
+
+ /* No slice header data is passed. And the driver needs to generate it */
+ /* For the Normal H264 */
+ slice_header_length_in_bits = build_avc_slice_header(seq_param,
+ pic_param,
+ slice_params,
+&slice_header);
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ (unsigned int *)slice_header,
+ ALIGN(slice_header_length_in_bits, 32)>> 5,
+ slice_header_length_in_bits& 0x1f,
+ 5, /* first 5 bytes are start code + nal unit type */
+ 1, 0, 1,
+ 1,
+ batch);
+
+ free(slice_header);
+ } else {
+ unsigned int skip_emul_byte_cnt;
+
+ header_data = (unsigned int *)encode_state->packed_header_data_ext[slice_header_index]->buffer;
+
+ param = (VAEncPackedHeaderParameterBuffer *)(encode_state->packed_header_params_ext[slice_header_index]->buffer);
+ length_in_bits = param->bit_length;
+
+ /* as the slice header is the last header data for one slice,
+ * the last header flag is set to one.
+ */
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 1,
+ 0,
+ !param->has_emulation_bytes,
+ 1,
+ batch);
+ }
+
+ return;
+}
+
+static void
+gen9_mfc_avc_inset_headers(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ int slice_index,
+ struct intel_batchbuffer *batch)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SPS);
+ unsigned int internal_rate_mode = generic_state->internal_rate_mode;
+ unsigned int skip_emul_byte_cnt;
+
+ if (slice_index == 0) {
+ if (encode_state->packed_header_data[idx]) {
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
+ unsigned int length_in_bits;
+
+ assert(encode_state->packed_header_param[idx]);
+ param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ }
+
+ idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_PPS);
+
+ if (encode_state->packed_header_data[idx]) {
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
+ unsigned int length_in_bits;
+
+ assert(encode_state->packed_header_param[idx]);
+ param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ }
+
+ idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SEI);
+
+ if (encode_state->packed_header_data[idx]) {
+ VAEncPackedHeaderParameterBuffer *param = NULL;
+ unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
+ unsigned int length_in_bits;
+
+ assert(encode_state->packed_header_param[idx]);
+ param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
+ length_in_bits = param->bit_length;
+
+ skip_emul_byte_cnt = intel_avc_find_skipemulcnt((unsigned char *)header_data, length_in_bits);
+ gen9_mfc_avc_insert_object(ctx,
+ encoder_context,
+ header_data,
+ ALIGN(length_in_bits, 32)>> 5,
+ length_in_bits& 0x1f,
+ skip_emul_byte_cnt,
+ 0,
+ 0,
+ !param->has_emulation_bytes,
+ 0,
+ batch);
+ } else if (internal_rate_mode == VA_RC_CBR) {
+ /* TODO: insert others */
+ }
+ }
+
+ gen9_mfc_avc_insert_slice_packed_data(ctx,
+ encode_state,
+ encoder_context,
+ slice_index,
+ batch);
+}
+
+static void
+gen9_mfc_avc_slice_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncPictureParameterBufferH264 *pic_param,
+ VAEncSliceParameterBufferH264 *slice_param,
+ VAEncSliceParameterBufferH264 *next_slice_param,
+ struct intel_batchbuffer *batch)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
+ unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
+ unsigned char correct[6], grow, shrink;
+ int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
+ int max_qp_n, max_qp_p;
+ int i;
+ int weighted_pred_idc = 0;
+ int num_ref_l0 = 0, num_ref_l1 = 0;
+ int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+ int slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+ unsigned int rc_panic_enable = 0;
+ unsigned int rate_control_counter_enable = 0;
+ unsigned int rounding_value = 0;
+ unsigned int rounding_inter_enable = 0;
+
+ //check the inter rounding
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ if(avc_state->rounding_inter_p == AVC_INVALID_ROUNDING_VALUE)
+ {
+ if(avc_state->adaptive_rounding_inter_enable&& !(generic_state->brc_enabled))
+ {
+ if(generic_state->gop_ref_distance == 1)
+ avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p_without_b[slice_qp];
+ else
+ avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_p[slice_qp];
+ }
+ else
+ {
+ avc_state->rounding_value = gen9_avc_inter_rounding_p[generic_state->preset];
+ }
+
+ }else
+ {
+ avc_state->rounding_value = avc_state->rounding_inter_p;
+ }
+ }else if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ if(pic_param->pic_fields.bits.reference_pic_flag)
+ {
+ if(avc_state->rounding_inter_b_ref == AVC_INVALID_ROUNDING_VALUE)
+ avc_state->rounding_value = gen9_avc_inter_rounding_b_ref[generic_state->preset];
+ else
+ avc_state->rounding_value = avc_state->rounding_inter_b_ref;
+ }
+ else
+ {
+ if(avc_state->rounding_inter_b == AVC_INVALID_ROUNDING_VALUE)
+ {
+ if(avc_state->adaptive_rounding_inter_enable&& !(generic_state->brc_enabled))
+ avc_state->rounding_value = gen9_avc_adaptive_inter_rounding_b[slice_qp];
+ else
+ avc_state->rounding_value = gen9_avc_inter_rounding_b[generic_state->preset];
+ }else
+ {
+ avc_state->rounding_value = avc_state->rounding_inter_b;
+ }
+ }
+ }
+
+ slice_hor_pos = slice_param->macroblock_address % generic_state->frame_width_in_mbs;
+ slice_ver_pos = slice_param->macroblock_address / generic_state->frame_height_in_mbs;
+
+ if (next_slice_param) {
+ next_slice_hor_pos = next_slice_param->macroblock_address % generic_state->frame_width_in_mbs;
+ next_slice_ver_pos = next_slice_param->macroblock_address / generic_state->frame_height_in_mbs;
+ } else {
+ next_slice_hor_pos = 0;
+ next_slice_ver_pos = generic_state->frame_height_in_mbs;
+ }
+
+ if (slice_type == SLICE_TYPE_I) {
+ luma_log2_weight_denom = 0;
+ chroma_log2_weight_denom = 0;
+ } else if (slice_type == SLICE_TYPE_P) {
+ weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
+ num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
+ rounding_inter_enable = avc_state->rounding_inter_enable;
+ rounding_value = avc_state->rounding_value;
+
+ if (slice_param->num_ref_idx_active_override_flag)
+ num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
+ } else if (slice_type == SLICE_TYPE_B) {
+ weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
+ num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
+ num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
+ rounding_inter_enable = avc_state->rounding_inter_enable;
+ rounding_value = avc_state->rounding_value;
+
+ if (slice_param->num_ref_idx_active_override_flag) {
+ num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
+ num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
+ }
+
+ if (weighted_pred_idc == 2) {
+ /* 8.4.3 - Derivation process for prediction weights (8-279) */
+ luma_log2_weight_denom = 5;
+ chroma_log2_weight_denom = 5;
+ }
+ }
+
+ max_qp_n = 0; /* TODO: update it */
+ max_qp_p = 0; /* TODO: update it */
+ grow = 0; /* TODO: update it */
+ shrink = 0; /* TODO: update it */
+
+ rate_control_counter_enable = (generic_state->brc_enabled&& (generic_state->curr_pak_pass != 0));
+ rc_panic_enable = (avc_state->rc_panic_enable&&
+ (!avc_state->min_max_qp_enable)&&
+ (encoder_context->rate_control_mode != VA_RC_CQP)&&
+ (generic_state->curr_pak_pass == (generic_state->num_pak_passes - 1)));
+
+ for (i = 0; i< 6; i++)
+ correct[i] = 0; /* TODO: update it */
+
+ BEGIN_BCS_BATCH(batch, 11);
+
+ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
+ OUT_BCS_BATCH(batch, slice_type);
+ OUT_BCS_BATCH(batch,
+ (num_ref_l1<< 24) |
+ (num_ref_l0<< 16) |
+ (chroma_log2_weight_denom<< 8) |
+ (luma_log2_weight_denom<< 0));
+ OUT_BCS_BATCH(batch,
+ (weighted_pred_idc<< 30) |
+ (((slice_type == SLICE_TYPE_B)?slice_param->direct_spatial_mv_pred_flag:0)<< 29) |
+ (slice_param->disable_deblocking_filter_idc<< 27) |
+ (slice_param->cabac_init_idc<< 24) |
+ (slice_qp<< 16) |
+ ((slice_param->slice_beta_offset_div2& 0xf)<< 8) |
+ ((slice_param->slice_alpha_c0_offset_div2& 0xf)<< 0));
+
+ OUT_BCS_BATCH(batch,
+ slice_ver_pos<< 24 |
+ slice_hor_pos<< 16 |
+ slice_param->macroblock_address);
+ OUT_BCS_BATCH(batch,
+ next_slice_ver_pos<< 16 |
+ next_slice_hor_pos);
+
+ OUT_BCS_BATCH(batch,
+ (rate_control_counter_enable<< 31) | /* TODO: ignore it for VDENC ??? */
+ (1<< 30) | /* ResetRateControlCounter */
+ (2<< 28) | /* Loose Rate Control */
+ (0<< 24) | /* RC Stable Tolerance */
+ (rc_panic_enable<< 23) | /* RC Panic Enable */
+ (1<< 22) | /* CBP mode */
+ (0<< 21) | /* MB Type Direct Conversion, 0: Enable, 1: Disable */
+ (0<< 20) | /* MB Type Skip Conversion, 0: Enable, 1: Disable */
+ (!next_slice_param<< 19) | /* Is Last Slice */
+ (0<< 18) | /* BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable */
+ (1<< 17) | /* HeaderPresentFlag */
+ (1<< 16) | /* SliceData PresentFlag */
+ (0<< 15) | /* TailPresentFlag, TODO: check it on VDEnc */
+ (1<< 13) | /* RBSP NAL TYPE */
+ (1<< 12)); /* CabacZeroWordInsertionEnable */
+
+ OUT_BCS_BATCH(batch, generic_ctx->compressed_bitstream.start_offset);
+
+ OUT_BCS_BATCH(batch,
+ (max_qp_n<< 24) | /*Target QP - 24 is lowest QP*/
+ (max_qp_p<< 16) | /*Target QP + 20 is highest QP*/
+ (shrink<< 8) |
+ (grow<< 0));
+ OUT_BCS_BATCH(batch,
+ (rounding_inter_enable<< 31) |
+ (rounding_value<< 28) |
+ (1<< 27) |
+ (5<< 24) |
+ (correct[5]<< 20) |
+ (correct[4]<< 16) |
+ (correct[3]<< 12) |
+ (correct[2]<< 8) |
+ (correct[1]<< 4) |
+ (correct[0]<< 0));
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
+}
+
+static uint8_t
+gen9_mfc_avc_get_ref_idx_state(VAPictureH264 *va_pic, unsigned int frame_store_id)
+{
+ unsigned int is_long_term =
+ !!(va_pic->flags& VA_PICTURE_H264_LONG_TERM_REFERENCE);
+ unsigned int is_top_field =
+ !!(va_pic->flags& VA_PICTURE_H264_TOP_FIELD);
+ unsigned int is_bottom_field =
+ !!(va_pic->flags& VA_PICTURE_H264_BOTTOM_FIELD);
+
+ return ((is_long_term<< 6) |
+ (0<< 5) |
+ (frame_store_id<< 1) |
+ ((is_top_field ^ 1)& is_bottom_field));
+}
+
+static void
+gen9_mfc_avc_ref_idx_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ struct intel_batchbuffer *batch)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ VAPictureH264 *ref_pic;
+ int i, slice_type, ref_idx_shift;
+ unsigned int fwd_ref_entry;
+ unsigned int bwd_ref_entry;
+
+ /* max 4 ref frames are allowed for l0 and l1 */
+ fwd_ref_entry = 0x80808080;
+ slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+
+ if ((slice_type == SLICE_TYPE_P) ||
+ (slice_type == SLICE_TYPE_B)) {
+ for (i = 0; i< avc_state->num_refs[0]; i++) {
+ ref_pic =&slice_param->RefPicList0[i];
+ ref_idx_shift = i * 8;
+
+ fwd_ref_entry&= ~(0xFF<< ref_idx_shift);
+ fwd_ref_entry += (gen9_mfc_avc_get_ref_idx_state(ref_pic, avc_state->list_ref_idx[0][i])<< ref_idx_shift);
+ }
+ }
+
+ bwd_ref_entry = 0x80808080;
+ if (slice_type == SLICE_TYPE_B) {
+ for (i = 0; i< avc_state->num_refs[1]; i++) {
+ ref_pic =&slice_param->RefPicList1[i];
+ ref_idx_shift = i * 8;
+
+ bwd_ref_entry&= ~(0xFF<< ref_idx_shift);
+ bwd_ref_entry += (gen9_mfc_avc_get_ref_idx_state(ref_pic, avc_state->list_ref_idx[1][i])<< ref_idx_shift);
+ }
+ }
+
+ if ((slice_type == SLICE_TYPE_P) ||
+ (slice_type == SLICE_TYPE_B)) {
+ BEGIN_BCS_BATCH(batch, 10);
+ OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
+ OUT_BCS_BATCH(batch, 0); // L0
+ OUT_BCS_BATCH(batch, fwd_ref_entry);
+
+ for (i = 0; i< 7; i++) {
+ OUT_BCS_BATCH(batch, 0x80808080);
+ }
+
+ ADVANCE_BCS_BATCH(batch);
+ }
+
+ if (slice_type == SLICE_TYPE_B) {
+ BEGIN_BCS_BATCH(batch, 10);
+ OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
+ OUT_BCS_BATCH(batch, 1); //Select L1
+ OUT_BCS_BATCH(batch, bwd_ref_entry); //max 4 reference allowed
+ for(i = 0; i< 7; i++) {
+ OUT_BCS_BATCH(batch, 0x80808080);
+ }
+ ADVANCE_BCS_BATCH(batch);
+ }
+}
+
+static void
+gen9_mfc_avc_weightoffset_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncPictureParameterBufferH264 *pic_param,
+ VAEncSliceParameterBufferH264 *slice_param,
+ struct intel_batchbuffer *batch)
+{
+ int i, slice_type;
+ short weightoffsets[32 * 6];
+
+ slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+
+ if (slice_type == SLICE_TYPE_P&&
+ pic_param->pic_fields.bits.weighted_pred_flag == 1) {
+ memset(weightoffsets,0,32*6 * sizeof(short));
+ for (i = 0; i< 32; i++) {
+ weightoffsets[i * 6 + 0] = slice_param->luma_weight_l0[i];
+ weightoffsets[i * 6 + 1] = slice_param->luma_offset_l0[i];
+ weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l0[i][0];
+ weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l0[i][0];
+ weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l0[i][1];
+ weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l0[i][1];
+ }
+
+ BEGIN_BCS_BATCH(batch, 98);
+ OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
+
+ ADVANCE_BCS_BATCH(batch);
+ }
+
+ if (slice_type == SLICE_TYPE_B&&
+ (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
+ memset(weightoffsets,0,32*6 * sizeof(short));
+ for (i = 0; i< 32; i++) {
+ weightoffsets[i * 6 + 0] = slice_param->luma_weight_l0[i];
+ weightoffsets[i * 6 + 1] = slice_param->luma_offset_l0[i];
+ weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l0[i][0];
+ weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l0[i][0];
+ weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l0[i][1];
+ weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l0[i][1];
+ }
+
+ BEGIN_BCS_BATCH(batch, 98);
+ OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
+ ADVANCE_BCS_BATCH(batch);
+
+ memset(weightoffsets,0,32*6 * sizeof(short));
+ for (i = 0; i< 32; i++) {
+ weightoffsets[i * 6 + 0] = slice_param->luma_weight_l1[i];
+ weightoffsets[i * 6 + 1] = slice_param->luma_offset_l1[i];
+ weightoffsets[i * 6 + 2] = slice_param->chroma_weight_l1[i][0];
+ weightoffsets[i * 6 + 3] = slice_param->chroma_offset_l1[i][0];
+ weightoffsets[i * 6 + 4] = slice_param->chroma_weight_l1[i][1];
+ weightoffsets[i * 6 + 5] = slice_param->chroma_offset_l1[i][1];
+ }
+
+ BEGIN_BCS_BATCH(batch, 98);
+ OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
+ OUT_BCS_BATCH(batch, 1);
+ intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
+ ADVANCE_BCS_BATCH(batch);
+ }
+}
+
+static void
+gen9_mfc_avc_single_slice(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ VAEncSliceParameterBufferH264 *slice_param,
+ VAEncSliceParameterBufferH264 *next_slice_param,
+ int slice_index)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct intel_batchbuffer *slice_batch = avc_ctx->pres_slice_batch_buffer_2nd_level;
+ VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+ struct gpe_mi_batch_buffer_start_parameter second_level_batch;
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+
+ unsigned int slice_offset = 0;
+
+ if(generic_state->curr_pak_pass == 0)
+ {
+ slice_offset = intel_batchbuffer_used_size(slice_batch);
+ avc_state->slice_batch_offset[slice_index] = slice_offset;
+ gen9_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context, slice_param,slice_batch);
+ gen9_mfc_avc_weightoffset_state(ctx,
+ encode_state,
+ encoder_context,
+ pic_param,
+ slice_param,
+ slice_batch);
+ gen9_mfc_avc_slice_state(ctx,
+ encode_state,
+ encoder_context,
+ pic_param,
+ slice_param,
+ next_slice_param,
+ slice_batch);
+ gen9_mfc_avc_inset_headers(ctx,
+ encode_state,
+ encoder_context,
+ slice_param,
+ slice_index,
+ slice_batch);
+
+ BEGIN_BCS_BATCH(slice_batch, 2);
+ OUT_BCS_BATCH(slice_batch, 0);
+ OUT_BCS_BATCH(slice_batch, MI_BATCH_BUFFER_END);
+ ADVANCE_BCS_BATCH(slice_batch);
+
+ }else
+ {
+ slice_offset = avc_state->slice_batch_offset[slice_index];
+ }
+ /* insert slice as second levle.*/
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ second_level_batch.is_second_level = 1; /* Must be the second level batch buffer */
+ second_level_batch.offset = slice_offset;
+ second_level_batch.bo = slice_batch->buffer;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch,&second_level_batch);
+
+ /* insert mb code as second levle.*/
+ obj_surface = encode_state->reconstructed_object;
+ assert(obj_surface->private_data);
+ avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
+
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ second_level_batch.is_second_level = 1; /* Must be the second level batch buffer */
+ second_level_batch.offset = slice_param->macroblock_address * 16 * 4;
+ second_level_batch.bo = avc_priv_surface->res_mb_code_surface.bo;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch,&second_level_batch);
+
+}
+
+static void
+gen9_avc_pak_slice_level(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct gpe_mi_flush_dw_parameter mi_flush_dw_params;
+ VAEncSliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
+ int i, j;
+ int slice_index = 0;
+ int is_frame_level = 1; /* TODO: check it for SKL,now single slice per frame */
+ int has_tail = 0; /* TODO: check it later */
+
+ for (j = 0; j< encode_state->num_slice_params_ext; j++) {
+ slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
+
+ if (j == encode_state->num_slice_params_ext - 1)
+ next_slice_group_param = NULL;
+ else
+ next_slice_group_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j + 1]->buffer;
+
+ for (i = 0; i< encode_state->slice_params_ext[j]->num_elements; i++) {
+ if (i< encode_state->slice_params_ext[j]->num_elements - 1)
+ next_slice_param = slice_param + 1;
+ else
+ next_slice_param = next_slice_group_param;
+
+ gen9_mfc_avc_single_slice(ctx,
+ encode_state,
+ encoder_context,
+ slice_param,
+ next_slice_param,
+ slice_index);
+ slice_param++;
+ slice_index++;
+
+ if (is_frame_level)
+ break;
+ else {
+ /* TODO: remove assert(0) and add other commands here */
+ assert(0);
+ }
+ }
+
+ if (is_frame_level)
+ break;
+ }
+
+ if (has_tail) {
+ /* TODO: insert a tail if required */
+ }
+
+ memset(&mi_flush_dw_params, 0, sizeof(mi_flush_dw_params));
+ mi_flush_dw_params.video_pipeline_cache_invalidate = 1;
+ gen8_gpe_mi_flush_dw(ctx, batch,&mi_flush_dw_params);
+}
+static void
+gen9_avc_pak_picture_level(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct gpe_mi_batch_buffer_start_parameter second_level_batch;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ if (generic_state->brc_enabled&&
+ generic_state->curr_pak_pass) {
+ struct gpe_mi_conditional_batch_buffer_end_parameter mi_conditional_batch_buffer_end_params;
+ struct encoder_status_buffer_internal *status_buffer;
+ status_buffer =&(avc_ctx->status_buffer);
+
+ memset(&mi_conditional_batch_buffer_end_params, 0, sizeof(mi_conditional_batch_buffer_end_params));
+ mi_conditional_batch_buffer_end_params.offset = status_buffer->image_status_mask_offset;
+ mi_conditional_batch_buffer_end_params.bo = status_buffer->bo;
+ mi_conditional_batch_buffer_end_params.compare_data = 0;
+ mi_conditional_batch_buffer_end_params.compare_mask_mode_disabled = 0;
+ gen9_gpe_mi_conditional_batch_buffer_end(ctx, batch,&mi_conditional_batch_buffer_end_params);
+ }
+
+ gen9_mfc_avc_pipe_mode_select(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_surface_state(ctx,encoder_context,&(generic_ctx->res_reconstructed_surface),0);
+ gen9_mfc_avc_surface_state(ctx,encoder_context,&(generic_ctx->res_uncompressed_input_surface),4);
+ gen9_mfc_avc_pipe_buf_addr_state(ctx,encoder_context);
+ gen9_mfc_avc_ind_obj_base_addr_state(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_bsp_buf_base_addr_state(ctx,encoder_context);
+
+ if(generic_state->brc_enabled)
+ {
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ if (generic_state->curr_pak_pass == 0) {
+ second_level_batch.offset = 0;
+ } else {
+ second_level_batch.offset = generic_state->curr_pak_pass * INTEL_AVC_IMAGE_STATE_CMD_SIZE;
+ }
+ second_level_batch.is_second_level = 1;
+ second_level_batch.bo = avc_ctx->res_brc_image_state_read_buffer.bo;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch,&second_level_batch);
+ }else
+ {
+ /*generate a new image state */
+ gen9_avc_set_image_state_non_brc(ctx,encode_state,encoder_context,&(avc_ctx->res_image_state_batch_buffer_2nd_level));
+ memset(&second_level_batch, 0, sizeof(second_level_batch));
+ second_level_batch.offset = 0;
+ second_level_batch.is_second_level = 1;
+ second_level_batch.bo = avc_ctx->res_image_state_batch_buffer_2nd_level.bo;
+ gen8_gpe_mi_batch_buffer_start(ctx, batch,&second_level_batch);
+ }
+
+ gen9_mfc_avc_qm_state(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_fqm_state(ctx,encode_state,encoder_context);
+ gen9_mfc_avc_directmode_state(ctx,encoder_context);
+
+}
+
+static void
+gen9_avc_read_mfc_status(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+
+ struct gpe_mi_store_register_mem_parameter mi_store_reg_mem_param;
+ struct gpe_mi_store_data_imm_parameter mi_store_data_imm_param;
+ struct gpe_mi_flush_dw_parameter mi_flush_dw_param;
+ struct encoder_status_buffer_internal *status_buffer;
+
+ status_buffer =&(avc_ctx->status_buffer);
+
+ memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
+ gen8_gpe_mi_flush_dw(ctx, batch,&mi_flush_dw_param);
+
+ /* read register and store into status_buffer and pak_statitistic info */
+ memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->bs_byte_count_frame_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->bs_byte_count_frame_nh_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_nh_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->mfc_qp_status_count_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->mfc_qp_status_count_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ mi_store_reg_mem_param.bo = status_buffer->bo;
+ mi_store_reg_mem_param.offset = status_buffer->image_status_mask_offset;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->image_status_mask_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ /*update the status in the pak_statistic_surface */
+ mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_reg_mem_param.offset = 0;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_reg_mem_param.offset = 4;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->bs_byte_count_frame_nh_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ memset(&mi_store_data_imm_param, 0, sizeof(mi_store_data_imm_param));
+ mi_store_data_imm_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_data_imm_param.offset = sizeof(unsigned int) * 2;
+ mi_store_data_imm_param.dw0 = (generic_state->curr_pak_pass + 1);
+ gen8_gpe_mi_store_data_imm(ctx, batch,&mi_store_data_imm_param);
+
+ mi_store_reg_mem_param.bo = avc_ctx->res_brc_pre_pak_statistics_output_buffer.bo;
+ mi_store_reg_mem_param.offset = sizeof(unsigned int) * (4 + generic_state->curr_pak_pass) ;
+ mi_store_reg_mem_param.mmio_offset = status_buffer->image_status_ctrl_reg_offset;
+ gen8_gpe_mi_store_register_mem(ctx, batch,&mi_store_reg_mem_param);
+
+ memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
+ gen8_gpe_mi_flush_dw(ctx, batch,&mi_flush_dw_param);
+
+ return;
+}
+
+static void
+gen9_avc_pak_brc_prepare(struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ unsigned int rate_control_mode = encoder_context->rate_control_mode;
+
+ switch (rate_control_mode& 0x7f) {
+ generic_state->internal_rate_mode = VA_RC_CBR;
+ break;
+
+ generic_state->internal_rate_mode = VA_RC_VBR;//AVBR
+ break;
+
+ generic_state->internal_rate_mode = VA_RC_CQP;
+ break;
+ }
+
+}
+
+static VAStatus
+gen9_avc_pak_pipeline_prepare(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus va_status;
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )pak_context->private_enc_state;
+
+ struct object_surface *obj_surface;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+ VAEncSliceParameterBufferH264 *slice_param = avc_state->slice_param[0];
+
+ struct gen9_surface_avc *avc_priv_surface;
+ int i, j, enable_avc_ildb = 0;
+ unsigned int allocate_flag = 1;
+ unsigned int size;
+ unsigned int w_mb = generic_state->frame_width_in_mbs;
+ unsigned int h_mb = generic_state->frame_height_in_mbs;
+ struct avc_surface_param surface_param;
+
+ /* update the parameter and check slice parameter */
+ for (j = 0; j< encode_state->num_slice_params_ext&& enable_avc_ildb == 0; j++) {
+ assert(encode_state->slice_params_ext&& encode_state->slice_params_ext[j]->buffer);
+ slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
+
+ for (i = 0; i< encode_state->slice_params_ext[j]->num_elements; i++) {
+ assert((slice_param->slice_type == SLICE_TYPE_I) ||
+ (slice_param->slice_type == SLICE_TYPE_SI) ||
+ (slice_param->slice_type == SLICE_TYPE_P) ||
+ (slice_param->slice_type == SLICE_TYPE_SP) ||
+ (slice_param->slice_type == SLICE_TYPE_B));
+
+ if (slice_param->disable_deblocking_filter_idc != 1) {
+ enable_avc_ildb = 1;
+ break;
+ }
+
+ slice_param++;
+ }
+ }
+ avc_state->enable_avc_ildb = enable_avc_ildb;
+
+ /* setup the all surface and buffer for PAK */
+ /* Setup current reconstruct frame */
+ obj_surface = encode_state->reconstructed_object;
+ va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
+
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ memset(&surface_param,0,sizeof(surface_param));
+ surface_param.frame_width = generic_state->frame_width_in_pixel;
+ surface_param.frame_height = generic_state->frame_height_in_pixel;
+ va_status = gen9_avc_init_check_surfaces(ctx,
+ obj_surface,encoder_context,
+&surface_param);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ /* init the member of avc_priv_surface,frame_store_id,qp_value */
+ {
+ avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = 0;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = 0;
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2]);
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1]);
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-2],avc_priv_surface->dmv_top);
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS-1],avc_priv_surface->dmv_bottom);
+ dri_bo_reference(avc_priv_surface->dmv_top);
+ dri_bo_reference(avc_priv_surface->dmv_bottom);
+ avc_priv_surface->qp_value = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+ avc_priv_surface->frame_store_id = 0;
+ avc_priv_surface->frame_idx = pic_param->CurrPic.frame_idx;
+ avc_priv_surface->top_field_order_cnt = pic_param->CurrPic.TopFieldOrderCnt;
+ avc_priv_surface->is_as_ref = pic_param->pic_fields.bits.reference_pic_flag;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-2] = avc_priv_surface->top_field_order_cnt;
+ avc_state->top_field_poc[NUM_MFC_AVC_DMV_BUFFERS-1] = avc_priv_surface->top_field_order_cnt + 1;
+ }
+ i965_free_gpe_resource(&generic_ctx->res_reconstructed_surface);
+ i965_free_gpe_resource(&avc_ctx->res_post_deblocking_output);
+ i965_free_gpe_resource(&avc_ctx->res_pre_deblocking_output);
+ i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_reconstructed_surface, obj_surface);
+
+
+ if (avc_state->enable_avc_ildb) {
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_post_deblocking_output, obj_surface);
+ } else {
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_pre_deblocking_output, obj_surface);
+ }
+ /* input YUV surface */
+ obj_surface = encode_state->input_yuv_object;
+ va_status = i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
+
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ i965_free_gpe_resource(&generic_ctx->res_uncompressed_input_surface);
+ i965_object_surface_to_2d_gpe_resource_with_align(&generic_ctx->res_uncompressed_input_surface, obj_surface);
+
+ /* Reference surfaces */
+ for (i = 0; i< ARRAY_ELEMS(avc_ctx->list_reference_res); i++) {
+ i965_free_gpe_resource(&avc_ctx->list_reference_res[i]);
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2]);
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1]);
+ obj_surface = encode_state->reference_objects[i];
+ avc_state->top_field_poc[2*i] = 0;
+ avc_state->top_field_poc[2*i+1] = 0;
+
+ if (obj_surface&& obj_surface->bo) {
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->list_reference_res[i], obj_surface);
+
+ /* actually it should be handled when it is reconstructed surface */
+ va_status = gen9_avc_init_check_surfaces(ctx,
+ obj_surface,encoder_context,
+&surface_param);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+ avc_priv_surface = (struct gen9_surface_avc *)obj_surface->private_data;
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2],avc_priv_surface->dmv_top);
+ i965_dri_object_to_buffer_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i*2 + 1],avc_priv_surface->dmv_bottom);
+ dri_bo_reference(avc_priv_surface->dmv_top);
+ dri_bo_reference(avc_priv_surface->dmv_bottom);
+ avc_priv_surface->frame_store_id = i;
+ avc_state->top_field_poc[2*i] = avc_priv_surface->top_field_order_cnt;
+ avc_state->top_field_poc[2*i+1] = avc_priv_surface->top_field_order_cnt+1;
+ }else
+ {
+ break;
+ }
+ }
+
+ if (avc_ctx->pres_slice_batch_buffer_2nd_level)
+ intel_batchbuffer_free(avc_ctx->pres_slice_batch_buffer_2nd_level);
+
+ avc_ctx->pres_slice_batch_buffer_2nd_level =
+ intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
+ 4096 *
+ encode_state->num_slice_params_ext);
+ if (!avc_ctx->pres_slice_batch_buffer_2nd_level)
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+
+ for (i = 0;i< MAX_AVC_SLICE_NUM;i++) {
+ avc_state->slice_batch_offset[i] = 0;
+ }
+
+
+ size = w_mb * 64;
+ i965_free_gpe_resource(&avc_ctx->res_intra_row_store_scratch_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_intra_row_store_scratch_buffer,
+ size,
+ "PAK Intra row store scratch buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = w_mb * 4 * 64;
+ i965_free_gpe_resource(&avc_ctx->res_deblocking_filter_row_store_scratch_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_deblocking_filter_row_store_scratch_buffer,
+ size,
+ "PAK Deblocking filter row store scratch buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = w_mb * 2 * 64;
+ i965_free_gpe_resource(&avc_ctx->res_bsd_mpc_row_store_scratch_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_bsd_mpc_row_store_scratch_buffer,
+ size,
+ "PAK BSD/MPC row store scratch buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = w_mb * h_mb * 16;
+ i965_free_gpe_resource(&avc_ctx->res_pak_mb_status_buffer);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_pak_mb_status_buffer,
+ size,
+ "PAK MB status buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ return VA_STATUS_SUCCESS;
+
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
+
+static VAStatus
+gen9_avc_encode_picture(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus va_status;
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+
+ va_status = gen9_avc_pak_pipeline_prepare(ctx, encode_state, encoder_context);
+
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+
Please check whether the below logic is correct.
It seems that it uses the GPU command of conditional end for the
subsequent pass. In such case all the commands should be put into one
batch buffer and it is submitted only once.
But the current logic causes that it is submitted multiple times.
[Pengfei] good comments. It will be fixed.
Post by Pengfei Qu
+ for (generic_state->curr_pak_pass = 0;
+ generic_state->curr_pak_pass< generic_state->num_pak_passes;
+ generic_state->curr_pak_pass++) {
+
+ if (i965->intel.has_bsd2)
+ intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+ else
+ intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
+ intel_batchbuffer_emit_mi_flush(batch);
+
+ if (generic_state->curr_pak_pass == 0) {
+ /* Initialize the avc Image Ctrl reg for the first pass,write 0 to staturs/control register, is it needed in AVC? */
+ struct gpe_mi_load_register_imm_parameter mi_load_reg_imm;
+ struct encoder_status_buffer_internal *status_buffer;
+
+ status_buffer =&(avc_ctx->status_buffer);
+ memset(&mi_load_reg_imm, 0, sizeof(mi_load_reg_imm));
+ mi_load_reg_imm.mmio_offset = status_buffer->image_status_ctrl_reg_offset;
+ mi_load_reg_imm.data = 0;
+ gen8_gpe_mi_load_register_imm(ctx, batch,&mi_load_reg_imm);
+ }
+ gen9_avc_pak_picture_level(ctx, encode_state, encoder_context);
+ gen9_avc_pak_slice_level(ctx, encode_state, encoder_context);
+ intel_batchbuffer_emit_mi_flush(batch);
+
+ gen9_avc_read_mfc_status(ctx, encoder_context);
+ intel_batchbuffer_end_atomic(batch);
+ intel_batchbuffer_flush(batch);
+
+ }
+
+ generic_state->seq_frame_number++;
+ generic_state->total_frame_number++;
+ generic_state->first_frame = 0;
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus
+gen9_avc_pak_pipeline(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus vaStatus;
+
+ switch (profile) {
+ vaStatus = gen9_avc_encode_picture(ctx, profile, encode_state, encoder_context);
+ break;
+
+ vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
+ break;
+ }
+
+ return vaStatus;
+}
+
+static void
+gen9_avc_pak_context_destroy(void * context)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )pak_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )pak_context->private_enc_ctx;
+
+ int i = 0;
+
+ if (!pak_context)
+ return;
+
+ // other things
+ i965_free_gpe_resource(&generic_ctx->res_reconstructed_surface);
+ i965_free_gpe_resource(&avc_ctx->res_post_deblocking_output);
+ i965_free_gpe_resource(&avc_ctx->res_pre_deblocking_output);
+ i965_free_gpe_resource(&generic_ctx->res_uncompressed_input_surface);
+
+ i965_free_gpe_resource(&generic_ctx->compressed_bitstream.res);
+ i965_free_gpe_resource(&avc_ctx->res_intra_row_store_scratch_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_deblocking_filter_row_store_scratch_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_bsd_mpc_row_store_scratch_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_pak_mb_status_buffer);
+
+ for(i = 0 ; i< MAX_MFC_AVC_REFERENCE_SURFACES; i++)
+ {
+ i965_free_gpe_resource(&avc_ctx->list_reference_res[i]);
+ }
+
+ for(i = 0 ; i< NUM_MFC_AVC_DMV_BUFFERS; i++)
+ {
+ i965_free_gpe_resource(&avc_ctx->res_direct_mv_buffersr[i]);
+ }
+
+ if (avc_ctx->pres_slice_batch_buffer_2nd_level)
+ {
+ intel_batchbuffer_free(avc_ctx->pres_slice_batch_buffer_2nd_level);
+ avc_ctx->pres_slice_batch_buffer_2nd_level = NULL;
+ }
+
+}
+
+static VAStatus
+gen9_avc_get_coded_status(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ struct i965_coded_buffer_segment *coded_buf_seg)
+{
+ struct encoder_status *avc_encode_status;
+
+ if (!encoder_context || !coded_buf_seg)
+ return VA_STATUS_ERROR_INVALID_BUFFER;
+
+ avc_encode_status = (struct encoder_status *)coded_buf_seg->codec_private_data;
+ coded_buf_seg->base.size = avc_encode_status->bs_byte_count_frame;
+
+ return VA_STATUS_SUCCESS;
+}
+
It will be better that this function is defined in Patch_07.
Post by Pengfei Qu
Add VME pipeline for H264 encoder
[Pengfei] it wll be moved to Patch_07.
Post by Pengfei Qu
+Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ /* VME& PAK share the same context */
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = NULL;
+ struct generic_encoder_context * generic_ctx = NULL;
+ struct gen9_avc_encoder_context * avc_ctx = NULL;
+ struct generic_enc_codec_state * generic_state = NULL;
+ struct avc_enc_state * avc_state = NULL;
+ struct encoder_status_buffer_internal *status_buffer;
+ uint32_t base_offset = offsetof(struct i965_coded_buffer_segment, codec_private_data);
+
+ vme_context = calloc(1, sizeof(struct encoder_vme_mfc_context));
+ generic_ctx = calloc(1, sizeof(struct generic_encoder_context));
+ avc_ctx = calloc(1, sizeof(struct gen9_avc_encoder_context));
+ generic_state = calloc(1, sizeof(struct generic_enc_codec_state));
+ avc_state = calloc(1, sizeof(struct avc_enc_state));
+
+ if(!vme_context || !generic_ctx || !avc_ctx || !generic_state || !avc_state)
+ goto allocate_structure_failed;
+
+ memset(vme_context,0,sizeof(struct encoder_vme_mfc_context));
+ memset(generic_ctx,0,sizeof(struct generic_encoder_context));
+ memset(avc_ctx,0,sizeof(struct gen9_avc_encoder_context));
+ memset(generic_state,0,sizeof(struct generic_enc_codec_state));
+ memset(avc_state,0,sizeof(struct avc_enc_state));
+
+ encoder_context->vme_context = vme_context;
+ vme_context->generic_enc_ctx = generic_ctx;
+ vme_context->private_enc_ctx = avc_ctx;
+ vme_context->generic_enc_state = generic_state;
+ vme_context->private_enc_state = avc_state;
+
+ if (IS_SKL(i965->intel.device_info)) {
+ generic_ctx->enc_kernel_ptr = (void *)skl_avc_encoder_kernels;
+ generic_ctx->enc_kernel_size = sizeof(skl_avc_encoder_kernels);
+ }
+ else
+ goto allocate_structure_failed;
+
+ /* initialize misc ? */
+ avc_ctx->ctx = ctx;
+ generic_ctx->use_hw_scoreboard = 1;
+ generic_ctx->use_hw_non_stalling_scoreboard = 1;
+
+ /* initialize generic state */
+
+ generic_state->kernel_mode = INTEL_ENC_KERNEL_NORMAL;
+ generic_state->preset = INTEL_PRESET_RT_SPEED;
+ generic_state->seq_frame_number = 0;
+ generic_state->total_frame_number = 0;
+ generic_state->frame_type = 0;
+ generic_state->first_frame = 1;
+
+ generic_state->frame_width_in_pixel = 0;
+ generic_state->frame_height_in_pixel = 0;
+ generic_state->frame_width_in_mbs = 0;
+ generic_state->frame_height_in_mbs = 0;
+ generic_state->frame_width_4x = 0;
+ generic_state->frame_height_4x = 0;
+ generic_state->frame_width_16x = 0;
+ generic_state->frame_height_16x = 0;
+ generic_state->frame_width_32x = 0;
+ generic_state->downscaled_width_4x_in_mb = 0;
+ generic_state->downscaled_height_4x_in_mb = 0;
+ generic_state->downscaled_width_16x_in_mb = 0;
+ generic_state->downscaled_height_16x_in_mb = 0;
+ generic_state->downscaled_width_32x_in_mb = 0;
+ generic_state->downscaled_height_32x_in_mb = 0;
+
+ generic_state->hme_supported = 1;
+ generic_state->b16xme_supported = 1;
+ generic_state->b32xme_supported = 0;
+ generic_state->hme_enabled = 0;
+ generic_state->b16xme_enabled = 0;
+ generic_state->b32xme_enabled = 0;
+ generic_state->brc_distortion_buffer_supported = 1;
+ generic_state->brc_constant_buffer_supported = 0;
+
+
+ generic_state->frame_rate = 30;
+ generic_state->brc_allocated = 0;
+ generic_state->brc_inited = 0;
+ generic_state->brc_need_reset = 0;
+ generic_state->is_low_delay = 0;
+ generic_state->brc_enabled = 0;//default
+ generic_state->internal_rate_mode = 0;
+ generic_state->curr_pak_pass = 0;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ generic_state->is_first_pass = 1;
+ generic_state->is_last_pass = 0;
+ generic_state->mb_brc_enabled = 0; // enable mb brc
+ generic_state->brc_roi_enable = 0;
+ generic_state->brc_dirty_roi_enable = 0;
+ generic_state->skip_frame_enbale = 0;
+
+ generic_state->target_bit_rate = 0;
+ generic_state->max_bit_rate = 0;
+ generic_state->min_bit_rate = 0;
+ generic_state->init_vbv_buffer_fullness_in_bit = 0;
+ generic_state->vbv_buffer_size_in_bit = 0;
+ generic_state->frames_per_100s = 0;
+ generic_state->gop_size = 0;
+ generic_state->gop_ref_distance = 0;
+ generic_state->brc_target_size = 0;
+ generic_state->brc_mode = 0;
+ generic_state->brc_init_current_target_buf_full_in_bits = 0.0;
+ generic_state->brc_init_reset_input_bits_per_frame = 0.0;
+ generic_state->brc_init_reset_buf_size_in_bits = 0;
+ generic_state->brc_init_previous_target_buf_full_in_bits = 0;
+ generic_state->window_size = 0;//default
+ generic_state->target_percentage = 0;
+
+ generic_state->avbr_curracy = 0;
+ generic_state->avbr_convergence = 0;
+
+ generic_state->num_skip_frames = 0;
+ generic_state->size_skip_frames = 0;
+
+ generic_state->num_roi = 0;
+ generic_state->max_delta_qp = 0;
+ generic_state->min_delta_qp = 0;
+
+ if (encoder_context->rate_control_mode != VA_RC_NONE&&
+ encoder_context->rate_control_mode != VA_RC_CQP) {
+ generic_state->brc_enabled = 1;
+ generic_state->brc_distortion_buffer_supported = 1;
+ generic_state->brc_constant_buffer_supported = 1;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ }
+ /*avc state initialization */
+ avc_state->mad_enable = 0;
+ avc_state->mb_disable_skip_map_enable = 0;
+ avc_state->sfd_enable = 1;//default
+ avc_state->sfd_mb_enable = 1;//set it true
+ avc_state->adaptive_search_window_enable = 1;//default
+ avc_state->mb_qp_data_enable = 0;
+ avc_state->intra_refresh_i_enable = 0;
+ avc_state->min_max_qp_enable = 0;
+ avc_state->skip_bias_adjustment_enable = 0;//default,same as skip_bias_adjustment_supporte? no
+
+ //external input
+ avc_state->non_ftq_skip_threshold_lut_input_enable = 0;
+ avc_state->ftq_skip_threshold_lut_input_enable = 0;
+ avc_state->ftq_override = 0;
+
+ avc_state->direct_bias_adjustment_enable = 0;
+ avc_state->global_motion_bias_adjustment_enable = 0;
+ avc_state->disable_sub_mb_partion = 0;
+ avc_state->arbitrary_num_mbs_in_slice = 0;
+ avc_state->adaptive_transform_decision_enable = 0;//default
+ avc_state->skip_check_disable = 0;
+ avc_state->tq_enable = 0;
+ avc_state->enable_avc_ildb = 0;
+ avc_state->mbaff_flag = 0;
+ avc_state->enable_force_skip = 1;//default
+ avc_state->rc_panic_enable = 1;//default
+ avc_state->suppress_recon_enable = 1;//default
+
+ avc_state->ref_pic_select_list_supported = 1;
+ avc_state->mb_brc_supported = 1;//?,default
+ avc_state->multi_pre_enable = 1;//default
+ avc_state->ftq_enable = 1;//default
+ avc_state->caf_supported = 1; //default
+ avc_state->caf_enable = 0;
+ avc_state->caf_disable_hd = 1;//default
+ avc_state->skip_bias_adjustment_supported = 1;//default
+
+ avc_state->adaptive_intra_scaling_enable = 1;//default
+ avc_state->old_mode_cost_enable = 0;//default
+ avc_state->multi_ref_qp_enable = 1;//default
+ avc_state->weighted_ref_l0_enable = 1;//default
+ avc_state->weighted_ref_l1_enable = 1;//default
+ avc_state->weighted_prediction_supported = 0;
+ avc_state->brc_split_enable = 0;
+ avc_state->slice_level_report_supported = 0;
+
+ avc_state->fbr_bypass_enable = 1;//default
+ avc_state->field_scaling_output_interleaved = 0;
+ avc_state->mb_variance_output_enable = 0;
+ avc_state->mb_pixel_average_output_enable = 0;
+ avc_state->rolling_intra_refresh_enable = 0;// same as intra_refresh_i_enable?
+ avc_state->mbenc_curbe_set_in_brc_update = 0;
+ avc_state->rounding_inter_enable = 1; //default
+ avc_state->adaptive_rounding_inter_enable = 1;//default
+
+ avc_state->mbenc_i_frame_dist_in_use = 0;
+ avc_state->mb_status_supported = 1; //set in intialization for gen9
+ avc_state->mb_status_enable = 0;
+ avc_state->mb_vproc_stats_enable = 0;
+ avc_state->flatness_check_enable = 0;
+ avc_state->flatness_check_supported = 1;//default
+ avc_state->block_based_skip_enable = 0;
+ avc_state->use_widi_mbenc_kernel = 0;
+ avc_state->kernel_trellis_enable = 0;
+ avc_state->generic_reserved = 0;
+
+ avc_state->rounding_value = 0;
+ avc_state->rounding_inter_p = 255;//default
+ avc_state->rounding_inter_b = 255; //default
+ avc_state->rounding_inter_b_ref = 255; //default
+ avc_state->min_qp_i = INTEL_AVC_MIN_QP;
+ avc_state->min_qp_p = INTEL_AVC_MIN_QP;
+ avc_state->min_qp_b = INTEL_AVC_MIN_QP;
+ avc_state->max_qp_i = INTEL_AVC_MAX_QP;
+ avc_state->max_qp_p = INTEL_AVC_MAX_QP;
+ avc_state->max_qp_b = INTEL_AVC_MAX_QP;
+
+ memset(avc_state->non_ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
+ memset(avc_state->ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
+ memset(avc_state->lamda_value_lut,0,52*2*sizeof(uint8_t));
+
+ avc_state->intra_refresh_qp_threshold = 0;
+ avc_state->trellis_flag = 0;
+ avc_state->hme_mv_cost_scaling_factor = 0;
+ avc_state->slice_height = 1;
+ avc_state->slice_num = 1;
+ memset(avc_state->dist_scale_factor_list0,0,32*sizeof(uint32_t));
+ avc_state->bi_weight = 0;
+ avc_state->brc_const_data_surface_width = 64;
+ avc_state->brc_const_data_surface_height = 44;
+
+ avc_state->num_refs[0] = 0;
+ avc_state->num_refs[1] = 0;
+ memset(avc_state->list_ref_idx,0,32*2*sizeof(uint32_t));
+ memset(avc_state->top_field_poc,0,NUM_MFC_AVC_DMV_BUFFERS*sizeof(int32_t));
+ avc_state->tq_rounding = 0;
+ avc_state->zero_mv_threshold = 0;
+ avc_state->slice_second_levle_batch_buffer_in_use = 0;
+
+ //1. seq/pic/slice
+
+ /* the definition of status buffer offset for Encoder */
+
+ status_buffer =&avc_ctx->status_buffer;
+ memset(status_buffer, 0,sizeof(struct encoder_status_buffer_internal));
+
+ status_buffer->base_offset = base_offset;
+ status_buffer->bs_byte_count_frame_offset = base_offset + offsetof(struct encoder_status, bs_byte_count_frame);
+ status_buffer->bs_byte_count_frame_nh_offset = base_offset + offsetof(struct encoder_status, bs_byte_count_frame_nh);
+ status_buffer->image_status_mask_offset = base_offset + offsetof(struct encoder_status, image_status_mask);
+ status_buffer->image_status_ctrl_offset = base_offset + offsetof(struct encoder_status, image_status_ctrl);
+ status_buffer->mfc_qp_status_count_offset = base_offset + offsetof(struct encoder_status, mfc_qp_status_count);
+ status_buffer->media_index_offset = base_offset + offsetof(struct encoder_status, media_index);
+
+ status_buffer->status_buffer_size = sizeof(struct encoder_status);
+ status_buffer->bs_byte_count_frame_reg_offset = MFC_BITSTREAM_BYTECOUNT_FRAME_REG;
+ status_buffer->bs_byte_count_frame_nh_reg_offset = MFC_BITSTREAM_BYTECOUNT_SLICE_REG;
+ status_buffer->image_status_mask_reg_offset = MFC_IMAGE_STATUS_MASK_REG;
+ status_buffer->image_status_ctrl_reg_offset = MFC_IMAGE_STATUS_CTRL_REG;
+ status_buffer->mfc_qp_status_count_reg_offset = MFC_QP_STATUS_COUNT_REG;
+
+ gen9_avc_kernel_init(ctx,encoder_context);
+ encoder_context->vme_context = vme_context;
+ encoder_context->vme_pipeline = gen9_avc_vme_pipeline;
+ encoder_context->vme_context_destroy = gen9_avc_vme_context_destroy;
+
+ return true;
+
+
+ if(vme_context)
+ free(vme_context);
+
+ if(generic_ctx)
+ free(generic_ctx);
+
+ if(avc_ctx)
+ free(avc_ctx);
+
+ if(generic_state)
+ free(generic_state);
+
+ if(avc_state)
+ free(avc_state);
+
+ return false;
+}
+
+Bool
+gen9_avc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+{
+ /* VME& PAK share the same context */
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+
+ if (!pak_context)
+ return false;
+
+ encoder_context->mfc_context = pak_context;
+ encoder_context->mfc_context_destroy = gen9_avc_pak_context_destroy;
+ encoder_context->mfc_pipeline = gen9_avc_pak_pipeline;
+ encoder_context->mfc_brc_prepare = gen9_avc_pak_brc_prepare;
+ encoder_context->get_status = gen9_avc_get_coded_status;
+ return true;
+}
Pengfei Qu
2017-01-13 09:24:10 UTC
Permalink
VME pipeline:
add resource and surface allocation and free function
add init table for frame mbbrc update
add scaling kernel for AVC encoder
add BRC init reset kernel for AVC RC logic
add BRC frame update-kernel for AVC RC logic
add BRC MB level update kernel for AVC RC logic
add REF frame QA caculation and MB level const data
add MBENC kernel for AVC encoder
add ME kernel for AVC encoder
add WP/SFD kernel for AVC encoder
add kernel init/destroy function for AVC encoder
add kernel related parameter check function for AVC
add VME pipeline init prepare/run function for AVC encoder

Reviewed-by: Sean V Kelley<***@posteo.de>
Signed-off-by: Pengfei Qu <***@intel.com>
---
src/gen9_avc_encoder.c | 5745 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 5745 insertions(+)
create mode 100755 src/gen9_avc_encoder.c

diff --git a/src/gen9_avc_encoder.c b/src/gen9_avc_encoder.c
new file mode 100755
index 0000000..5caa9f4
--- /dev/null
+++ b/src/gen9_avc_encoder.c
@@ -0,0 +1,5745 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu <***@intel.com>
+ *
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+#include <math.h>
+#include <assert.h>
+#include <va/va.h>
+
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_encoder.h"
+#include "i965_encoder_utils.h"
+#include "intel_media.h"
+
+#include "i965_gpe_utils.h"
+#include "i965_encoder_common.h"
+#include "i965_avc_encoder_common.h"
+#include "gen9_avc_encoder_kernels.h"
+#include "gen9_avc_encoder.h"
+#include "gen9_avc_const_def.h"
+
+#define MAX_URB_SIZE 4096 /* In register */
+#define NUM_KERNELS_PER_GPE_CONTEXT 1
+#define MBENC_KERNEL_BASE GEN9_AVC_KERNEL_MBENC_QUALITY_I
+
+#define OUT_BUFFER_2DW(batch, bo, is_target, delta) do { \
+ if (bo) { \
+ OUT_BCS_RELOC64(batch, \
+ bo, \
+ I915_GEM_DOMAIN_INSTRUCTION, \
+ is_target ? I915_GEM_DOMAIN_RENDER : 0, \
+ delta); \
+ } else { \
+ OUT_BCS_BATCH(batch, 0); \
+ OUT_BCS_BATCH(batch, 0); \
+ } \
+ } while (0)
+
+#define OUT_BUFFER_3DW(batch, bo, is_target, delta, attr) do { \
+ OUT_BUFFER_2DW(batch, bo, is_target, delta); \
+ OUT_BCS_BATCH(batch, attr); \
+ } while (0)
+
+
+static const uint32_t qm_flat[16] = {
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010
+};
+
+static const uint32_t fqm_flat[32] = {
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000
+};
+
+static unsigned int slice_type_kernel[3] = {1,2,0};
+
+const gen9_avc_brc_init_reset_curbe_data gen9_avc_brc_init_reset_curbe_init_data =
+{
+ // unsigned int 0
+ {
+ 0
+ },
+
+ // unsigned int 1
+ {
+ 0
+ },
+
+ // unsigned int 2
+ {
+ 0
+ },
+
+ // unsigned int 3
+ {
+ 0
+ },
+
+ // unsigned int 4
+ {
+ 0
+ },
+
+ // unsigned int 5
+ {
+ 0
+ },
+
+ // unsigned int 6
+ {
+ 0
+ },
+
+ // unsigned int 7
+ {
+ 0
+ },
+
+ // unsigned int 8
+ {
+ 0,
+ 0
+ },
+
+ // unsigned int 9
+ {
+ 0,
+ 0
+ },
+
+ // unsigned int 10
+ {
+ 0,
+ 0
+ },
+
+ // unsigned int 11
+ {
+ 0,
+ 1
+ },
+
+ // unsigned int 12
+ {
+ 51,
+ 0
+ },
+
+ // unsigned int 13
+ {
+ 40,
+ 60,
+ 80,
+ 120
+ },
+
+ // unsigned int 14
+ {
+ 35,
+ 60,
+ 80,
+ 120
+ },
+
+ // unsigned int 15
+ {
+ 40,
+ 60,
+ 90,
+ 115
+ },
+
+ // unsigned int 16
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 17
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 18
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 19
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 20
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 21
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 22
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 23
+ {
+ 0
+ }
+};
+
+const gen9_avc_frame_brc_update_curbe_data gen9_avc_frame_brc_update_curbe_init_data =
+{
+ // unsigned int 0
+ {
+ 0
+ },
+
+ // unsigned int 1
+ {
+ 0
+ },
+
+ // unsigned int 2
+ {
+ 0
+ },
+
+ // unsigned int 3
+ {
+ 10,
+ 50
+ },
+
+ // unsigned int 4
+ {
+ 100,
+ 150
+ },
+
+ // unsigned int 5
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 6
+ {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 7
+ {
+ 0
+ },
+
+ // unsigned int 8
+ {
+ 1,
+ 1,
+ 3,
+ 2
+ },
+
+ // unsigned int 9
+ {
+ 1,
+ 40,
+ 5,
+ 5
+ },
+
+ // unsigned int 10
+ {
+ 3,
+ 1,
+ 7,
+ 18
+ },
+
+ // unsigned int 11
+ {
+ 25,
+ 37,
+ 40,
+ 75
+ },
+
+ // unsigned int 12
+ {
+ 97,
+ 103,
+ 125,
+ 160
+ },
+
+ // unsigned int 13
+ {
+ -3,
+ -2,
+ -1,
+ 0
+ },
+
+ // unsigned int 14
+ {
+ 1,
+ 2,
+ 3,
+ 0xff
+ },
+
+ // unsigned int 15
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 16
+ {
+ 0
+ },
+
+ // unsigned int 17
+ {
+ 0
+ },
+
+ // unsigned int 18
+ {
+ 0
+ },
+
+ // unsigned int 19
+ {
+ 0
+ },
+
+ // unsigned int 20
+ {
+ 0
+ },
+
+ // unsigned int 21
+ {
+ 0
+ },
+
+ // unsigned int 22
+ {
+ 0
+ },
+
+ // unsigned int 23
+ {
+ 0
+ },
+
+};
+
+static void
+gen9_avc_update_misc_parameters(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ int i;
+
+ /* brc */
+ generic_state->max_bit_rate = ALIGN(encoder_context->brc.bits_per_second[0], 1000) / 1000;
+ generic_state->window_size = encoder_context->brc.window_size;
+ generic_state->brc_need_reset = encoder_context->brc.need_reset;
+
+ if (generic_state->internal_rate_mode == VA_RC_CBR) {
+ generic_state->min_bit_rate = generic_state->max_bit_rate;
+ generic_state->mb_brc_enabled = encoder_context->brc.mb_rate_control[0];
+
+ if (generic_state->target_bit_rate != generic_state->max_bit_rate) {
+ generic_state->target_bit_rate = generic_state->max_bit_rate;
+ generic_state->brc_need_reset = 1;
+ }
+ } else if (generic_state->internal_rate_mode == VA_RC_VBR) {
+ generic_state->min_bit_rate = generic_state->max_bit_rate * (2 * encoder_context->brc.target_percentage[0] - 100) / 100;
+ generic_state->mb_brc_enabled = encoder_context->brc.mb_rate_control[0];
+
+ if (generic_state->target_bit_rate != generic_state->max_bit_rate * encoder_context->brc.target_percentage[0] / 100) {
+ generic_state->target_bit_rate = generic_state->max_bit_rate * encoder_context->brc.target_percentage[0] / 100;
+ generic_state->brc_need_reset = 1;
+ }
+ }
+
+ /* frame rate */
+ generic_state->frames_per_100s = encoder_context->brc.framerate[0].num/encoder_context->brc.framerate[0].den * 100;
+ generic_state->frame_rate = encoder_context->brc.framerate[0].num/encoder_context->brc.framerate[0].den ;
+
+ /* HRD */
+ if (generic_state->internal_rate_mode != VA_RC_CQP)
+ {
+ generic_state->vbv_buffer_size_in_bit = encoder_context->brc.hrd_buffer_size;//misc->buffer_size;
+ generic_state->init_vbv_buffer_fullness_in_bit = encoder_context->brc.hrd_initial_buffer_fullness;//misc->initial_buffer_fullness;
+ }
+
+ /* ROI */
+ generic_state->num_roi = MIN(encoder_context->brc.num_roi, 3);
+ if (generic_state->num_roi > 0) {
+ generic_state->max_delta_qp = encoder_context->brc.roi_max_delta_qp;
+ generic_state->min_delta_qp = encoder_context->brc.roi_min_delta_qp;
+
+ for (i = 0; i < generic_state->num_roi; i++) {
+ generic_state->roi[i].left = encoder_context->brc.roi[i].left;
+ generic_state->roi[i].right = encoder_context->brc.roi[i].right;
+ generic_state->roi[i].top = encoder_context->brc.roi[i].top;
+ generic_state->roi[i].bottom = encoder_context->brc.roi[i].bottom;
+ generic_state->roi[i].value = encoder_context->brc.roi[i].value;
+
+ generic_state->roi[i].left /= 16;
+ generic_state->roi[i].right /= 16;
+ generic_state->roi[i].top /= 16;
+ generic_state->roi[i].bottom /= 16;
+ }
+ }
+
+}
+
+static bool
+intel_avc_get_kernel_header_and_size(void *pvbinary,
+ int binary_size,
+ INTEL_GENERIC_ENC_OPERATION operation,
+ int krnstate_idx,
+ struct i965_kernel *ret_kernel)
+{
+ typedef uint32_t BIN_PTR[4];
+
+ char *bin_start;
+ gen9_avc_encoder_kernel_header *pkh_table;
+ kernel_header *pcurr_header, *pinvalid_entry, *pnext_header;
+ int next_krnoffset;
+
+ if (!pvbinary || !ret_kernel)
+ return false;
+
+ bin_start = (char *)pvbinary;
+ pkh_table = (gen9_avc_encoder_kernel_header *)pvbinary;
+ pinvalid_entry = &(pkh_table->static_detection) + 1;
+ next_krnoffset = binary_size;
+
+ if (operation == INTEL_GENERIC_ENC_SCALING4X)
+ {
+ pcurr_header = &pkh_table->ply_dscale_ply;
+ }
+ else if (operation == INTEL_GENERIC_ENC_SCALING2X)
+ {
+ pcurr_header = &pkh_table->ply_2xdscale_ply;
+ }
+ else if (operation == INTEL_GENERIC_ENC_ME)
+ {
+ pcurr_header = &pkh_table->me_p;
+ }
+ else if (operation == INTEL_GENERIC_ENC_BRC)
+ {
+ pcurr_header = &pkh_table->frame_brc_init;
+ }
+ else if (operation == INTEL_GENERIC_ENC_MBENC)
+ {
+ pcurr_header = &pkh_table->mbenc_quality_I;
+ }
+ else if (operation == INTEL_GENERIC_ENC_WP)
+ {
+ pcurr_header = &pkh_table->wp;
+ }
+ else if (operation == INTEL_GENERIC_ENC_SFD)
+ {
+ pcurr_header = &pkh_table->static_detection;
+ }
+ else
+ {
+ return false;
+ }
+
+ pcurr_header += krnstate_idx;
+ ret_kernel->bin = (const BIN_PTR *)(bin_start + (pcurr_header->kernel_start_pointer << 6));
+
+ pnext_header = (pcurr_header + 1);
+ if (pnext_header < pinvalid_entry)
+ {
+ next_krnoffset = pnext_header->kernel_start_pointer << 6;
+ }
+ ret_kernel->size = next_krnoffset - (pcurr_header->kernel_start_pointer << 6);
+
+ return true;
+}
+static void
+gen9_free_surfaces_avc(void **data)
+{
+ struct gen9_surface_avc *avc_surface;
+
+ if (!data || !*data)
+ return;
+
+ avc_surface = *data;
+
+ if (avc_surface->scaled_4x_surface_obj) {
+ i965_DestroySurfaces(avc_surface->ctx, &avc_surface->scaled_4x_surface_id, 1);
+ avc_surface->scaled_4x_surface_id = VA_INVALID_SURFACE;
+ avc_surface->scaled_4x_surface_obj = NULL;
+ }
+
+ if (avc_surface->scaled_16x_surface_obj) {
+ i965_DestroySurfaces(avc_surface->ctx, &avc_surface->scaled_16x_surface_id, 1);
+ avc_surface->scaled_16x_surface_id = VA_INVALID_SURFACE;
+ avc_surface->scaled_16x_surface_obj = NULL;
+ }
+
+ if (avc_surface->scaled_32x_surface_obj) {
+ i965_DestroySurfaces(avc_surface->ctx, &avc_surface->scaled_32x_surface_id, 1);
+ avc_surface->scaled_32x_surface_id = VA_INVALID_SURFACE;
+ avc_surface->scaled_32x_surface_obj = NULL;
+ }
+
+ i965_free_gpe_resource(&avc_surface->res_mb_code_surface);
+ i965_free_gpe_resource(&avc_surface->res_mv_data_surface);
+ i965_free_gpe_resource(&avc_surface->res_ref_pic_select_surface);
+
+ dri_bo_unreference(avc_surface->dmv_top);
+ avc_surface->dmv_top = NULL;
+ dri_bo_unreference(avc_surface->dmv_bottom);
+ avc_surface->dmv_bottom = NULL;
+
+ free(avc_surface);
+
+ *data = NULL;
+
+ return;
+}
+
+static VAStatus
+gen9_avc_init_check_surfaces(VADriverContextP ctx,
+ struct object_surface *obj_surface,
+ struct intel_encoder_context *encoder_context,
+ struct avc_surface_param *surface_param)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+
+ struct gen9_surface_avc *avc_surface;
+ int downscaled_width_4x, downscaled_height_4x;
+ int downscaled_width_16x, downscaled_height_16x;
+ int downscaled_width_32x, downscaled_height_32x;
+ int size = 0;
+ unsigned int frame_width_in_mbs = ALIGN(surface_param->frame_width,16) / 16;
+ unsigned int frame_height_in_mbs = ALIGN(surface_param->frame_height,16) / 16;
+ unsigned int frame_mb_nums = frame_width_in_mbs * frame_height_in_mbs;
+ int allocate_flag = 1;
+ int width,height;
+
+ if (!obj_surface || !obj_surface->bo)
+ return VA_STATUS_ERROR_INVALID_SURFACE;
+
+ if (obj_surface->private_data &&
+ obj_surface->free_private_data != gen9_free_surfaces_avc) {
+ obj_surface->free_private_data(&obj_surface->private_data);
+ obj_surface->private_data = NULL;
+ }
+
+ if (obj_surface->private_data) {
+ return VA_STATUS_SUCCESS;
+ }
+
+ avc_surface = calloc(1, sizeof(struct gen9_surface_avc));
+
+ if (!avc_surface)
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+
+ avc_surface->ctx = ctx;
+ obj_surface->private_data = avc_surface;
+ obj_surface->free_private_data = gen9_free_surfaces_avc;
+
+ downscaled_width_4x = generic_state->frame_width_4x;
+ downscaled_height_4x = generic_state->frame_height_4x;
+
+ i965_CreateSurfaces(ctx,
+ downscaled_width_4x,
+ downscaled_height_4x,
+ VA_RT_FORMAT_YUV420,
+ 1,
+ &avc_surface->scaled_4x_surface_id);
+
+ avc_surface->scaled_4x_surface_obj = SURFACE(avc_surface->scaled_4x_surface_id);
+
+ if (!avc_surface->scaled_4x_surface_obj) {
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+ }
+
+ i965_check_alloc_surface_bo(ctx, avc_surface->scaled_4x_surface_obj, 1,
+ VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
+
+ downscaled_width_16x = generic_state->frame_width_16x;
+ downscaled_height_16x = generic_state->frame_height_16x;
+ i965_CreateSurfaces(ctx,
+ downscaled_width_16x,
+ downscaled_height_16x,
+ VA_RT_FORMAT_YUV420,
+ 1,
+ &avc_surface->scaled_16x_surface_id);
+ avc_surface->scaled_16x_surface_obj = SURFACE(avc_surface->scaled_16x_surface_id);
+
+ if (!avc_surface->scaled_16x_surface_obj) {
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+ }
+
+ i965_check_alloc_surface_bo(ctx, avc_surface->scaled_16x_surface_obj, 1,
+ VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
+
+ downscaled_width_32x = generic_state->frame_width_32x;
+ downscaled_height_32x = generic_state->frame_height_32x;
+ i965_CreateSurfaces(ctx,
+ downscaled_width_32x,
+ downscaled_height_32x,
+ VA_RT_FORMAT_YUV420,
+ 1,
+ &avc_surface->scaled_32x_surface_id);
+ avc_surface->scaled_32x_surface_obj = SURFACE(avc_surface->scaled_32x_surface_id);
+
+ if (!avc_surface->scaled_32x_surface_obj) {
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+ }
+
+ i965_check_alloc_surface_bo(ctx, avc_surface->scaled_32x_surface_obj, 1,
+ VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
+
+ /*mb code and mv data for each frame*/
+ size = frame_mb_nums * 16 * 4;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_surface->res_mb_code_surface,
+ ALIGN(size,0x1000),
+ "mb code buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = frame_mb_nums * 32 * 4;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_surface->res_mv_data_surface,
+ ALIGN(size,0x1000),
+ "mv data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ /* ref pic list*/
+ if(avc_state->ref_pic_select_list_supported)
+ {
+ width = ALIGN(frame_width_in_mbs * 8,64);
+ height= frame_height_in_mbs ;
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_surface->res_ref_pic_select_surface,
+ width, height,
+ width,
+ "Ref pic select list buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ }
+
+ /*direct mv*/
+ avc_surface->dmv_top =
+ dri_bo_alloc(i965->intel.bufmgr,
+ "direct mv top Buffer",
+ 68 * frame_mb_nums,
+ 64);
+ avc_surface->dmv_bottom =
+ dri_bo_alloc(i965->intel.bufmgr,
+ "direct mv bottom Buffer",
+ 68 * frame_mb_nums,
+ 64);
+ assert(avc_surface->dmv_top);
+ assert(avc_surface->dmv_bottom);
+
+ return VA_STATUS_SUCCESS;
+
+failed_allocation:
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
+
+static VAStatus
+gen9_avc_allocate_resources(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ unsigned int size = 0;
+ unsigned int width = 0;
+ unsigned int height = 0;
+ unsigned char * data = NULL;
+ int allocate_flag = 1;
+ int i = 0;
+
+ /*all the surface/buffer are allocated here*/
+
+ /*second level batch buffer for image state write when cqp etc*/
+ i965_free_gpe_resource(&avc_ctx->res_image_state_batch_buffer_2nd_level);
+ size = INTEL_AVC_IMAGE_STATE_CMD_SIZE ;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_image_state_batch_buffer_2nd_level,
+ ALIGN(size,0x1000),
+ "second levle batch (image state write) buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ /* scaling related surface */
+ if(avc_state->mb_status_supported)
+ {
+ i965_free_gpe_resource(&avc_ctx->res_mb_status_buffer);
+ size = (generic_state->frame_width_in_mbs * generic_state->frame_height_in_mbs * 16 * 4 + 1023)&~0x3ff;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_mb_status_buffer,
+ ALIGN(size,0x1000),
+ "MB statistics output buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->res_mb_status_buffer);
+ }
+
+ if(avc_state->flatness_check_supported)
+ {
+ width = generic_state->frame_width_in_mbs * 4;
+ height= generic_state->frame_height_in_mbs * 4;
+ i965_free_gpe_resource(&avc_ctx->res_flatness_check_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->res_flatness_check_surface,
+ width, height,
+ ALIGN(width,64),
+ "Flatness check buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ }
+ /* me related surface */
+ width = generic_state->downscaled_width_4x_in_mb * 8;
+ height= generic_state->downscaled_height_4x_in_mb * 4 * 10;
+ i965_free_gpe_resource(&avc_ctx->s4x_memv_distortion_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->s4x_memv_distortion_buffer,
+ width, height,
+ ALIGN(width,64),
+ "4x MEMV distortion buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s4x_memv_distortion_buffer);
+
+ width = (generic_state->downscaled_width_4x_in_mb + 7)/8 * 64;
+ height= (generic_state->downscaled_height_4x_in_mb + 1)/2 * 8;
+ i965_free_gpe_resource(&avc_ctx->s4x_memv_min_distortion_brc_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->s4x_memv_min_distortion_brc_buffer,
+ width, height,
+ width,
+ "4x MEMV min distortion brc buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s4x_memv_min_distortion_brc_buffer);
+
+
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 32,64);
+ height= generic_state->downscaled_height_4x_in_mb * 4 * 2 * 10;
+ i965_free_gpe_resource(&avc_ctx->s4x_memv_data_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->s4x_memv_data_buffer,
+ width, height,
+ width,
+ "4x MEMV data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s4x_memv_data_buffer);
+
+
+ width = ALIGN(generic_state->downscaled_width_16x_in_mb * 32,64);
+ height= generic_state->downscaled_height_16x_in_mb * 4 * 2 * 10 ;
+ i965_free_gpe_resource(&avc_ctx->s16x_memv_data_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->s16x_memv_data_buffer,
+ width, height,
+ width,
+ "16x MEMV data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s16x_memv_data_buffer);
+
+
+ width = ALIGN(generic_state->downscaled_width_32x_in_mb * 32,64);
+ height= generic_state->downscaled_height_32x_in_mb * 4 * 2 * 10 ;
+ i965_free_gpe_resource(&avc_ctx->s32x_memv_data_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->s32x_memv_data_buffer,
+ width, height,
+ width,
+ "32x MEMV data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s32x_memv_data_buffer);
+
+
+ if(!generic_state->brc_allocated)
+ {
+ /*brc related surface */
+ i965_free_gpe_resource(&avc_ctx->res_brc_history_buffer);
+ size = 864;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_brc_history_buffer,
+ ALIGN(size,0x1000),
+ "brc history buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ i965_free_gpe_resource(&avc_ctx->res_brc_pre_pak_statistics_output_buffer);
+ size = 64;//44
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_brc_pre_pak_statistics_output_buffer,
+ ALIGN(size,0x1000),
+ "brc pak statistic buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ i965_free_gpe_resource(&avc_ctx->res_brc_image_state_read_buffer);
+ size = INTEL_AVC_IMAGE_STATE_CMD_SIZE * 7;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_brc_image_state_read_buffer,
+ ALIGN(size,0x1000),
+ "brc image state read buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ i965_free_gpe_resource(&avc_ctx->res_brc_image_state_write_buffer);
+ size = INTEL_AVC_IMAGE_STATE_CMD_SIZE * 7;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_brc_image_state_write_buffer,
+ ALIGN(size,0x1000),
+ "brc image state write buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ width = ALIGN(64,64);
+ height= 44;
+ i965_free_gpe_resource(&avc_ctx->res_brc_const_data_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->res_brc_const_data_buffer,
+ width, height,
+ width,
+ "brc const data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ if(generic_state->brc_distortion_buffer_supported)
+ {
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 8,64);
+ height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
+ width = (generic_state->downscaled_width_4x_in_mb + 7)/8 * 64;
+ height= (generic_state->downscaled_height_4x_in_mb + 1)/2 * 8;
+ i965_free_gpe_resource(&avc_ctx->res_brc_dist_data_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->res_brc_dist_data_surface,
+ width, height,
+ width,
+ "brc dist data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->res_brc_dist_data_surface);
+ }
+
+ if(generic_state->brc_roi_enable)
+ {
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 16,64);
+ height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
+ i965_free_gpe_resource(&avc_ctx->res_mbbrc_roi_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->res_mbbrc_roi_surface,
+ width, height,
+ width,
+ "mbbrc roi buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->res_mbbrc_roi_surface);
+ }
+
+ /*mb qp in mb brc*/
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 4,64);
+ height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
+ i965_free_gpe_resource(&avc_ctx->res_mbbrc_mb_qp_data_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->res_mbbrc_mb_qp_data_surface,
+ width, height,
+ width,
+ "mbbrc mb qp buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ i965_free_gpe_resource(&avc_ctx->res_mbbrc_const_data_buffer);
+ size = 16 * 52 * 4;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_mbbrc_const_data_buffer,
+ ALIGN(size,0x1000),
+ "mbbrc const data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ generic_state->brc_allocated = 1;
+ }
+
+ /*mb qp external*/
+ if(avc_state->mb_qp_data_enable)
+ {
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 4,64);
+ height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
+ i965_free_gpe_resource(&avc_ctx->res_mb_qp_data_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->res_mb_qp_data_surface,
+ width, height,
+ width,
+ "external mb qp buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ }
+
+
+ /* maybe it is not needed by now. it is used in crypt mode*/
+ i965_free_gpe_resource(&avc_ctx->res_brc_mbenc_curbe_write_buffer);
+ size = ALIGN(sizeof(gen9_avc_mbenc_curbe_data), 64) + ALIGN(sizeof(struct gen8_interface_descriptor_data), 64) ;//* NUM_GEN9_AVC_KERNEL_MBENC;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_brc_mbenc_curbe_write_buffer,
+ size,
+ "mbenc curbe data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ /* mbenc related surface. it share most of surface with other kernels */
+ if(avc_state->arbitrary_num_mbs_in_slice)
+ {
+ width = (generic_state->frame_width_in_mbs + 1) * 64;
+ height= generic_state->frame_height_in_mbs ;
+ i965_free_gpe_resource(&avc_ctx->res_mbenc_slice_map_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+ &avc_ctx->res_mbenc_slice_map_surface,
+ width, height,
+ width,
+ "slice map buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ /*generate slice map,default one slice per frame.*/
+ }
+
+ /* sfd related surface */
+ if(avc_state->sfd_enable)
+ {
+ i965_free_gpe_resource(&avc_ctx->res_sfd_output_buffer);
+ size = 128;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_sfd_output_buffer,
+ size,
+ "sfd output buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_p_frame_buffer);
+ size = ALIGN(52,64);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_sfd_cost_table_p_frame_buffer,
+ size,
+ "sfd P frame cost table buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ data = i965_map_gpe_resource(&(avc_ctx->res_sfd_cost_table_p_frame_buffer));
+ assert(data);
+ memcpy(data,gen9_avc_sfd_cost_table_p_frame,sizeof(unsigned char) *52);
+ i965_unmap_gpe_resource(&(avc_ctx->res_sfd_cost_table_p_frame_buffer));
+
+ i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_b_frame_buffer);
+ size = ALIGN(52,64);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_sfd_cost_table_b_frame_buffer,
+ size,
+ "sfd B frame cost table buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ data = i965_map_gpe_resource(&(avc_ctx->res_sfd_cost_table_b_frame_buffer));
+ assert(data);
+ memcpy(data,gen9_avc_sfd_cost_table_b_frame,sizeof(unsigned char) *52);
+ i965_unmap_gpe_resource(&(avc_ctx->res_sfd_cost_table_b_frame_buffer));
+ }
+
+ /* wp related surfaces */
+ if(avc_state->weighted_prediction_supported)
+ {
+ for(i = 0; i < 2 ; i++)
+ {
+ if (avc_ctx->wp_output_pic_select_surface_obj[i]) {
+ continue;
+ }
+
+ width = generic_state->frame_width_in_pixel;
+ height= generic_state->frame_height_in_pixel ;
+ i965_CreateSurfaces(ctx,
+ width,
+ height,
+ VA_RT_FORMAT_YUV420,
+ 1,
+ &avc_ctx->wp_output_pic_select_surface_id[i]);
+ avc_ctx->wp_output_pic_select_surface_obj[i] = SURFACE(avc_ctx->wp_output_pic_select_surface_id[i]);
+
+ if (!avc_ctx->wp_output_pic_select_surface_obj[i]) {
+ goto failed_allocation;
+ }
+
+ i965_check_alloc_surface_bo(ctx, avc_ctx->wp_output_pic_select_surface_obj[i], 1,
+ VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
+ }
+ i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[0]);
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_wp_output_pic_select_surface_list[0], avc_ctx->wp_output_pic_select_surface_obj[0]);
+ i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[1]);
+ i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_wp_output_pic_select_surface_list[1], avc_ctx->wp_output_pic_select_surface_obj[1]);
+ }
+
+ /* other */
+
+ i965_free_gpe_resource(&avc_ctx->res_mad_data_buffer);
+ size = 4 * 1;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+ &avc_ctx->res_mad_data_buffer,
+ ALIGN(size,0x1000),
+ "MAD data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ return VA_STATUS_SUCCESS;
+
+failed_allocation:
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
+
+static void
+gen9_avc_free_resources(struct encoder_vme_mfc_context * vme_context)
+{
+ if(!vme_context)
+ return;
+
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ VADriverContextP ctx = avc_ctx->ctx;
+ int i = 0;
+
+ /* free all the surface/buffer here*/
+ i965_free_gpe_resource(&avc_ctx->res_image_state_batch_buffer_2nd_level);
+ i965_free_gpe_resource(&avc_ctx->res_mb_status_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_flatness_check_surface);
+ i965_free_gpe_resource(&avc_ctx->s4x_memv_distortion_buffer);
+ i965_free_gpe_resource(&avc_ctx->s4x_memv_min_distortion_brc_buffer);
+ i965_free_gpe_resource(&avc_ctx->s4x_memv_data_buffer);
+ i965_free_gpe_resource(&avc_ctx->s16x_memv_data_buffer);
+ i965_free_gpe_resource(&avc_ctx->s32x_memv_data_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_brc_history_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_brc_pre_pak_statistics_output_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_brc_image_state_read_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_brc_image_state_write_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_brc_const_data_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_brc_dist_data_surface);
+ i965_free_gpe_resource(&avc_ctx->res_mbbrc_roi_surface);
+ i965_free_gpe_resource(&avc_ctx->res_mbbrc_mb_qp_data_surface);
+ i965_free_gpe_resource(&avc_ctx->res_mb_qp_data_surface);
+ i965_free_gpe_resource(&avc_ctx->res_mbbrc_const_data_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_brc_mbenc_curbe_write_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_mbenc_slice_map_surface);
+ i965_free_gpe_resource(&avc_ctx->res_sfd_output_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_p_frame_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_b_frame_buffer);
+ i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[0]);
+ i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[1]);
+ i965_free_gpe_resource(&avc_ctx->res_mad_data_buffer);
+
+ for(i = 0;i < 2 ; i++)
+ {
+ if (avc_ctx->wp_output_pic_select_surface_obj[i]) {
+ i965_DestroySurfaces(ctx, &avc_ctx->wp_output_pic_select_surface_id[i], 1);
+ avc_ctx->wp_output_pic_select_surface_id[i] = VA_INVALID_SURFACE;
+ avc_ctx->wp_output_pic_select_surface_obj[i] = NULL;
+ }
+ }
+
+}
+
+static void
+gen9_avc_run_kernel_media_object(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ struct i965_gpe_context *gpe_context,
+ int media_function,
+ struct gpe_media_object_parameter *param)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct encoder_status_buffer_internal *status_buffer;
+ struct gpe_mi_store_data_imm_parameter mi_store_data_imm;
+
+ if (!batch)
+ return;
+
+ intel_batchbuffer_start_atomic(batch, 0x1000);
+
+ status_buffer = &(avc_ctx->status_buffer);
+ memset(&mi_store_data_imm, 0, sizeof(mi_store_data_imm));
+ mi_store_data_imm.bo = status_buffer->bo;
+ mi_store_data_imm.offset = status_buffer->media_index_offset;
+ mi_store_data_imm.dw0 = media_function;
+ gen8_gpe_mi_store_data_imm(ctx, batch, &mi_store_data_imm);
+
+ intel_batchbuffer_emit_mi_flush(batch);
+ gen9_gpe_pipeline_setup(ctx, gpe_context, batch);
+ gen8_gpe_media_object(ctx, gpe_context, batch, param);
+ gen8_gpe_media_state_flush(ctx, gpe_context, batch);
+
+ gen9_gpe_pipeline_end(ctx, gpe_context, batch);
+
+ intel_batchbuffer_end_atomic(batch);
+
+ intel_batchbuffer_flush(batch);
+}
+
+static void
+gen9_avc_run_kernel_media_object_walker(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context,
+ struct i965_gpe_context *gpe_context,
+ int media_function,
+ struct gpe_media_object_walker_parameter *param)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+
+ struct intel_batchbuffer *batch = encoder_context->base.batch;
+ struct encoder_status_buffer_internal *status_buffer;
+ struct gpe_mi_store_data_imm_parameter mi_store_data_imm;
+
+ if (!batch)
+ return;
+
+ intel_batchbuffer_start_atomic(batch, 0x1000);
+
+ intel_batchbuffer_emit_mi_flush(batch);
+
+ status_buffer = &(avc_ctx->status_buffer);
+ memset(&mi_store_data_imm, 0, sizeof(mi_store_data_imm));
+ mi_store_data_imm.bo = status_buffer->bo;
+ mi_store_data_imm.offset = status_buffer->media_index_offset;
+ mi_store_data_imm.dw0 = media_function;
+ gen8_gpe_mi_store_data_imm(ctx, batch, &mi_store_data_imm);
+
+ gen9_gpe_pipeline_setup(ctx, gpe_context, batch);
+ gen8_gpe_media_object_walker(ctx, gpe_context, batch, param);
+ gen8_gpe_media_state_flush(ctx, gpe_context, batch);
+
+ gen9_gpe_pipeline_end(ctx, gpe_context, batch);
+
+ intel_batchbuffer_end_atomic(batch);
+
+ intel_batchbuffer_flush(batch);
+}
+
+static void
+gen9_init_gpe_context_avc(VADriverContextP ctx,
+ struct i965_gpe_context *gpe_context,
+ struct encoder_kernel_parameter *kernel_param)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+
+ gpe_context->curbe.length = kernel_param->curbe_size; // in bytes
+
+ gpe_context->sampler.entry_size = 0;
+ gpe_context->sampler.max_entries = 0;
+
+ if (kernel_param->sampler_size) {
+ gpe_context->sampler.entry_size = ALIGN(kernel_param->sampler_size, 64);
+ gpe_context->sampler.max_entries = 1;
+ }
+
+ gpe_context->idrt.entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64); // 8 dws, 1 register
+ gpe_context->idrt.max_entries = NUM_KERNELS_PER_GPE_CONTEXT;
+
+ gpe_context->surface_state_binding_table.max_entries = MAX_AVC_ENCODER_SURFACES;
+ gpe_context->surface_state_binding_table.binding_table_offset = 0;
+ gpe_context->surface_state_binding_table.surface_state_offset = ALIGN(MAX_AVC_ENCODER_SURFACES * 4, 64);
+ gpe_context->surface_state_binding_table.length = ALIGN(MAX_AVC_ENCODER_SURFACES * 4, 64) + ALIGN(MAX_AVC_ENCODER_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN9, 64);
+
+ if (i965->intel.eu_total > 0)
+ gpe_context->vfe_state.max_num_threads = 6 * i965->intel.eu_total;
+ else
+ gpe_context->vfe_state.max_num_threads = 112; // 16 EU * 7 threads
+
+ gpe_context->vfe_state.curbe_allocation_size = MAX(1, ALIGN(gpe_context->curbe.length, 32) >> 5); // in registers
+ gpe_context->vfe_state.urb_entry_size = MAX(1, ALIGN(kernel_param->inline_data_size, 32) >> 5); // in registers
+ gpe_context->vfe_state.num_urb_entries = (MAX_URB_SIZE -
+ gpe_context->vfe_state.curbe_allocation_size -
+ ((gpe_context->idrt.entry_size >> 5) *
+ gpe_context->idrt.max_entries)) / gpe_context->vfe_state.urb_entry_size;
+ gpe_context->vfe_state.num_urb_entries = CLAMP(1, 127, gpe_context->vfe_state.num_urb_entries);
+ gpe_context->vfe_state.gpgpu_mode = 0;
+}
+
+static void
+gen9_init_vfe_scoreboard_avc(struct i965_gpe_context *gpe_context,
+ struct encoder_scoreboard_parameter *scoreboard_param)
+{
+ gpe_context->vfe_desc5.scoreboard0.mask = scoreboard_param->mask;
+ gpe_context->vfe_desc5.scoreboard0.type = scoreboard_param->type;
+ gpe_context->vfe_desc5.scoreboard0.enable = scoreboard_param->enable;
+
+ if (scoreboard_param->walkpat_flag) {
+ gpe_context->vfe_desc5.scoreboard0.mask = 0x0F;
+ gpe_context->vfe_desc5.scoreboard0.type = 1;
+
+ gpe_context->vfe_desc6.scoreboard1.delta_x0 = 0x0;
+ gpe_context->vfe_desc6.scoreboard1.delta_y0 = 0xF;
+
+ gpe_context->vfe_desc6.scoreboard1.delta_x1 = 0x0;
+ gpe_context->vfe_desc6.scoreboard1.delta_y1 = 0xE;
+
+ gpe_context->vfe_desc6.scoreboard1.delta_x2 = 0xF;
+ gpe_context->vfe_desc6.scoreboard1.delta_y2 = 0x3;
+
+ gpe_context->vfe_desc6.scoreboard1.delta_x3 = 0xF;
+ gpe_context->vfe_desc6.scoreboard1.delta_y3 = 0x1;
+ } else {
+ // Scoreboard 0
+ gpe_context->vfe_desc6.scoreboard1.delta_x0 = 0xF;
+ gpe_context->vfe_desc6.scoreboard1.delta_y0 = 0x0;
+
+ // Scoreboard 1
+ gpe_context->vfe_desc6.scoreboard1.delta_x1 = 0x0;
+ gpe_context->vfe_desc6.scoreboard1.delta_y1 = 0xF;
+
+ // Scoreboard 2
+ gpe_context->vfe_desc6.scoreboard1.delta_x2 = 0x1;
+ gpe_context->vfe_desc6.scoreboard1.delta_y2 = 0xF;
+
+ // Scoreboard 3
+ gpe_context->vfe_desc6.scoreboard1.delta_x3 = 0xF;
+ gpe_context->vfe_desc6.scoreboard1.delta_y3 = 0xF;
+
+ // Scoreboard 4
+ gpe_context->vfe_desc7.scoreboard2.delta_x4 = 0xF;
+ gpe_context->vfe_desc7.scoreboard2.delta_y4 = 0x1;
+
+ // Scoreboard 5
+ gpe_context->vfe_desc7.scoreboard2.delta_x5 = 0x0;
+ gpe_context->vfe_desc7.scoreboard2.delta_y5 = 0xE;
+
+ // Scoreboard 6
+ gpe_context->vfe_desc7.scoreboard2.delta_x6 = 0x1;
+ gpe_context->vfe_desc7.scoreboard2.delta_y6 = 0xE;
+
+ // Scoreboard 7
+ gpe_context->vfe_desc7.scoreboard2.delta_x6 = 0xF;
+ gpe_context->vfe_desc7.scoreboard2.delta_y6 = 0xE;
+ }
+}
+/*
+VME pipeline related function
+*/
+
+/*
+scaling kernel related function
+*/
+static void
+gen9_avc_set_curbe_scaling4x(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param)
+{
+ gen9_avc_scaling4x_curbe_data *curbe_cmd;
+ struct scaling_param *surface_param = (struct scaling_param *)param;
+
+ curbe_cmd = i965_gpe_context_map_curbe(gpe_context);
+
+ if (!curbe_cmd)
+ return;
+
+ memset(curbe_cmd, 0, sizeof(gen9_avc_scaling4x_curbe_data));
+
+ curbe_cmd->dw0.input_picture_width = surface_param->input_frame_width;
+ curbe_cmd->dw0.input_picture_height = surface_param->input_frame_height;
+
+ curbe_cmd->dw1.input_y_bti = GEN9_AVC_SCALING_FRAME_SRC_Y_INDEX;
+ curbe_cmd->dw2.output_y_bti = GEN9_AVC_SCALING_FRAME_DST_Y_INDEX;
+
+
+ curbe_cmd->dw5.flatness_threshold = 128;
+ curbe_cmd->dw6.enable_mb_flatness_check = surface_param->enable_mb_flatness_check;
+ curbe_cmd->dw7.enable_mb_variance_output = surface_param->enable_mb_variance_output;
+ curbe_cmd->dw8.enable_mb_pixel_average_output = surface_param->enable_mb_pixel_average_output;
+
+ if (curbe_cmd->dw6.enable_mb_flatness_check ||
+ curbe_cmd->dw7.enable_mb_variance_output ||
+ curbe_cmd->dw8.enable_mb_pixel_average_output)
+ {
+ curbe_cmd->dw10.mbv_proc_stat_bti = GEN9_AVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX;
+ }
+
+ i965_gpe_context_unmap_curbe(gpe_context);
+ return;
+}
+
+static void
+gen9_avc_set_curbe_scaling2x(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param)
+{
+ gen9_avc_scaling2x_curbe_data *curbe_cmd;
+ struct scaling_param *surface_param = (struct scaling_param *)param;
+
+ curbe_cmd = i965_gpe_context_map_curbe(gpe_context);
+
+ if (!curbe_cmd)
+ return;
+
+ memset(curbe_cmd, 0, sizeof(gen9_avc_scaling2x_curbe_data));
+
+ curbe_cmd->dw0.input_picture_width = surface_param->input_frame_width;
+ curbe_cmd->dw0.input_picture_height = surface_param->input_frame_height;
+
+ curbe_cmd->dw8.input_y_bti = GEN9_AVC_SCALING_FRAME_SRC_Y_INDEX;
+ curbe_cmd->dw9.output_y_bti = GEN9_AVC_SCALING_FRAME_DST_Y_INDEX;
+
+ i965_gpe_context_unmap_curbe(gpe_context);
+ return;
+}
+
+static void
+gen9_avc_send_surface_scaling(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void *param)
+{
+ struct scaling_param *surface_param = (struct scaling_param *)param;
+ unsigned int surface_format;
+ unsigned int res_size;
+
+ if (surface_param->scaling_out_use_32unorm_surf_fmt)
+ surface_format = I965_SURFACEFORMAT_R32_UNORM;
+ else if (surface_param->scaling_out_use_16unorm_surf_fmt)
+ surface_format = I965_SURFACEFORMAT_R16_UNORM;
+ else
+ surface_format = I965_SURFACEFORMAT_R8_UNORM;
+
+ gen9_add_2d_gpe_surface(ctx, gpe_context,
+ surface_param->input_surface,
+ 0, 1, surface_format,
+ GEN9_AVC_SCALING_FRAME_SRC_Y_INDEX);
+
+ gen9_add_2d_gpe_surface(ctx, gpe_context,
+ surface_param->output_surface,
+ 0, 1, surface_format,
+ GEN9_AVC_SCALING_FRAME_DST_Y_INDEX);
+
+ /*add buffer mv_proc_stat, here need change*/
+ if (surface_param->mbv_proc_stat_enabled)
+ {
+ res_size = 16 * (surface_param->input_frame_width/16) * (surface_param->input_frame_height/16) * sizeof(unsigned int);
+
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ surface_param->pres_mbv_proc_stat_buffer,
+ 0,
+ res_size/4,
+ 0,
+ GEN9_AVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX);
+ }else if(surface_param->enable_mb_flatness_check)
+ {
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ surface_param->pres_flatness_check_surface,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_SCALING_FRAME_MBVPROCSTATS_DST_INDEX);
+ }
+
+ return;
+}
+
+static VAStatus
+gen9_avc_kernel_scaling(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int hme_type)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
+
+ struct i965_gpe_context *gpe_context;
+ struct scaling_param surface_param;
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+ struct gpe_media_object_walker_parameter media_object_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
+ unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
+ int media_function = 0;
+ int kernel_idx = 0;
+
+ obj_surface = encode_state->reconstructed_object;
+ avc_priv_surface = obj_surface->private_data;
+
+ memset(&surface_param,0,sizeof(struct scaling_param));
+ switch(hme_type)
+ {
+ case INTEL_ENC_HME_4x :
+ {
+ media_function = INTEL_MEDIA_STATE_4X_SCALING;
+ kernel_idx = GEN9_AVC_KERNEL_SCALING_4X_IDX;
+ downscaled_width_in_mb = generic_state->downscaled_width_4x_in_mb;
+ downscaled_height_in_mb = generic_state->downscaled_height_4x_in_mb;
+
+ surface_param.input_surface = encode_state->input_yuv_object ;
+ surface_param.input_frame_width = generic_state->frame_width_in_pixel ;
+ surface_param.input_frame_height = generic_state->frame_height_in_pixel ;
+
+ surface_param.output_surface = avc_priv_surface->scaled_4x_surface_obj ;
+ surface_param.output_frame_width = generic_state->frame_width_4x ;
+ surface_param.output_frame_height = generic_state->frame_height_4x ;
+
+ surface_param.enable_mb_flatness_check = avc_state->flatness_check_enable;
+ surface_param.enable_mb_variance_output = avc_state->mb_status_enable;
+ surface_param.enable_mb_pixel_average_output = avc_state->mb_status_enable;
+
+ surface_param.blk8x8_stat_enabled = 0 ;
+ surface_param.use_4x_scaling = 1 ;
+ surface_param.use_16x_scaling = 0 ;
+ surface_param.use_32x_scaling = 0 ;
+ break;
+ }
+ case INTEL_ENC_HME_16x :
+ {
+ media_function = INTEL_MEDIA_STATE_16X_SCALING;
+ kernel_idx = GEN9_AVC_KERNEL_SCALING_4X_IDX;
+ downscaled_width_in_mb = generic_state->downscaled_width_16x_in_mb;
+ downscaled_height_in_mb = generic_state->downscaled_height_16x_in_mb;
+
+ surface_param.input_surface = avc_priv_surface->scaled_4x_surface_obj ;
+ surface_param.input_frame_width = generic_state->frame_width_4x ;
+ surface_param.input_frame_height = generic_state->frame_height_4x ;
+
+ surface_param.output_surface = avc_priv_surface->scaled_16x_surface_obj ;
+ surface_param.output_frame_width = generic_state->frame_width_16x ;
+ surface_param.output_frame_height = generic_state->frame_height_16x ;
+
+ surface_param.enable_mb_flatness_check = 0 ;
+ surface_param.enable_mb_variance_output = 0 ;
+ surface_param.enable_mb_pixel_average_output = 0 ;
+
+ surface_param.blk8x8_stat_enabled = 0 ;
+ surface_param.use_4x_scaling = 0 ;
+ surface_param.use_16x_scaling = 1 ;
+ surface_param.use_32x_scaling = 0 ;
+
+ break;
+ }
+ case INTEL_ENC_HME_32x :
+ {
+ media_function = INTEL_MEDIA_STATE_32X_SCALING;
+ kernel_idx = GEN9_AVC_KERNEL_SCALING_2X_IDX;
+ downscaled_width_in_mb = generic_state->downscaled_width_32x_in_mb;
+ downscaled_height_in_mb = generic_state->downscaled_height_32x_in_mb;
+
+ surface_param.input_surface = avc_priv_surface->scaled_16x_surface_obj ;
+ surface_param.input_frame_width = generic_state->frame_width_16x ;
+ surface_param.input_frame_height = generic_state->frame_height_16x ;
+
+ surface_param.output_surface = avc_priv_surface->scaled_32x_surface_obj ;
+ surface_param.output_frame_width = generic_state->frame_width_32x ;
+ surface_param.output_frame_height = generic_state->frame_height_32x ;
+
+ surface_param.enable_mb_flatness_check = 0 ;
+ surface_param.enable_mb_variance_output = 0 ;
+ surface_param.enable_mb_pixel_average_output = 0 ;
+
+ surface_param.blk8x8_stat_enabled = 0 ;
+ surface_param.use_4x_scaling = 0 ;
+ surface_param.use_16x_scaling = 0 ;
+ surface_param.use_32x_scaling = 1 ;
+ break;
+ }
+ default :
+ assert(0);
+
+ }
+
+ gpe_context = &(avc_ctx->context_scaling.gpe_contexts[kernel_idx]);
+
+ gen8_gpe_context_init(ctx, gpe_context);
+ gen9_gpe_reset_binding_table(ctx, gpe_context);
+
+ if(surface_param.use_32x_scaling)
+ {
+ generic_ctx->pfn_set_curbe_scaling2x(ctx,encode_state,gpe_context,encoder_context,&surface_param);
+ }else
+ {
+ generic_ctx->pfn_set_curbe_scaling4x(ctx,encode_state,gpe_context,encoder_context,&surface_param);
+ }
+
+ if(surface_param.use_32x_scaling)
+ {
+ surface_param.scaling_out_use_16unorm_surf_fmt = 1 ;
+ surface_param.scaling_out_use_32unorm_surf_fmt = 0 ;
+ }else
+ {
+ surface_param.scaling_out_use_16unorm_surf_fmt = 0 ;
+ surface_param.scaling_out_use_32unorm_surf_fmt = 1 ;
+ }
+
+ if(surface_param.use_4x_scaling)
+ {
+ if(avc_state->mb_status_supported)
+ {
+ surface_param.enable_mb_flatness_check = 0;
+ surface_param.mbv_proc_stat_enabled = (surface_param.use_4x_scaling)?(avc_state->mb_status_enable || avc_state->flatness_check_enable):0 ;
+ surface_param.pres_mbv_proc_stat_buffer = &(avc_ctx->res_mb_status_buffer);
+
+ }else
+ {
+ surface_param.enable_mb_flatness_check = (surface_param.use_4x_scaling)?avc_state->flatness_check_enable:0;
+ surface_param.mbv_proc_stat_enabled = 0 ;
+ surface_param.pres_flatness_check_surface = &(avc_ctx->res_flatness_check_surface);
+ }
+ }
+
+ generic_ctx->pfn_send_scaling_surface(ctx,encode_state,gpe_context,encoder_context,&surface_param);
+
+
+ gen8_gpe_setup_interface_data(ctx, gpe_context);
+
+ memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
+ if(surface_param.use_32x_scaling)
+ {
+ kernel_walker_param.resolution_x = downscaled_width_in_mb ;
+ kernel_walker_param.resolution_y = downscaled_height_in_mb ;
+ }else
+ {
+ /* the scaling is based on 8x8 blk level */
+ kernel_walker_param.resolution_x = downscaled_width_in_mb * 2;
+ kernel_walker_param.resolution_y = downscaled_height_in_mb * 2;
+ }
+ kernel_walker_param.no_dependency = 1;
+
+ i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
+
+ gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
+ gpe_context,
+ media_function,
+ &media_object_walker_param);
+
+ return VA_STATUS_SUCCESS;
+}
+/*
+frame/mb brc related function
+*/
+static void
+gen9_avc_init_mfx_avc_img_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ struct gen9_mfx_avc_img_state *pstate)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+
+ VAEncSequenceParameterBufferH264 *seq_param = avc_state->seq_param;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+
+ memset(pstate, 0, sizeof(*pstate));
+
+ pstate->dw0.dword_length = (sizeof(struct gen9_mfx_avc_img_state)) / 4 -2;
+ pstate->dw0.sub_opcode_b = 0;
+ pstate->dw0.sub_opcode_a = 0;
+ pstate->dw0.command_opcode = 1;
+ pstate->dw0.pipeline = 2;
+ pstate->dw0.command_type = 3;
+
+ pstate->dw1.frame_size_in_mbs = generic_state->frame_width_in_mbs * generic_state->frame_height_in_mbs ;
+
+ pstate->dw2.frame_width_in_mbs_minus1 = generic_state->frame_width_in_mbs - 1;
+ pstate->dw2.frame_height_in_mbs_minus1 = generic_state->frame_height_in_mbs - 1;
+
+ pstate->dw3.image_structure = 0;//frame is zero
+ pstate->dw3.weighted_bipred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
+ pstate->dw3.weighted_pred_flag = pic_param->pic_fields.bits.weighted_pred_flag;
+ pstate->dw3.brc_domain_rate_control_enable = 0;//1,set for vdenc;
+ pstate->dw3.chroma_qp_offset = pic_param->chroma_qp_index_offset;
+ pstate->dw3.second_chroma_qp_offset = pic_param->second_chroma_qp_index_offset;
+
+ pstate->dw4.field_picture_flag = 0;
+ pstate->dw4.mbaff_mode_active = seq_param->seq_fields.bits.mb_adaptive_frame_field_flag;
+ pstate->dw4.frame_mb_only_flag = seq_param->seq_fields.bits.frame_mbs_only_flag;
+ pstate->dw4.transform_8x8_idct_mode_flag = pic_param->pic_fields.bits.transform_8x8_mode_flag;
+ pstate->dw4.direct_8x8_interface_flag = seq_param->seq_fields.bits.direct_8x8_inference_flag;
+ pstate->dw4.constrained_intra_prediction_flag = pic_param->pic_fields.bits.constrained_intra_pred_flag;
+ pstate->dw4.entropy_coding_flag = pic_param->pic_fields.bits.entropy_coding_mode_flag;
+ pstate->dw4.mb_mv_format_flag = 1;
+ pstate->dw4.chroma_format_idc = seq_param->seq_fields.bits.chroma_format_idc;
+ pstate->dw4.mv_unpacked_flag = 1;
+ pstate->dw4.insert_test_flag = 0;
+ pstate->dw4.load_slice_pointer_flag = 0;
+ pstate->dw4.macroblock_stat_enable = 0; /* disable in the first pass */
+ pstate->dw4.minimum_frame_size = 0;
+ pstate->dw5.intra_mb_max_bit_flag = 1;
+ pstate->dw5.inter_mb_max_bit_flag = 1;
+ pstate->dw5.frame_size_over_flag = 1;
+ pstate->dw5.frame_size_under_flag = 1;
+ pstate->dw5.intra_mb_ipcm_flag = 1;
+ pstate->dw5.mb_rate_ctrl_flag = 0; /* Always 0 in VDEnc mode */
+ pstate->dw5.non_first_pass_flag = 0;
+ pstate->dw5.aq_enable = pstate->dw5.aq_rounding = 0;
+ pstate->dw5.aq_chroma_disable = 1;
+ if(pstate->dw4.entropy_coding_flag && (avc_state->tq_enable))
+ {
+ pstate->dw5.aq_enable = avc_state->tq_enable;
+ pstate->dw5.aq_rounding = avc_state->tq_rounding;
+ }else
+ {
+ pstate->dw5.aq_rounding = 0;
+ }
+
+ pstate->dw6.intra_mb_max_size = 2700;
+ pstate->dw6.inter_mb_max_size = 4095;
+
+ pstate->dw8.slice_delta_qp_max0 = 0;
+ pstate->dw8.slice_delta_qp_max1 = 0;
+ pstate->dw8.slice_delta_qp_max2 = 0;
+ pstate->dw8.slice_delta_qp_max3 = 0;
+
+ pstate->dw9.slice_delta_qp_min0 = 0;
+ pstate->dw9.slice_delta_qp_min1 = 0;
+ pstate->dw9.slice_delta_qp_min2 = 0;
+ pstate->dw9.slice_delta_qp_min3 = 0;
+
+ pstate->dw10.frame_bitrate_min = 0;
+ pstate->dw10.frame_bitrate_min_unit = 1;
+ pstate->dw10.frame_bitrate_min_unit_mode = 1;
+ pstate->dw10.frame_bitrate_max = (1 << 14) - 1;
+ pstate->dw10.frame_bitrate_max_unit = 1;
+ pstate->dw10.frame_bitrate_max_unit_mode = 1;
+
+ pstate->dw11.frame_bitrate_min_delta = 0;
+ pstate->dw11.frame_bitrate_max_delta = 0;
+
+ pstate->dw12.vad_error_logic = 1;
+ /* TODO: set paramters DW19/DW20 for slices */
+}
+
+void gen9_avc_set_image_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ struct i965_gpe_resource *gpe_resource)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ char *pdata;
+ int i;
+ unsigned int * data;
+ struct gen9_mfx_avc_img_state cmd;
+
+ pdata = i965_map_gpe_resource(gpe_resource);
+
+ gen9_avc_init_mfx_avc_img_state(ctx,encode_state,encoder_context,&cmd);
+ for(i = 0; i < generic_state->num_pak_passes;i++)
+ {
+
+ if(i == 0)
+ {
+ cmd.dw4.macroblock_stat_enable = 0;
+ cmd.dw5.non_first_pass_flag = 0;
+ }else
+ {
+ cmd.dw4.macroblock_stat_enable = 1;
+ cmd.dw5.non_first_pass_flag = 1;
+ cmd.dw5.intra_mb_ipcm_flag = 1;
+
+ }
+ cmd.dw5.mb_rate_ctrl_flag = 0;
+ memcpy(pdata,&cmd,sizeof(struct gen9_mfx_avc_img_state));
+ data = (unsigned int *)(pdata + sizeof(struct gen9_mfx_avc_img_state));
+ *data = MI_BATCH_BUFFER_END;
+
+ pdata += INTEL_AVC_IMAGE_STATE_CMD_SIZE;
+ }
+ i965_unmap_gpe_resource(gpe_resource);
+ return;
+}
+
+void gen9_avc_set_image_state_non_brc(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ struct i965_gpe_resource *gpe_resource)
+{
+ struct encoder_vme_mfc_context * pak_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )pak_context->generic_enc_state;
+ char *pdata;
+
+ unsigned int * data;
+ struct gen9_mfx_avc_img_state cmd;
+
+ pdata = i965_map_gpe_resource(gpe_resource);
+
+ gen9_avc_init_mfx_avc_img_state(ctx,encode_state,encoder_context,&cmd);
+
+ if(generic_state->curr_pak_pass == 0)
+ {
+ cmd.dw4.macroblock_stat_enable = 0;
+ cmd.dw5.non_first_pass_flag = 0;
+
+ }
+ else
+ {
+ cmd.dw4.macroblock_stat_enable = 1;
+ cmd.dw5.non_first_pass_flag = 0;
+ cmd.dw5.intra_mb_ipcm_flag = 1;
+ }
+
+ cmd.dw5.mb_rate_ctrl_flag = 0;
+ memcpy(pdata,&cmd,sizeof(struct gen9_mfx_avc_img_state));
+ data = (unsigned int *)(pdata + sizeof(struct gen9_mfx_avc_img_state));
+ *data = MI_BATCH_BUFFER_END;
+
+ i965_unmap_gpe_resource(gpe_resource);
+ return;
+}
+
+static void
+gen9_avc_init_brc_const_data(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+
+ struct i965_gpe_resource *gpe_resource = NULL;
+ unsigned char * data =NULL;
+ unsigned char * data_tmp = NULL;
+ unsigned int size = 0;
+ unsigned int table_idx = 0;
+ unsigned int block_based_skip_enable = avc_state->block_based_skip_enable;
+ int i = 0;
+
+ struct object_surface *obj_surface;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+ VASurfaceID surface_id;
+ unsigned int transform_8x8_mode_flag = pic_param->pic_fields.bits.transform_8x8_mode_flag;
+
+ gpe_resource = &(avc_ctx->res_brc_const_data_buffer);
+ assert(gpe_resource);
+
+ i965_zero_gpe_resource(gpe_resource);
+
+ data = i965_map_gpe_resource(gpe_resource);
+ assert(data);
+
+ table_idx = slice_type_kernel[generic_state->frame_type];
+
+ /* Fill surface with QP Adjustment table, Distortion threshold table, MaxFrame threshold table, Distortion QP Adjustment Table*/
+ size = sizeof(gen9_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb);
+ memcpy(data,gen9_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb,size*sizeof(unsigned char));
+
+ data += size;
+
+ /* skip threshold table*/
+ size = 128;
+ switch(generic_state->frame_type)
+ {
+ case SLICE_TYPE_P:
+ memcpy(data,gen9_avc_skip_value_p[block_based_skip_enable][transform_8x8_mode_flag],size * sizeof(unsigned char));
+ break;
+ case SLICE_TYPE_B:
+ memcpy(data,gen9_avc_skip_value_b[block_based_skip_enable][transform_8x8_mode_flag],size * sizeof(unsigned char));
+ break;
+ default:
+ /*SLICE_TYPE_I,no change */
+ break;
+ }
+
+ if((generic_state->frame_type != SLICE_TYPE_I) && avc_state->non_ftq_skip_threshold_lut_input_enable)
+ {
+ for(i = 0; i< 52 ; i++)
+ {
+ *(data + 1 + (i * 2)) = (unsigned char)i965_avc_calc_skip_value(block_based_skip_enable,transform_8x8_mode_flag,avc_state->non_ftq_skip_threshold_lut[i]);
+ }
+ }
+ data += size;
+
+ /*fill the qp for ref list*/
+ size = 32 + 32 +32 +160;
+ memset(data,0xff,32);
+ memset(data+32+32,0xff,32);
+ switch(generic_state->frame_type)
+ {
+ case SLICE_TYPE_P:
+ {
+ for(i = 0 ; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList0[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface)
+ break;
+ *(data + i) = avc_state->list_ref_idx[0][i];//?
+ }
+ }
+ break;
+ case SLICE_TYPE_B:
+ {
+ data = data + 32 + 32;
+ for(i = 0 ; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList1[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface)
+ break;
+ *(data + i) = avc_state->list_ref_idx[1][i];//?
+ }
+
+ data = data - 32 - 32;
+
+ for(i = 0 ; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList0[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface)
+ break;
+ *(data + i) = avc_state->list_ref_idx[0][i];//?
+ }
+ }
+ break;
+ default:
+ /*SLICE_TYPE_I,no change */
+ break;
+ }
+ data += size;
+
+ /*mv cost and mode cost*/
+ size = 1664;
+ memcpy(data,(unsigned char *)&gen9_avc_mode_mv_cost_table[table_idx][0][0],size * sizeof(unsigned char));
+
+ if(avc_state->old_mode_cost_enable)
+ { data_tmp = data;
+ for(i = 0; i < 52 ; i++)
+ {
+ *(data_tmp +3) = (unsigned int)gen9_avc_old_intra_mode_cost[i];
+ data_tmp += 16;
+ }
+ }
+
+ if(avc_state->ftq_skip_threshold_lut_input_enable)
+ {
+ for(i = 0; i < 52 ; i++)
+ {
+ *(data + (i * 32) + 24) =
+ *(data + (i * 32) + 25) =
+ *(data + (i * 32) + 27) =
+ *(data + (i * 32) + 28) =
+ *(data + (i * 32) + 29) =
+ *(data + (i * 32) + 30) =
+ *(data + (i * 32) + 31) = avc_state->ftq_skip_threshold_lut[i];
+ }
+
+ }
+ data += size;
+
+ /*ref cost*/
+ size = 128;
+ memcpy(data,(unsigned char *)&gen9_avc_ref_cost[table_idx][0],size * sizeof(unsigned char));
+ data += size;
+
+ /*scaling factor*/
+ size = 64;
+ if(avc_state->adaptive_intra_scaling_enable)
+ {
+ memcpy(data,(unsigned char *)&gen9_avc_adaptive_intra_scaling_factor,size * sizeof(unsigned char));
+ }else
+ {
+ memcpy(data,(unsigned char *)&gen9_avc_intra_scaling_factor,size * sizeof(unsigned char));
+ }
+ i965_unmap_gpe_resource(gpe_resource);
+}
+
+static void
+gen9_avc_init_brc_const_data_old(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+
+ struct i965_gpe_resource *gpe_resource = NULL;
+ unsigned int * data =NULL;
+ unsigned int * data_tmp = NULL;
+ unsigned int size = 0;
+ unsigned int table_idx = 0;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+ unsigned int block_based_skip_enable = avc_state->block_based_skip_enable;
+ unsigned int transform_8x8_mode_flag = pic_param->pic_fields.bits.transform_8x8_mode_flag;
+ int i = 0;
+
+ gpe_resource = &(avc_ctx->res_brc_const_data_buffer);
+ assert(gpe_resource);
+
+ i965_zero_gpe_resource(gpe_resource);
+
+ data = i965_map_gpe_resource(gpe_resource);
+ assert(data);
+
+ table_idx = slice_type_kernel[generic_state->frame_type];
+
+ /* Fill surface with QP Adjustment table, Distortion threshold table, MaxFrame threshold table, Distortion QP Adjustment Table*/
+ size = sizeof(gen75_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb);
+ memcpy(data,gen75_avc_qp_adjustment_dist_threshold_max_frame_threshold_dist_qp_adjustment_ipb,size*sizeof(unsigned char));
+
+ data += size;
+
+ /* skip threshold table*/
+ size = 128;
+ switch(generic_state->frame_type)
+ {
+ case SLICE_TYPE_P:
+ memcpy(data,gen9_avc_skip_value_p[block_based_skip_enable][transform_8x8_mode_flag],size * sizeof(unsigned char));
+ break;
+ case SLICE_TYPE_B:
+ memcpy(data,gen9_avc_skip_value_b[block_based_skip_enable][transform_8x8_mode_flag],size * sizeof(unsigned char));
+ break;
+ default:
+ /*SLICE_TYPE_I,no change */
+ break;
+ }
+
+ if((generic_state->frame_type != SLICE_TYPE_I) && avc_state->non_ftq_skip_threshold_lut_input_enable)
+ {
+ for(i = 0; i< 52 ; i++)
+ {
+ *(data + 1 + (i * 2)) = (unsigned char)i965_avc_calc_skip_value(block_based_skip_enable,transform_8x8_mode_flag,avc_state->non_ftq_skip_threshold_lut[i]);
+ }
+ }
+ data += size;
+
+ /*fill the qp for ref list*/
+ size = 128;
+ data += size;
+ size = 128;
+ data += size;
+
+ /*mv cost and mode cost*/
+ size = 1664;
+ memcpy(data,(unsigned char *)&gen75_avc_mode_mv_cost_table[table_idx][0][0],size * sizeof(unsigned char));
+
+ if(avc_state->old_mode_cost_enable)
+ { data_tmp = data;
+ for(i = 0; i < 52 ; i++)
+ {
+ *(data_tmp +3) = (unsigned int)gen9_avc_old_intra_mode_cost[i];
+ data_tmp += 16;
+ }
+ }
+
+ if(avc_state->ftq_skip_threshold_lut_input_enable)
+ {
+ for(i = 0; i < 52 ; i++)
+ {
+ *(data + (i * 32) + 24) =
+ *(data + (i * 32) + 25) =
+ *(data + (i * 32) + 27) =
+ *(data + (i * 32) + 28) =
+ *(data + (i * 32) + 29) =
+ *(data + (i * 32) + 30) =
+ *(data + (i * 32) + 31) = avc_state->ftq_skip_threshold_lut[i];
+ }
+
+ }
+ data += size;
+
+ /*ref cost*/
+ size = 128;
+ memcpy(data,(unsigned char *)&gen9_avc_ref_cost[table_idx][0],size * sizeof(unsigned char));
+
+ i965_unmap_gpe_resource(gpe_resource);
+}
+static void
+gen9_avc_set_curbe_brc_init_reset(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ gen9_avc_brc_init_reset_curbe_data *cmd;
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ double input_bits_per_frame = 0;
+ double bps_ratio = 0;
+ VAEncSequenceParameterBufferH264 * seq_param = avc_state->seq_param;
+ struct avc_param common_param;
+
+ cmd = i965_gpe_context_map_curbe(gpe_context);
+
+ memcpy(cmd,&gen9_avc_brc_init_reset_curbe_init_data,sizeof(gen9_avc_brc_init_reset_curbe_data));
+
+ memset(&common_param,0,sizeof(common_param));
+ common_param.frame_width_in_pixel = generic_state->frame_width_in_pixel;
+ common_param.frame_height_in_pixel = generic_state->frame_height_in_pixel;
+ common_param.frame_width_in_mbs = generic_state->frame_width_in_mbs;
+ common_param.frame_height_in_mbs = generic_state->frame_height_in_mbs;
+ common_param.frames_per_100s = generic_state->frames_per_100s;
+ common_param.vbv_buffer_size_in_bit = generic_state->vbv_buffer_size_in_bit;
+ common_param.target_bit_rate = generic_state->target_bit_rate;
+
+ cmd->dw0.profile_level_max_frame = i965_avc_get_profile_level_max_frame(&common_param,seq_param->level_idc);
+ cmd->dw1.init_buf_full_in_bits = generic_state->init_vbv_buffer_fullness_in_bit;
+ cmd->dw2.buf_size_in_bits = generic_state->vbv_buffer_size_in_bit;
+ cmd->dw3.average_bit_rate = generic_state->target_bit_rate * 1000;
+ cmd->dw4.max_bit_rate = generic_state->max_bit_rate * 1000;
+ cmd->dw8.gop_p = (generic_state->gop_ref_distance)?((generic_state->gop_size -1)/generic_state->gop_ref_distance):0;
+ cmd->dw9.gop_b = (generic_state->gop_size - 1 - cmd->dw8.gop_p);
+ cmd->dw9.frame_width_in_bytes = generic_state->frame_width_in_pixel;
+ cmd->dw10.frame_height_in_bytes = generic_state->frame_height_in_pixel;
+ cmd->dw12.no_slices = avc_state->slice_num;
+
+ //VUI
+ if(seq_param->vui_parameters_present_flag && generic_state->internal_rate_mode != INTEL_BRC_AVBR )
+ {
+ cmd->dw4.max_bit_rate = cmd->dw4.max_bit_rate;
+ if(generic_state->internal_rate_mode == VA_RC_CBR)
+ {
+ cmd->dw3.average_bit_rate = cmd->dw4.max_bit_rate;
+
+ }
+
+ }
+ cmd->dw6.frame_rate_m = generic_state->frames_per_100s;
+ cmd->dw7.frame_rate_d = 100;
+ cmd->dw8.brc_flag = 0;
+ cmd->dw8.brc_flag |= (generic_state->mb_brc_enabled)? 0 : 0x8000;
+
+
+ if(generic_state->internal_rate_mode == VA_RC_CBR)
+ { //CBR
+ cmd->dw4.max_bit_rate = cmd->dw3.average_bit_rate;
+ cmd->dw8.brc_flag = cmd->dw8.brc_flag |INTEL_ENCODE_BRCINIT_ISCBR;
+
+ }else if(generic_state->internal_rate_mode == VA_RC_VBR)
+ {//VBR
+ if(cmd->dw4.max_bit_rate < cmd->dw3.average_bit_rate)
+ {
+ cmd->dw4.max_bit_rate = cmd->dw3.average_bit_rate << 1;
+ }
+ cmd->dw8.brc_flag = cmd->dw8.brc_flag |INTEL_ENCODE_BRCINIT_ISVBR;
+
+ }else if(generic_state->internal_rate_mode == INTEL_BRC_AVBR)
+ { //AVBR
+ cmd->dw4.max_bit_rate =cmd->dw3.average_bit_rate;
+ cmd->dw8.brc_flag = cmd->dw8.brc_flag |INTEL_ENCODE_BRCINIT_ISAVBR;
+
+ }
+ //igonre icq/vcm/qvbr
+
+ cmd->dw10.avbr_accuracy = generic_state->avbr_curracy;
+ cmd->dw11.avbr_convergence = generic_state->avbr_convergence;
+
+ //frame bits
+ input_bits_per_frame = (double)(cmd->dw4.max_bit_rate) * (double)(cmd->dw7.frame_rate_d)/(double)(cmd->dw6.frame_rate_m);;
+
+ if(cmd->dw2.buf_size_in_bits == 0)
+ {
+ cmd->dw2.buf_size_in_bits = (unsigned int)(input_bits_per_frame * 4);
+ }
+
+ if(cmd->dw1.init_buf_full_in_bits == 0)
+ {
+ cmd->dw1.init_buf_full_in_bits = cmd->dw2.buf_size_in_bits * 7/8;
+ }
+ if(cmd->dw1.init_buf_full_in_bits < (unsigned int)(input_bits_per_frame * 2))
+ {
+ cmd->dw1.init_buf_full_in_bits = (unsigned int)(input_bits_per_frame * 2);
+ }
+ if(cmd->dw1.init_buf_full_in_bits > cmd->dw2.buf_size_in_bits)
+ {
+ cmd->dw1.init_buf_full_in_bits = cmd->dw2.buf_size_in_bits;
+ }
+
+ //AVBR
+ if(generic_state->internal_rate_mode == INTEL_BRC_AVBR)
+ {
+ cmd->dw2.buf_size_in_bits = 2 * generic_state->target_bit_rate * 1000;
+ cmd->dw1.init_buf_full_in_bits = (unsigned int)(3 * cmd->dw2.buf_size_in_bits/4);
+
+ }
+
+ bps_ratio = input_bits_per_frame / (cmd->dw2.buf_size_in_bits/30.0);
+ bps_ratio = (bps_ratio < 0.1)? 0.1:(bps_ratio > 3.5)?3.5:bps_ratio;
+
+
+ cmd->dw16.deviation_threshold_0_pand_b = (unsigned int)(-50 * pow(0.90,bps_ratio));
+ cmd->dw16.deviation_threshold_1_pand_b = (unsigned int)(-50 * pow(0.66,bps_ratio));
+ cmd->dw16.deviation_threshold_2_pand_b = (unsigned int)(-50 * pow(0.46,bps_ratio));
+ cmd->dw16.deviation_threshold_3_pand_b = (unsigned int)(-50 * pow(0.3, bps_ratio));
+ cmd->dw17.deviation_threshold_4_pand_b = (unsigned int)(50 * pow(0.3, bps_ratio));
+ cmd->dw17.deviation_threshold_5_pand_b = (unsigned int)(50 * pow(0.46, bps_ratio));
+ cmd->dw17.deviation_threshold_6_pand_b = (unsigned int)(50 * pow(0.7, bps_ratio));
+ cmd->dw17.deviation_threshold_7_pand_b = (unsigned int)(50 * pow(0.9, bps_ratio));
+ cmd->dw18.deviation_threshold_0_vbr = (unsigned int)(-50 * pow(0.9, bps_ratio));
+ cmd->dw18.deviation_threshold_1_vbr = (unsigned int)(-50 * pow(0.7, bps_ratio));
+ cmd->dw18.deviation_threshold_2_vbr = (unsigned int)(-50 * pow(0.5, bps_ratio));
+ cmd->dw18.deviation_threshold_3_vbr = (unsigned int)(-50 * pow(0.3, bps_ratio));
+ cmd->dw19.deviation_threshold_4_vbr = (unsigned int)(100 * pow(0.4, bps_ratio));
+ cmd->dw19.deviation_threshold_5_vbr = (unsigned int)(100 * pow(0.5, bps_ratio));
+ cmd->dw19.deviation_threshold_6_vbr = (unsigned int)(100 * pow(0.75,bps_ratio));
+ cmd->dw19.deviation_threshold_7_vbr = (unsigned int)(100 * pow(0.9, bps_ratio));
+ cmd->dw20.deviation_threshold_0_i = (unsigned int)(-50 * pow(0.8, bps_ratio));
+ cmd->dw20.deviation_threshold_1_i = (unsigned int)(-50 * pow(0.6, bps_ratio));
+ cmd->dw20.deviation_threshold_2_i = (unsigned int)(-50 * pow(0.34,bps_ratio));
+ cmd->dw20.deviation_threshold_3_i = (unsigned int)(-50 * pow(0.2, bps_ratio));
+ cmd->dw21.deviation_threshold_4_i = (unsigned int)(50 * pow(0.2, bps_ratio));
+ cmd->dw21.deviation_threshold_5_i = (unsigned int)(50 * pow(0.4, bps_ratio));
+ cmd->dw21.deviation_threshold_6_i = (unsigned int)(50 * pow(0.66, bps_ratio));
+ cmd->dw21.deviation_threshold_7_i = (unsigned int)(50 * pow(0.9, bps_ratio));
+
+ cmd->dw22.sliding_window_size = generic_state->window_size;
+
+ i965_gpe_context_unmap_curbe(gpe_context);
+
+ return;
+}
+
+static void
+gen9_avc_send_surface_brc_init_reset(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param_mbenc)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_brc_history_buffer,
+ 0,
+ avc_ctx->res_brc_history_buffer.size,
+ 0,
+ GEN9_AVC_BRC_INIT_RESET_HISTORY_INDEX);
+
+ gen9_add_buffer_2d_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_brc_dist_data_surface,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_BRC_INIT_RESET_DISTORTION_INDEX);
+
+ return;
+}
+
+static VAStatus
+gen9_avc_kernel_brc_init_reset(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
+
+ struct i965_gpe_context *gpe_context;
+ struct gpe_media_object_parameter media_object_param;
+ struct gpe_media_object_inline_data media_object_inline_data;
+ int media_function = 0;
+ int kernel_idx = GEN9_AVC_KERNEL_BRC_INIT;
+
+ media_function = INTEL_MEDIA_STATE_BRC_INIT_RESET;
+
+ if(generic_state->brc_inited)
+ kernel_idx = GEN9_AVC_KERNEL_BRC_RESET;
+
+ gpe_context = &(avc_ctx->context_brc.gpe_contexts[kernel_idx]);
+
+ gen8_gpe_context_init(ctx, gpe_context);
+ gen9_gpe_reset_binding_table(ctx, gpe_context);
+
+ generic_ctx->pfn_set_curbe_brc_init_reset(ctx,encode_state,gpe_context,encoder_context,NULL);
+
+ generic_ctx->pfn_send_brc_init_reset_surface(ctx,encode_state,gpe_context,encoder_context,NULL);
+
+ gen8_gpe_setup_interface_data(ctx, gpe_context);
+
+ memset(&media_object_param, 0, sizeof(media_object_param));
+ memset(&media_object_inline_data, 0, sizeof(media_object_inline_data));
+ media_object_param.pinline_data = &media_object_inline_data;
+ media_object_param.inline_size = sizeof(media_object_inline_data);
+
+ gen9_avc_run_kernel_media_object(ctx, encoder_context,
+ gpe_context,
+ media_function,
+ &media_object_param);
+
+ return VA_STATUS_SUCCESS;
+}
+
+static void
+gen9_avc_set_curbe_brc_frame_update(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ gen9_avc_frame_brc_update_curbe_data *cmd;
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+ struct avc_param common_param;
+ VAEncSequenceParameterBufferH264 * seq_param = avc_state->seq_param;
+
+ obj_surface = encode_state->reconstructed_object;
+
+ if (!obj_surface || !obj_surface->private_data)
+ return;
+ avc_priv_surface = obj_surface->private_data;
+
+ cmd = i965_gpe_context_map_curbe(gpe_context);
+
+ memcpy(cmd,&gen9_avc_frame_brc_update_curbe_init_data,sizeof(gen9_avc_frame_brc_update_curbe_data));
+
+ cmd->dw5.target_size_flag = 0 ;
+ if(generic_state->brc_init_current_target_buf_full_in_bits > (double)generic_state->brc_init_reset_buf_size_in_bits)
+ {
+ /*overflow*/
+ generic_state->brc_init_current_target_buf_full_in_bits -= (double)generic_state->brc_init_reset_buf_size_in_bits;
+ cmd->dw5.target_size_flag = 1 ;
+ }
+
+ if(generic_state->skip_frame_enbale)
+ {
+ cmd->dw6.num_skip_frames = generic_state->num_skip_frames ;
+ cmd->dw7.size_skip_frames = generic_state->size_skip_frames;
+
+ generic_state->brc_init_current_target_buf_full_in_bits += generic_state->brc_init_reset_input_bits_per_frame * generic_state->num_skip_frames;
+
+ }
+ cmd->dw0.target_size = (unsigned int)generic_state->brc_init_current_target_buf_full_in_bits ;
+ cmd->dw1.frame_number = generic_state->seq_frame_number ;
+ cmd->dw2.size_of_pic_headers = generic_state->herder_bytes_inserted << 3 ;
+ cmd->dw5.cur_frame_type = generic_state->frame_type ;
+ cmd->dw5.brc_flag = 0 ;
+ cmd->dw5.brc_flag |= (avc_priv_surface->is_as_ref)?INTEL_ENCODE_BRCUPDATE_IS_REFERENCE:0 ;
+
+ if(avc_state->multi_pre_enable)
+ {
+ cmd->dw5.brc_flag |= INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP ;
+ cmd->dw14.qp_index_of_cur_pic = avc_priv_surface->frame_idx ; //do not know this. use -1
+ }
+
+ cmd->dw5.max_num_paks = generic_state->num_pak_passes ;
+ if(avc_state->min_max_qp_enable)
+ {
+ switch(generic_state->frame_type)
+ {
+ case SLICE_TYPE_I:
+ cmd->dw6.minimum_qp = avc_state->min_qp_i ;
+ cmd->dw6.maximum_qp = avc_state->max_qp_i ;
+ break;
+ case SLICE_TYPE_P:
+ cmd->dw6.minimum_qp = avc_state->min_qp_p ;
+ cmd->dw6.maximum_qp = avc_state->max_qp_p ;
+ break;
+ case SLICE_TYPE_B:
+ cmd->dw6.minimum_qp = avc_state->min_qp_b ;
+ cmd->dw6.maximum_qp = avc_state->max_qp_b ;
+ break;
+ }
+ }else
+ {
+ cmd->dw6.minimum_qp = 0 ;
+ cmd->dw6.maximum_qp = 0 ;
+ }
+ cmd->dw6.enable_force_skip = avc_state->enable_force_skip ;
+ cmd->dw6.enable_sliding_window = 0 ;
+
+ generic_state->brc_init_current_target_buf_full_in_bits += generic_state->brc_init_reset_input_bits_per_frame;
+
+ if(generic_state->internal_rate_mode == INTEL_BRC_AVBR)
+ {
+ cmd->dw3.start_gadj_frame0 = (unsigned int)((10 * generic_state->avbr_convergence) / (double)150);
+ cmd->dw3.start_gadj_frame1 = (unsigned int)((50 * generic_state->avbr_convergence) / (double)150);
+ cmd->dw4.start_gadj_frame2 = (unsigned int)((100 * generic_state->avbr_convergence) / (double)150);
+ cmd->dw4.start_gadj_frame3 = (unsigned int)((150 * generic_state->avbr_convergence) / (double)150);
+ cmd->dw11.g_rate_ratio_threshold_0 = (unsigned int)((100 - (generic_state->avbr_curracy / (double)30)*(100 - 40)));
+ cmd->dw11.g_rate_ratio_threshold_1 = (unsigned int)((100 - (generic_state->avbr_curracy / (double)30)*(100 - 75)));
+ cmd->dw12.g_rate_ratio_threshold_2 = (unsigned int)((100 - (generic_state->avbr_curracy / (double)30)*(100 - 97)));
+ cmd->dw12.g_rate_ratio_threshold_3 = (unsigned int)((100 + (generic_state->avbr_curracy / (double)30)*(103 - 100)));
+ cmd->dw12.g_rate_ratio_threshold_4 = (unsigned int)((100 + (generic_state->avbr_curracy / (double)30)*(125 - 100)));
+ cmd->dw12.g_rate_ratio_threshold_5 = (unsigned int)((100 + (generic_state->avbr_curracy / (double)30)*(160 - 100)));
+
+ }
+ cmd->dw15.enable_roi = generic_state->brc_roi_enable ;
+
+ memset(&common_param,0,sizeof(common_param));
+ common_param.frame_width_in_pixel = generic_state->frame_width_in_pixel;
+ common_param.frame_height_in_pixel = generic_state->frame_height_in_pixel;
+ common_param.frame_width_in_mbs = generic_state->frame_width_in_mbs;
+ common_param.frame_height_in_mbs = generic_state->frame_height_in_mbs;
+ common_param.frames_per_100s = generic_state->frames_per_100s;
+ common_param.vbv_buffer_size_in_bit = generic_state->vbv_buffer_size_in_bit;
+ common_param.target_bit_rate = generic_state->target_bit_rate;
+
+ cmd->dw19.user_max_frame = i965_avc_get_profile_level_max_frame(&common_param,seq_param->level_idc);
+ i965_gpe_context_unmap_curbe(gpe_context);
+
+ return;
+}
+
+static void
+gen9_avc_send_surface_brc_frame_update(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param_brc)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct brc_param * param = (struct brc_param *)param_brc ;
+ struct i965_gpe_context * gpe_context_mbenc = param->gpe_context_mbenc;
+
+
+ /* brc history buffer*/
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_brc_history_buffer,
+ 0,
+ avc_ctx->res_brc_history_buffer.size,
+ 0,
+ GEN9_AVC_FRAME_BRC_UPDATE_HISTORY_INDEX);
+
+ /* previous pak buffer*/
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_brc_pre_pak_statistics_output_buffer,
+ 0,
+ avc_ctx->res_brc_pre_pak_statistics_output_buffer.size,
+ 0,
+ GEN9_AVC_FRAME_BRC_UPDATE_PAK_STATISTICS_OUTPUT_INDEX);
+
+ /* image state command buffer read only*/
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_brc_image_state_read_buffer,
+ 0,
+ avc_ctx->res_brc_image_state_read_buffer.size,
+ 0,
+ GEN9_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_READ_INDEX);
+
+ /* image state command buffer write only*/
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_brc_image_state_write_buffer,
+ 0,
+ avc_ctx->res_brc_image_state_write_buffer.size,
+ 0,
+ GEN9_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_WRITE_INDEX);
+
+ /* Mbenc curbe input buffer */
+ gen9_add_dri_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_context_mbenc->dynamic_state.bo,
+ 0,
+ ALIGN(gpe_context_mbenc->curbe.length, 64),
+ gpe_context_mbenc->curbe.offset,
+ GEN9_AVC_FRAME_BRC_UPDATE_MBENC_CURBE_READ_INDEX);
+ /* Mbenc curbe output buffer */
+ gen9_add_dri_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_context_mbenc->dynamic_state.bo,
+ 0,
+ ALIGN(gpe_context_mbenc->curbe.length, 64),
+ gpe_context_mbenc->curbe.offset,
+ GEN9_AVC_FRAME_BRC_UPDATE_MBENC_CURBE_WRITE_INDEX);
+
+ /* AVC_ME Distortion 2D surface buffer,input/output. is it res_brc_dist_data_surface*/
+ gen9_add_buffer_2d_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_brc_dist_data_surface,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_FRAME_BRC_UPDATE_DISTORTION_INDEX);
+
+ /* BRC const data 2D surface buffer */
+ gen9_add_buffer_2d_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_brc_const_data_buffer,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_FRAME_BRC_UPDATE_CONSTANT_DATA_INDEX);
+
+ /* MB statistical data surface*/
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_mb_status_buffer,
+ 0,
+ avc_ctx->res_mb_status_buffer.size,
+ 0,
+ GEN9_AVC_FRAME_BRC_UPDATE_MB_STATUS_INDEX);
+
+ return;
+}
+
+static VAStatus
+gen9_avc_kernel_brc_frame_update(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+
+ struct i965_gpe_context *gpe_context;
+ struct gpe_media_object_parameter media_object_param;
+ struct gpe_media_object_inline_data media_object_inline_data;
+ int media_function = 0;
+ int kernel_idx = 0;
+ unsigned int mb_const_data_buffer_in_use,mb_qp_buffer_in_use;
+ unsigned int brc_enabled = 0;
+ unsigned int roi_enable = (generic_state->num_roi > 0)?1:0;
+ unsigned int dirty_roi_enable = ((generic_state->dirty_num_roi > 0) && (generic_state->frame_type == SLICE_TYPE_P) && (0));
+
+ /* the following set the mbenc curbe*/
+ struct mbenc_param curbe_mbenc_param ;
+ struct brc_param curbe_brc_param ;
+
+ mb_const_data_buffer_in_use =
+ generic_state->mb_brc_enabled ||
+ roi_enable ||
+ dirty_roi_enable ||
+ avc_state->mb_qp_data_enable ||
+ avc_state->rolling_intra_refresh_enable;
+ mb_qp_buffer_in_use =
+ generic_state->mb_brc_enabled ||
+ generic_state->brc_roi_enable ||
+ avc_state->mb_qp_data_enable;
+
+ switch(generic_state->kernel_mode)
+ {
+ case INTEL_ENC_KERNEL_NORMAL :
+ {
+ kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_NORMAL_I;
+ break;
+ }
+ case INTEL_ENC_KERNEL_PERFORMANCE :
+ {
+ kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_PERFORMANCE_I;
+ break;
+ }
+ case INTEL_ENC_KERNEL_QUALITY :
+ {
+ kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_QUALITY_I;
+ break;
+ }
+ default:
+ assert(0);
+
+ }
+
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ kernel_idx += 1;
+ }
+ else if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ kernel_idx += 2;
+ }
+
+ gpe_context = &(avc_ctx->context_mbenc.gpe_contexts[kernel_idx]);
+ gen8_gpe_context_init(ctx, gpe_context);
+
+ memset(&curbe_mbenc_param,0,sizeof(struct mbenc_param));
+
+ curbe_mbenc_param.mb_const_data_buffer_in_use = mb_const_data_buffer_in_use;
+ curbe_mbenc_param.mb_qp_buffer_in_use = mb_qp_buffer_in_use;
+ curbe_mbenc_param.mbenc_i_frame_dist_in_use = 0;
+ curbe_mbenc_param.brc_enabled = brc_enabled;
+ curbe_mbenc_param.roi_enabled = roi_enable;
+
+ /* set curbe mbenc*/
+ generic_ctx->pfn_set_curbe_mbenc(ctx,encode_state,gpe_context,encoder_context,&curbe_mbenc_param);
+ avc_state->mbenc_curbe_set_in_brc_update = 1;
+
+ /*begin brc frame update*/
+ memset(&curbe_brc_param,0,sizeof(struct brc_param));
+ curbe_brc_param.gpe_context_mbenc = gpe_context;
+ media_function = INTEL_MEDIA_STATE_BRC_UPDATE;
+ kernel_idx = GEN9_AVC_KERNEL_BRC_FRAME_UPDATE;
+ gpe_context = &(avc_ctx->context_brc.gpe_contexts[kernel_idx]);
+ curbe_brc_param.gpe_context_brc_frame_update = gpe_context;
+
+ gen8_gpe_context_init(ctx, gpe_context);
+ gen9_gpe_reset_binding_table(ctx, gpe_context);
+ /*brc copy ignored*/
+
+ /* set curbe frame update*/
+ generic_ctx->pfn_set_curbe_brc_frame_update(ctx,encode_state,gpe_context,encoder_context,&curbe_brc_param);
+
+ /* load brc constant data, is it same as mbenc mb brc constant data? no.*/
+ if(avc_state->multi_pre_enable)
+ {
+ gen9_avc_init_brc_const_data(ctx,encode_state,encoder_context);
+ }else
+ {
+ gen9_avc_init_brc_const_data_old(ctx,encode_state,encoder_context);
+ }
+ /* image state construct*/
+ gen9_avc_set_image_state(ctx,encode_state,encoder_context,&(avc_ctx->res_brc_image_state_read_buffer));
+ /* set surface frame mbenc*/
+ generic_ctx->pfn_send_brc_frame_update_surface(ctx,encode_state,gpe_context,encoder_context,&curbe_brc_param);
+
+
+ gen8_gpe_setup_interface_data(ctx, gpe_context);
+
+ memset(&media_object_param, 0, sizeof(media_object_param));
+ memset(&media_object_inline_data, 0, sizeof(media_object_inline_data));
+ media_object_param.pinline_data = &media_object_inline_data;
+ media_object_param.inline_size = sizeof(media_object_inline_data);
+
+ gen9_avc_run_kernel_media_object(ctx, encoder_context,
+ gpe_context,
+ media_function,
+ &media_object_param);
+
+ return VA_STATUS_SUCCESS;
+}
+
+static void
+gen9_avc_set_curbe_brc_mb_update(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ gen9_avc_mb_brc_curbe_data *cmd;
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+
+ cmd = i965_gpe_context_map_curbe(gpe_context);
+ memset(cmd,0,sizeof(gen9_avc_mb_brc_curbe_data));
+
+ cmd->dw0.cur_frame_type = generic_state->frame_type;
+ if(generic_state->brc_roi_enable)
+ {
+ cmd->dw0.enable_roi = 1;
+ }else
+ {
+ cmd->dw0.enable_roi = 0;
+ }
+
+ i965_gpe_context_unmap_curbe(gpe_context);
+
+ return;
+}
+
+static void
+gen9_avc_send_surface_brc_mb_update(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param_mbenc)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+
+ /* brc history buffer*/
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_brc_history_buffer,
+ 0,
+ avc_ctx->res_brc_history_buffer.size,
+ 0,
+ GEN9_AVC_MB_BRC_UPDATE_HISTORY_INDEX);
+
+ /* MB qp data buffer is it same as res_mbbrc_mb_qp_data_surface*/
+ if(generic_state->mb_brc_enabled)
+ {
+ gen9_add_buffer_2d_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_mbbrc_mb_qp_data_surface,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MB_BRC_UPDATE_MB_QP_INDEX);
+
+ }
+
+ /* BRC roi feature*/
+ if(generic_state->brc_roi_enable)
+ {
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_mbbrc_roi_surface,
+ 0,
+ avc_ctx->res_mbbrc_roi_surface.size,
+ 0,
+ GEN9_AVC_MB_BRC_UPDATE_ROI_INDEX);
+
+ }
+
+ /* MB statistical data surface*/
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ &avc_ctx->res_mb_status_buffer,
+ 0,
+ avc_ctx->res_mb_status_buffer.size,
+ 0,
+ GEN9_AVC_MB_BRC_UPDATE_MB_STATUS_INDEX);
+
+ return;
+}
+
+static VAStatus
+gen9_avc_kernel_brc_mb_update(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
+
+ struct i965_gpe_context *gpe_context;
+ struct gpe_media_object_walker_parameter media_object_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
+ int media_function = 0;
+ int kernel_idx = 0;
+
+ media_function = INTEL_MEDIA_STATE_MB_BRC_UPDATE;
+ kernel_idx = GEN9_AVC_KERNEL_BRC_MB_UPDATE;
+ gpe_context = &(avc_ctx->context_brc.gpe_contexts[kernel_idx]);
+
+ gen8_gpe_context_init(ctx, gpe_context);
+ gen9_gpe_reset_binding_table(ctx, gpe_context);
+
+ /* set curbe brc mb update*/
+ generic_ctx->pfn_set_curbe_brc_mb_update(ctx,encode_state,gpe_context,encoder_context,NULL);
+
+
+ /* set surface brc mb update*/
+ generic_ctx->pfn_send_brc_mb_update_surface(ctx,encode_state,gpe_context,encoder_context,NULL);
+
+
+ gen8_gpe_setup_interface_data(ctx, gpe_context);
+
+ memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
+ /* the scaling is based on 8x8 blk level */
+ kernel_walker_param.resolution_x = (generic_state->frame_width_in_mbs + 1)/2;
+ kernel_walker_param.resolution_y = (generic_state->frame_height_in_mbs + 1)/2 ;
+ kernel_walker_param.no_dependency = 1;
+
+ i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
+
+ gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
+ gpe_context,
+ media_function,
+ &media_object_walker_param);
+
+ return VA_STATUS_SUCCESS;
+}
+
+/*
+mbenc kernel related function,it include intra dist kernel
+*/
+static int
+gen9_avc_get_biweight(int dist_scale_factor_ref_id0_list0, unsigned short weighted_bipredidc)
+{
+ int biweight = 32; // default value
+
+ /* based on kernel HLD*/
+ if (weighted_bipredidc != INTEL_AVC_WP_MODE_IMPLICIT)
+ {
+ biweight = 32;
+ }
+ else
+ {
+ biweight = (dist_scale_factor_ref_id0_list0 + 2) >> 2;
+
+ if (biweight != 16 && biweight != 21 &&
+ biweight != 32 && biweight != 43 && biweight != 48)
+ {
+ biweight = 32; // If # of B-pics between two refs is more than 3. VME does not support it.
+ }
+ }
+
+ return biweight;
+}
+
+static void
+gen9_avc_get_dist_scale_factor(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+
+ int max_num_references;
+ VAPictureH264 *curr_pic;
+ VAPictureH264 *ref_pic_l0;
+ VAPictureH264 *ref_pic_l1;
+ int i = 0;
+ int tb = 0;
+ int td = 0;
+ int tx = 0;
+ int tmp = 0;
+ int poc0 = 0;
+ int poc1 = 0;
+
+ max_num_references = pic_param->num_ref_idx_l0_active_minus1 + 1;
+
+ memset(avc_state->dist_scale_factor_list0,0,32*sizeof(unsigned int));
+ curr_pic = &pic_param->CurrPic;
+ for(i = 0; i < max_num_references; i++)
+ {
+ ref_pic_l0 = &(slice_param->RefPicList0[i]);
+
+ if((ref_pic_l0->flags & VA_PICTURE_H264_INVALID) ||
+ (ref_pic_l0->picture_id == VA_INVALID_SURFACE) )
+ break;
+ ref_pic_l1 = &(slice_param->RefPicList1[0]);
+ if((ref_pic_l0->flags & VA_PICTURE_H264_INVALID) ||
+ (ref_pic_l0->picture_id == VA_INVALID_SURFACE) )
+ break;
+
+ poc0 = (curr_pic->TopFieldOrderCnt - ref_pic_l0->TopFieldOrderCnt);
+ poc1 = (ref_pic_l1->TopFieldOrderCnt - ref_pic_l0->TopFieldOrderCnt);
+ CLIP(poc0,-128,127);
+ CLIP(poc1,-128,127);
+ tb = poc0;
+ td = poc1;
+
+ if(td == 0)
+ {
+ td = 1;
+ }
+ tmp = (td/2 > 0)?(td/2):(-(td/2));
+ tx = (16384 + tmp)/td ;
+ tmp = (tb*tx+32)>>6;
+ CLIP(tmp,-1024,1023);
+ avc_state->dist_scale_factor_list0[i] = tmp;
+ }
+ return;
+}
+
+static unsigned int
+gen9_avc_get_qp_from_ref_list(VADriverContextP ctx,
+ VAEncSliceParameterBufferH264 *slice_param,
+ int list,
+ int ref_frame_idx)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+ VASurfaceID surface_id;
+
+ assert(slice_param);
+ assert(list < 2);
+
+ if(list == 0)
+ {
+ if(ref_frame_idx < slice_param->num_ref_idx_l0_active_minus1 + 1)
+ surface_id = slice_param->RefPicList0[ref_frame_idx].picture_id;
+ else
+ return 0;
+ }else
+ {
+ if(ref_frame_idx < slice_param->num_ref_idx_l1_active_minus1 + 1)
+ surface_id = slice_param->RefPicList1[ref_frame_idx].picture_id;
+ else
+ return 0;
+ }
+ obj_surface = SURFACE(surface_id);
+ if(obj_surface && obj_surface->private_data)
+ {
+ avc_priv_surface = obj_surface->private_data;
+ return avc_priv_surface->qp_value;
+ }else
+ {
+ return 0;
+ }
+}
+
+static void
+gen9_avc_load_mb_brc_const_data(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+
+ struct i965_gpe_resource *gpe_resource = NULL;
+ unsigned int * data =NULL;
+ unsigned int * data_tmp = NULL;
+ unsigned int size = 16 * 52;
+ unsigned int table_idx = 0;
+ unsigned int block_based_skip_enable = avc_state->block_based_skip_enable;
+ unsigned int transform_8x8_mode_flag = pic_param->pic_fields.bits.transform_8x8_mode_flag;
+ int i = 0;
+
+ gpe_resource = &(avc_ctx->res_mbbrc_const_data_buffer);
+ assert(gpe_resource);
+ data = i965_map_gpe_resource(gpe_resource);
+ assert(data);
+
+ table_idx = slice_type_kernel[generic_state->frame_type];
+
+ memcpy(data,gen9_avc_mb_brc_const_data[table_idx][0],size*sizeof(unsigned int));
+
+ data_tmp = data;
+
+ switch(generic_state->frame_type)
+ {
+ case SLICE_TYPE_I:
+ for(i = 0; i < 52 ; i++)
+ {
+ if(avc_state->old_mode_cost_enable)
+ *data = (unsigned int)gen9_avc_old_intra_mode_cost[i];
+ data += 16;
+ }
+ break;
+ case SLICE_TYPE_P:
+ case SLICE_TYPE_B:
+ for(i = 0; i < 52 ; i++)
+ {
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ if(avc_state->skip_bias_adjustment_enable)
+ *(data + 3) = (unsigned int)gen9_avc_mv_cost_p_skip_adjustment[i];
+ }
+ if(avc_state->non_ftq_skip_threshold_lut_input_enable)
+ {
+ *(data + 9) = (unsigned int)i965_avc_calc_skip_value(block_based_skip_enable,transform_8x8_mode_flag,avc_state->non_ftq_skip_threshold_lut[i]);
+ }else if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ *(data + 9) = (unsigned int)gen9_avc_skip_value_p[block_based_skip_enable][transform_8x8_mode_flag][i];
+ }else
+ {
+ *(data + 9) = (unsigned int)gen9_avc_skip_value_b[block_based_skip_enable][transform_8x8_mode_flag][i];
+ }
+
+ if(avc_state->adaptive_intra_scaling_enable)
+ {
+ *(data + 10) = (unsigned int)gen9_avc_adaptive_intra_scaling_factor[i];
+ }else
+ {
+ *(data + 10) = (unsigned int)gen9_avc_intra_scaling_factor[i];
+
+ }
+ data += 16;
+
+ }
+ break;
+ default:
+ assert(0);
+ }
+
+ data = data_tmp;
+ for(i = 0; i < 52 ; i++)
+ {
+ if(avc_state->ftq_skip_threshold_lut_input_enable)
+ {
+ *(data + 6) = (avc_state->ftq_skip_threshold_lut[i] |
+ (avc_state->ftq_skip_threshold_lut[i] <<16) |
+ (avc_state->ftq_skip_threshold_lut[i] <<24) );
+ *(data + 7) = (avc_state->ftq_skip_threshold_lut[i] |
+ (avc_state->ftq_skip_threshold_lut[i] <<8) |
+ (avc_state->ftq_skip_threshold_lut[i] <<16) |
+ (avc_state->ftq_skip_threshold_lut[i] <<24) );
+ }
+
+ if(avc_state->kernel_trellis_enable)
+ {
+ *(data + 11) = (unsigned int)avc_state->lamda_value_lut[i][0];
+ *(data + 12) = (unsigned int)avc_state->lamda_value_lut[i][1];
+
+ }
+ data += 16;
+
+ }
+ i965_unmap_gpe_resource(gpe_resource);
+}
+
+static void
+gen9_avc_set_curbe_mbenc(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ gen9_avc_mbenc_curbe_data *cmd;
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+ VASurfaceID surface_id;
+ struct object_surface *obj_surface;
+
+ struct mbenc_param * curbe_param = (struct mbenc_param *)param ;
+ unsigned char qp = 0;
+ unsigned char me_method = 0;
+ unsigned int mbenc_i_frame_dist_in_use = curbe_param->mbenc_i_frame_dist_in_use;
+ unsigned int table_idx = 0;
+
+ unsigned int preset = generic_state->preset;
+ me_method = (generic_state->frame_type == SLICE_TYPE_B)? gen9_avc_b_me_method[preset]:gen9_avc_p_me_method[preset];
+ qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+
+ cmd = (gen9_avc_mbenc_curbe_data *)i965_gpe_context_map_curbe(gpe_context);
+ memset(cmd,0,sizeof(gen9_avc_mbenc_curbe_data));
+
+ if(mbenc_i_frame_dist_in_use)
+ {
+ memcpy(cmd,gen9_avc_mbenc_curbe_i_frame_dist_init_data,sizeof(gen9_avc_mbenc_curbe_data));
+
+ }else
+ {
+ switch(generic_state->frame_type)
+ {
+ case SLICE_TYPE_I:
+ memcpy(cmd,gen9_avc_mbenc_curbe_normal_i_frame_init_data,sizeof(gen9_avc_mbenc_curbe_data));
+ break;
+ case SLICE_TYPE_P:
+ memcpy(cmd,gen9_avc_mbenc_curbe_normal_p_frame_init_data,sizeof(gen9_avc_mbenc_curbe_data));
+ break;
+ case SLICE_TYPE_B:
+ memcpy(cmd,gen9_avc_mbenc_curbe_normal_b_frame_init_data,sizeof(gen9_avc_mbenc_curbe_data));
+ break;
+ default:
+ assert(0);
+ }
+
+ }
+ cmd->dw0.adaptive_enable = gen9_avc_enable_adaptive_search[preset];
+ cmd->dw37.adaptive_enable = gen9_avc_enable_adaptive_search[preset];
+ cmd->dw0.t8x8_flag_for_inter_enable = pic_param->pic_fields.bits.transform_8x8_mode_flag;
+ cmd->dw37.t8x8_flag_for_inter_enable = pic_param->pic_fields.bits.transform_8x8_mode_flag;
+
+ cmd->dw2.max_len_sp = gen9_avc_max_len_sp[preset];
+ cmd->dw38.max_len_sp = 0;
+
+ cmd->dw3.src_access = 0;
+ cmd->dw3.ref_access = 0;
+
+ if(avc_state->ftq_enable && (generic_state->frame_type != SLICE_TYPE_I))
+ {
+ if(avc_state->ftq_override)
+ {
+ cmd->dw3.ftq_enable = avc_state->ftq_enable;
+
+ }else
+ {
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ cmd->dw3.ftq_enable = gen9_avc_max_ftq_based_skip[preset] & 0x01;
+
+ }else
+ {
+ cmd->dw3.ftq_enable = (gen9_avc_max_ftq_based_skip[preset] >> 1) & 0x01;
+ }
+ }
+ }else
+ {
+ cmd->dw3.ftq_enable = 0;
+ }
+
+ if(avc_state->disable_sub_mb_partion)
+ cmd->dw3.sub_mb_part_mask = 0x7;
+
+ if(mbenc_i_frame_dist_in_use)
+ {
+ cmd->dw2.pitch_width = generic_state->downscaled_width_4x_in_mb;
+ cmd->dw4.picture_height_minus1 = generic_state->downscaled_height_4x_in_mb - 1;
+ cmd->dw5.slice_mb_height = (avc_state->slice_height + 4 - 1)/4;
+ cmd->dw6.batch_buffer_end = 0;
+ cmd->dw31.intra_compute_type = 1;
+
+ }else
+ {
+ cmd->dw2.pitch_width = generic_state->frame_width_in_mbs;
+ cmd->dw4.picture_height_minus1 = generic_state->frame_height_in_mbs - 1;
+ cmd->dw5.slice_mb_height = (avc_state->arbitrary_num_mbs_in_slice)?generic_state->frame_height_in_mbs:avc_state->slice_height;
+
+ {
+ memcpy(&(cmd->dw8),gen9_avc_mode_mv_cost_table[slice_type_kernel[generic_state->frame_type]][qp],8*sizeof(unsigned int));
+ if((generic_state->frame_type == SLICE_TYPE_I) && avc_state->old_mode_cost_enable)
+ {
+ //cmd->dw8 = gen9_avc_old_intra_mode_cost[qp];
+ }else if(avc_state->skip_bias_adjustment_enable)
+ {
+ /* Load different MvCost for P picture when SkipBiasAdjustment is enabled
+ // No need to check for P picture as the flag is only enabled for P picture */
+ cmd->dw11.value = gen9_avc_mv_cost_p_skip_adjustment[qp];
+
+ }
+ }
+
+ table_idx = (generic_state->frame_type == SLICE_TYPE_B)?1:0;
+ memcpy(&(cmd->dw16),table_enc_search_path[table_idx][me_method],16*sizeof(unsigned int));
+ }
+ cmd->dw4.enable_fbr_bypass = avc_state->fbr_bypass_enable;
+ cmd->dw4.enable_intra_cost_scaling_for_static_frame = avc_state->sfd_enable && generic_state->hme_enabled;
+ cmd->dw4.field_parity_flag = 0;//bottom field
+ cmd->dw4.enable_cur_fld_idr = 0;//field realted
+ cmd->dw4.contrained_intra_pred_flag = pic_param->pic_fields.bits.constrained_intra_pred_flag;
+ cmd->dw4.hme_enable = generic_state->hme_enabled;
+ cmd->dw4.picture_type = slice_type_kernel[generic_state->frame_type];
+ cmd->dw4.use_actual_ref_qp_value = generic_state->hme_enabled && (gen9_avc_mr_disable_qp_check[preset] == 0);
+
+
+ cmd->dw7.intra_part_mask = pic_param->pic_fields.bits.transform_8x8_mode_flag?0:0x02;
+ cmd->dw7.src_field_polarity = 0;//field related
+
+ /*ftq_skip_threshold_lut set,dw14 /15*/
+
+ /*r5 disable NonFTQSkipThresholdLUT*/
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ cmd->dw32.skip_val = gen9_avc_skip_value_p[avc_state->block_based_skip_enable][pic_param->pic_fields.bits.transform_8x8_mode_flag][qp];
+
+ }else if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ cmd->dw32.skip_val = gen9_avc_skip_value_b[avc_state->block_based_skip_enable][pic_param->pic_fields.bits.transform_8x8_mode_flag][qp];
+
+ }
+
+ cmd->dw13.qp_prime_y = qp;
+ cmd->dw13.qp_prime_cb = qp;
+ cmd->dw13.qp_prime_cr = qp;
+ cmd->dw13.target_size_in_word = 0xff;//hardcode for brc disable
+
+
+ if((generic_state->frame_type != SLICE_TYPE_I)&& avc_state->multi_pre_enable)
+ {
+ switch(gen9_avc_multi_pred[preset])
+ {
+ case 0:
+ cmd->dw32.mult_pred_l0_disable = 128;
+ cmd->dw32.mult_pred_l1_disable = 128;
+ break;
+ case 1:
+ cmd->dw32.mult_pred_l0_disable = (generic_state->frame_type == SLICE_TYPE_P)?1:128;
+ cmd->dw32.mult_pred_l1_disable = 128;
+ break;
+ case 2:
+ cmd->dw32.mult_pred_l0_disable = (generic_state->frame_type == SLICE_TYPE_B)?1:128;
+ cmd->dw32.mult_pred_l1_disable = (generic_state->frame_type == SLICE_TYPE_B)?1:128;
+ break;
+ case 3:
+ cmd->dw32.mult_pred_l0_disable = 1;
+ cmd->dw32.mult_pred_l1_disable = (generic_state->frame_type == SLICE_TYPE_B)?1:128;
+ break;
+
+ }
+
+ }else
+ {
+ cmd->dw32.mult_pred_l0_disable = 128;
+ cmd->dw32.mult_pred_l1_disable = 128;
+ }
+
+ /*field setting for dw33 34, ignored*/
+
+ if(avc_state->adaptive_transform_decision_enable)
+ {
+ if(generic_state->frame_type != SLICE_TYPE_I)
+ {
+ cmd->dw34.enable_adaptive_tx_decision = 1;
+ }
+
+ cmd->dw58.mb_texture_threshold = 1024;
+ cmd->dw58.tx_decision_threshold = 128;
+ }
+
+
+ if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ cmd->dw34.list1_ref_id0_frm_field_parity = 0; //frame only
+ cmd->dw34.list1_ref_id0_frm_field_parity = 0;
+ cmd->dw34.b_direct_mode = slice_param->direct_spatial_mv_pred_flag;
+ }
+ cmd->dw34.b_original_bff = 0; //frame only
+ cmd->dw34.enable_mb_flatness_check_optimization = avc_state->flatness_check_enable;
+ cmd->dw34.roi_enable_flag = curbe_param->roi_enabled;
+ cmd->dw34.mad_enable_falg = avc_state->mad_enable;
+ cmd->dw34.mb_brc_enable = avc_state->mb_qp_data_enable || generic_state->mb_brc_enabled;
+ cmd->dw34.arbitray_num_mbs_per_slice = avc_state->arbitrary_num_mbs_in_slice;
+ cmd->dw34.force_non_skip_check = avc_state->mb_disable_skip_map_enable;
+
+ if(cmd->dw34.force_non_skip_check)
+ {
+ cmd->dw34.disable_enc_skip_check = avc_state->skip_check_disable;
+ }
+
+ cmd->dw36.check_all_fractional_enable = avc_state->caf_enable;
+ cmd->dw38.ref_threshold = 400;
+ cmd->dw39.hme_ref_windows_comb_threshold = (generic_state->frame_type == SLICE_TYPE_B)?gen9_avc_hme_b_combine_len[preset]:gen9_avc_hme_combine_len[preset];
+
+ /* Default:2 used for MBBRC (MB QP Surface width and height are 4x downscaled picture in MB unit * 4 bytes)
+ 0 used for MBQP data surface (MB QP Surface width and height are same as the input picture size in MB unit * 1bytes)
+ starting GEN9, BRC use split kernel, MB QP surface is same size as input picture */
+ cmd->dw47.mb_qp_read_factor = (avc_state->mb_qp_data_enable || generic_state->mb_brc_enabled)?0:2;
+
+ if(mbenc_i_frame_dist_in_use)
+ {
+ cmd->dw13.qp_prime_y = 0;
+ cmd->dw13.qp_prime_cb = 0;
+ cmd->dw13.qp_prime_cr = 0;
+ cmd->dw33.intra_16x16_nondc_penalty = 0;
+ cmd->dw33.intra_8x8_nondc_penalty = 0;
+ cmd->dw33.intra_4x4_nondc_penalty = 0;
+
+ }
+ if(cmd->dw4.use_actual_ref_qp_value)
+ {
+ cmd->dw44.actual_qp_value_for_ref_id0_list0 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,0);
+ cmd->dw44.actual_qp_value_for_ref_id1_list0 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,1);
+ cmd->dw44.actual_qp_value_for_ref_id2_list0 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,2);
+ cmd->dw44.actual_qp_value_for_ref_id3_list0 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,3);
+ cmd->dw45.actual_qp_value_for_ref_id4_list0 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,4);
+ cmd->dw45.actual_qp_value_for_ref_id5_list0 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,5);
+ cmd->dw45.actual_qp_value_for_ref_id6_list0 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,6);
+ cmd->dw45.actual_qp_value_for_ref_id7_list0 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,0,7);
+ cmd->dw46.actual_qp_value_for_ref_id0_list1 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,1,0);
+ cmd->dw46.actual_qp_value_for_ref_id1_list1 = gen9_avc_get_qp_from_ref_list(ctx,slice_param,1,1);
+ }
+
+ table_idx = slice_type_kernel[generic_state->frame_type];
+ cmd->dw46.ref_cost = gen9_avc_ref_cost[table_idx][qp];
+
+ if(generic_state->frame_type == SLICE_TYPE_I)
+ {
+ cmd->dw0.skip_mode_enable = 0;
+ cmd->dw37.skip_mode_enable = 0;
+ cmd->dw36.hme_combine_overlap = 0;
+ cmd->dw47.intra_cost_sf = 16;
+ cmd->dw34.enable_direct_bias_adjustment = 0;
+ cmd->dw34.enable_global_motion_bias_adjustment = 0;
+
+ }else if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ cmd->dw1.max_num_mvs = i965_avc_get_max_mv_per_2mb(avc_state->seq_param->level_idc)/2;
+ cmd->dw3.bme_disable_fbr = 1;
+ cmd->dw5.ref_width = gen9_avc_search_x[preset];
+ cmd->dw5.ref_height = gen9_avc_search_y[preset];
+ cmd->dw7.non_skip_zmv_added = 1;
+ cmd->dw7.non_skip_mode_added = 1;
+ cmd->dw7.skip_center_mask = 1;
+ cmd->dw47.intra_cost_sf = (avc_state->adaptive_intra_scaling_enable)?gen9_avc_adaptive_intra_scaling_factor[qp]:gen9_avc_intra_scaling_factor[qp];
+ cmd->dw47.max_vmv_r = i965_avc_get_max_mv_len(avc_state->seq_param->level_idc) * 4;//frame onlys
+ cmd->dw36.hme_combine_overlap = 1;
+ cmd->dw36.num_ref_idx_l0_minus_one = (avc_state->multi_pre_enable)?slice_param->num_ref_idx_l0_active_minus1:0;
+ cmd->dw39.ref_width = gen9_avc_search_x[preset];
+ cmd->dw39.ref_height = gen9_avc_search_y[preset];
+ cmd->dw34.enable_direct_bias_adjustment = 0;
+ cmd->dw34.enable_global_motion_bias_adjustment = avc_state->global_motion_bias_adjustment_enable;
+ if(avc_state->global_motion_bias_adjustment_enable)
+ cmd->dw59.hme_mv_cost_scaling_factor = avc_state->hme_mv_cost_scaling_factor;
+
+ }else
+ {
+ cmd->dw1.max_num_mvs = i965_avc_get_max_mv_per_2mb(avc_state->seq_param->level_idc)/2;
+ cmd->dw1.bi_weight = avc_state->bi_weight;
+ cmd->dw3.search_ctrl = 7;
+ cmd->dw3.skip_type = 1;
+ cmd->dw5.ref_width = gen9_avc_b_search_x[preset];
+ cmd->dw5.ref_height = gen9_avc_b_search_y[preset];
+ cmd->dw7.skip_center_mask = 0xff;
+ cmd->dw47.intra_cost_sf = (avc_state->adaptive_intra_scaling_enable)?gen9_avc_adaptive_intra_scaling_factor[qp]:gen9_avc_intra_scaling_factor[qp];
+ cmd->dw47.max_vmv_r = i965_avc_get_max_mv_len(avc_state->seq_param->level_idc) * 4;//frame only
+ cmd->dw36.hme_combine_overlap = 1;
+ surface_id = slice_param->RefPicList1[0].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface)
+ {
+ WARN_ONCE("Invalid backward reference frame\n");
+ return;
+ }
+ cmd->dw36.is_fwd_frame_short_term_ref = !!( slice_param->RefPicList1[0].flags & VA_PICTURE_H264_SHORT_TERM_REFERENCE);
+
+ cmd->dw36.num_ref_idx_l0_minus_one = (avc_state->multi_pre_enable)?slice_param->num_ref_idx_l0_active_minus1:0;
+ cmd->dw36.num_ref_idx_l1_minus_one = (avc_state->multi_pre_enable)?slice_param->num_ref_idx_l1_active_minus1:0;
+ cmd->dw39.ref_width = gen9_avc_b_search_x[preset];
+ cmd->dw39.ref_height = gen9_avc_b_search_y[preset];
+ cmd->dw40.dist_scale_factor_ref_id0_list0 = avc_state->dist_scale_factor_list0[0];
+ cmd->dw40.dist_scale_factor_ref_id1_list0 = avc_state->dist_scale_factor_list0[1];
+ cmd->dw41.dist_scale_factor_ref_id2_list0 = avc_state->dist_scale_factor_list0[2];
+ cmd->dw41.dist_scale_factor_ref_id3_list0 = avc_state->dist_scale_factor_list0[3];
+ cmd->dw42.dist_scale_factor_ref_id4_list0 = avc_state->dist_scale_factor_list0[4];
+ cmd->dw42.dist_scale_factor_ref_id5_list0 = avc_state->dist_scale_factor_list0[5];
+ cmd->dw43.dist_scale_factor_ref_id6_list0 = avc_state->dist_scale_factor_list0[6];
+ cmd->dw43.dist_scale_factor_ref_id7_list0 = avc_state->dist_scale_factor_list0[7];
+
+ cmd->dw34.enable_direct_bias_adjustment = avc_state->direct_bias_adjustment_enable;
+ if(cmd->dw34.enable_direct_bias_adjustment)
+ {
+ cmd->dw7.non_skip_zmv_added = 1;
+ cmd->dw7.non_skip_mode_added = 1;
+ }
+
+ cmd->dw34.enable_global_motion_bias_adjustment = avc_state->global_motion_bias_adjustment_enable;
+ if(avc_state->global_motion_bias_adjustment_enable)
+ cmd->dw59.hme_mv_cost_scaling_factor = avc_state->hme_mv_cost_scaling_factor;
+
+ }
+
+ avc_state->block_based_skip_enable = cmd->dw3.block_based_skip_enable;
+
+ if(avc_state->rolling_intra_refresh_enable)
+ {
+ /*by now disable it*/
+ cmd->dw34.widi_intra_refresh_en = avc_state->rolling_intra_refresh_enable;
+
+ }else
+ {
+ cmd->dw34.widi_intra_refresh_en = 0;
+ }
+
+ cmd->dw34.enable_per_mb_static_check = avc_state->sfd_enable && generic_state->hme_enabled;
+ cmd->dw34.enable_adaptive_search_window_size = avc_state->adaptive_search_window_enable;
+
+ /*roi set disable by now. 49-56*/
+ if(curbe_param->roi_enabled)
+ {
+ cmd->dw49.roi_1_x_left = generic_state->roi[0].left;
+ cmd->dw49.roi_1_y_top = generic_state->roi[0].top;
+ cmd->dw50.roi_1_x_right = generic_state->roi[0].right;
+ cmd->dw50.roi_1_y_bottom = generic_state->roi[0].bottom;
+
+ cmd->dw51.roi_2_x_left = generic_state->roi[1].left;
+ cmd->dw51.roi_2_y_top = generic_state->roi[1].top;
+ cmd->dw52.roi_2_x_right = generic_state->roi[1].right;
+ cmd->dw52.roi_2_y_bottom = generic_state->roi[1].bottom;
+
+ cmd->dw53.roi_3_x_left = generic_state->roi[2].left;
+ cmd->dw53.roi_3_y_top = generic_state->roi[2].top;
+ cmd->dw54.roi_3_x_right = generic_state->roi[2].right;
+ cmd->dw54.roi_3_y_bottom = generic_state->roi[2].bottom;
+
+ cmd->dw55.roi_4_x_left = generic_state->roi[3].left;
+ cmd->dw55.roi_4_y_top = generic_state->roi[3].top;
+ cmd->dw56.roi_4_x_right = generic_state->roi[3].right;
+ cmd->dw56.roi_4_y_bottom = generic_state->roi[3].bottom;
+
+ if(!generic_state->brc_enabled)
+ {
+ char tmp = 0;
+ tmp = generic_state->roi[0].value;
+ CLIP(tmp,-qp,52-qp);
+ cmd->dw57.roi_1_dqp_prime_y = tmp;
+ tmp = generic_state->roi[1].value;
+ CLIP(tmp,-qp,52-qp);
+ cmd->dw57.roi_2_dqp_prime_y = tmp;
+ tmp = generic_state->roi[2].value;
+ CLIP(tmp,-qp,52-qp);
+ cmd->dw57.roi_3_dqp_prime_y = tmp;
+ tmp = generic_state->roi[3].value;
+ CLIP(tmp,-qp,52-qp);
+ cmd->dw57.roi_4_dqp_prime_y = tmp;
+ }else
+ {
+ cmd->dw34.roi_enable_flag = 0;
+ }
+ }
+
+ cmd->dw64.mb_data_surf_index = GEN9_AVC_MBENC_MFC_AVC_PAK_OBJ_INDEX;
+ cmd->dw65.mv_data_surf_index = GEN9_AVC_MBENC_IND_MV_DATA_INDEX;
+ cmd->dw66.i_dist_surf_index = GEN9_AVC_MBENC_BRC_DISTORTION_INDEX;
+ cmd->dw67.src_y_surf_index = GEN9_AVC_MBENC_CURR_Y_INDEX;
+ cmd->dw68.mb_specific_data_surf_index = GEN9_AVC_MBENC_MB_SPECIFIC_DATA_INDEX;
+ cmd->dw69.aux_vme_out_surf_index = GEN9_AVC_MBENC_AUX_VME_OUT_INDEX;
+ cmd->dw70.curr_ref_pic_sel_surf_index = GEN9_AVC_MBENC_REFPICSELECT_L0_INDEX;
+ cmd->dw71.hme_mv_pred_fwd_bwd_surf_index = GEN9_AVC_MBENC_MV_DATA_FROM_ME_INDEX;
+ cmd->dw72.hme_dist_surf_index = GEN9_AVC_MBENC_4XME_DISTORTION_INDEX;
+ cmd->dw73.slice_map_surf_index = GEN9_AVC_MBENC_SLICEMAP_DATA_INDEX;
+ cmd->dw74.fwd_frm_mb_data_surf_index = GEN9_AVC_MBENC_FWD_MB_DATA_INDEX;
+ cmd->dw75.fwd_frm_mv_surf_index = GEN9_AVC_MBENC_FWD_MV_DATA_INDEX;
+ cmd->dw76.mb_qp_buffer = GEN9_AVC_MBENC_MBQP_INDEX;
+ cmd->dw77.mb_brc_lut = GEN9_AVC_MBENC_MBBRC_CONST_DATA_INDEX;
+ cmd->dw78.vme_inter_prediction_surf_index = GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_INDEX;
+ cmd->dw79.vme_inter_prediction_mr_surf_index = GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_INDEX;
+ cmd->dw80.mb_stats_surf_index = GEN9_AVC_MBENC_MB_STATS_INDEX;
+ cmd->dw81.mad_surf_index = GEN9_AVC_MBENC_MAD_DATA_INDEX;
+ cmd->dw82.force_non_skip_mb_map_surface = GEN9_AVC_MBENC_FORCE_NONSKIP_MB_MAP_INDEX;
+ cmd->dw83.widi_wa_surf_index = GEN9_AVC_MBENC_WIDI_WA_INDEX;
+ cmd->dw84.brc_curbe_surf_index = GEN9_AVC_MBENC_BRC_CURBE_DATA_INDEX;
+ cmd->dw85.static_detection_cost_table_index = GEN9_AVC_MBENC_SFD_COST_TABLE_INDEX;
+
+ i965_gpe_context_unmap_curbe(gpe_context);
+
+ return;
+}
+
+static void
+gen9_avc_send_surface_mbenc(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param_mbenc)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ struct object_surface *obj_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+ struct i965_gpe_resource *gpe_resource;
+ struct mbenc_param * param = (struct mbenc_param *)param_mbenc ;
+ VASurfaceID surface_id;
+ unsigned int mbenc_i_frame_dist_in_use = param->mbenc_i_frame_dist_in_use;
+ unsigned int size = 0;
+ unsigned int w_mb = generic_state->frame_width_in_mbs;
+ unsigned int h_mb = generic_state->frame_height_in_mbs;
+ int i = 0;
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+
+ obj_surface = encode_state->reconstructed_object;
+
+ if (!obj_surface || !obj_surface->private_data)
+ return;
+ avc_priv_surface = obj_surface->private_data;
+
+ /*pak obj command buffer output*/
+ size = w_mb * h_mb * 16 * 4;
+ gpe_resource = &avc_priv_surface->res_mb_code_surface;
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_resource,
+ 0,
+ size / 4,
+ 0,
+ GEN9_AVC_MBENC_MFC_AVC_PAK_OBJ_INDEX);
+
+ /*mv data buffer output*/
+ size = w_mb * h_mb * 32 * 4;
+ gpe_resource = &avc_priv_surface->res_mv_data_surface;
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_resource,
+ 0,
+ size / 4,
+ 0,
+ GEN9_AVC_MBENC_IND_MV_DATA_INDEX);
+
+ /*input current YUV surface, current input Y/UV object*/
+ if(mbenc_i_frame_dist_in_use)
+ {
+ obj_surface = encode_state->reconstructed_object;
+ if (!obj_surface || !obj_surface->private_data)
+ return;
+ avc_priv_surface = obj_surface->private_data;
+ obj_surface = avc_priv_surface->scaled_4x_surface_obj;
+ }else
+ {
+ obj_surface = encode_state->input_yuv_object;
+ }
+ gen9_add_2d_gpe_surface(ctx,
+ gpe_context,
+ obj_surface,
+ 0,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_CURR_Y_INDEX);
+
+ gen9_add_2d_gpe_surface(ctx,
+ gpe_context,
+ obj_surface,
+ 1,
+ 1,
+ I965_SURFACEFORMAT_R16_UINT,
+ GEN9_AVC_MBENC_CURR_UV_INDEX);
+
+ if(generic_state->hme_enabled)
+ {
+ /*memv input 4x*/
+ gpe_resource = &(avc_ctx->s4x_memv_data_buffer);
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_MV_DATA_FROM_ME_INDEX);
+ /* memv distortion input*/
+ gpe_resource = &(avc_ctx->s4x_memv_distortion_buffer);
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_4XME_DISTORTION_INDEX);
+ }
+
+ /*mbbrc const data_buffer*/
+ if(param->mb_const_data_buffer_in_use)
+ {
+ size = 16 * 52 * sizeof(unsigned int);
+ gpe_resource = &avc_ctx->res_mbbrc_const_data_buffer;
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_resource,
+ 0,
+ size / 4,
+ 0,
+ GEN9_AVC_MBENC_MBBRC_CONST_DATA_INDEX);
+
+ }
+
+ /*mb qp data_buffer*/
+ if(param->mb_qp_buffer_in_use)
+ {
+ if(avc_state->mb_qp_data_enable)
+ gpe_resource = &(avc_ctx->res_mb_qp_data_surface);
+ else
+ gpe_resource = &(avc_ctx->res_mbbrc_mb_qp_data_surface);
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_MBQP_INDEX);
+ }
+
+ /*input current YUV surface, current input Y/UV object*/
+ if(mbenc_i_frame_dist_in_use)
+ {
+ obj_surface = encode_state->reconstructed_object;
+ if (!obj_surface || !obj_surface->private_data)
+ return;
+ avc_priv_surface = obj_surface->private_data;
+ obj_surface = avc_priv_surface->scaled_4x_surface_obj;
+ }else
+ {
+ obj_surface = encode_state->input_yuv_object;
+ }
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ obj_surface,
+ GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_INDEX);
+ /*input ref YUV surface*/
+ for(i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList0[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ break;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ obj_surface,
+ GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_INDEX+i*2 + 1);
+ }
+ /*input current YUV surface, current input Y/UV object*/
+ if(mbenc_i_frame_dist_in_use)
+ {
+ obj_surface = encode_state->reconstructed_object;
+ if (!obj_surface || !obj_surface->private_data)
+ return;
+ avc_priv_surface = obj_surface->private_data;
+ obj_surface = avc_priv_surface->scaled_4x_surface_obj;
+ }else
+ {
+ obj_surface = encode_state->input_yuv_object;
+ }
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ obj_surface,
+ GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_INDEX);
+
+ for(i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
+ {
+ if(i > 0) break;// only one ref supported here for B frame
+ surface_id = slice_param->RefPicList1[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ break;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ obj_surface,
+ GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_INDEX+i*2 + 1);
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ obj_surface,
+ GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_INDEX+i*2 + 2);
+ if(i == 0)
+ {
+ avc_priv_surface = obj_surface->private_data;
+ /*pak obj command buffer output(mb code)*/
+ size = w_mb * h_mb * 16 * 4;
+ gpe_resource = &avc_priv_surface->res_mb_code_surface;
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_resource,
+ 0,
+ size / 4,
+ 0,
+ GEN9_AVC_MBENC_FWD_MB_DATA_INDEX);
+
+ /*mv data buffer output*/
+ size = w_mb * h_mb * 32 * 4;
+ gpe_resource = &avc_priv_surface->res_mv_data_surface;
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_resource,
+ 0,
+ size / 4,
+ 0,
+ GEN9_AVC_MBENC_FWD_MV_DATA_INDEX);
+
+ }
+
+ if( i < INTEL_AVC_MAX_BWD_REF_NUM)
+ {
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ obj_surface,
+ GEN9_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_INDEX+i*2 + 1 + INTEL_AVC_MAX_BWD_REF_NUM);
+ }
+
+ }
+
+ /* BRC distortion data buffer for I frame*/
+ if(mbenc_i_frame_dist_in_use)
+ {
+ gpe_resource = &(avc_ctx->res_brc_dist_data_surface);
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_BRC_DISTORTION_INDEX);
+ }
+
+ /* as ref frame ,update later RefPicSelect of Current Picture*/
+ obj_surface = encode_state->reconstructed_object;
+ avc_priv_surface = obj_surface->private_data;
+ if(avc_state->ref_pic_select_list_supported && avc_priv_surface->is_as_ref)
+ {
+ gpe_resource = &(avc_priv_surface->res_ref_pic_select_surface);
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_REFPICSELECT_L0_INDEX);
+
+ }
+
+ if(param->mb_vproc_stats_enable)
+ {
+ /*mb status buffer input*/
+ size = w_mb * h_mb * 16 * 4;
+ gpe_resource = &(avc_ctx->res_mb_status_buffer);
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_resource,
+ 0,
+ size / 4,
+ 0,
+ GEN9_AVC_MBENC_MB_STATS_INDEX);
+
+ }else if(avc_state->flatness_check_enable)
+ {
+
+ gpe_resource = &(avc_ctx->res_flatness_check_surface);
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_MB_STATS_INDEX);
+ }
+
+ if(param->mad_enable)
+ {
+ /*mad buffer input*/
+ size = 4;
+ gpe_resource = &(avc_ctx->res_mad_data_buffer);
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_resource,
+ 0,
+ size / 4,
+ 0,
+ GEN9_AVC_MBENC_MAD_DATA_INDEX);
+ i965_zero_gpe_resource(gpe_resource);
+ }
+
+ /*brc updated mbenc curbe data buffer,it is ignored*/
+
+ /*artitratry num mbs in slice*/
+ if(avc_state->arbitrary_num_mbs_in_slice)
+ {
+ /*slice surface input*/
+ gpe_resource = &(avc_ctx->res_mbenc_slice_map_surface);
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_SLICEMAP_DATA_INDEX);
+ }
+
+ /* BRC distortion data buffer for I frame */
+ if(!mbenc_i_frame_dist_in_use)
+ {
+ if(avc_state->mb_disable_skip_map_enable)
+ {
+ gpe_resource = &(avc_ctx->res_mb_disable_skip_map_surface);
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_FORCE_NONSKIP_MB_MAP_INDEX);
+ }
+
+ if(avc_state->sfd_enable && generic_state->hme_enabled)
+ {
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ gpe_resource = &(avc_ctx->res_sfd_cost_table_p_frame_buffer);
+
+ }else if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ gpe_resource = &(avc_ctx->res_sfd_cost_table_b_frame_buffer);
+ }
+
+ if(generic_state->frame_type != SLICE_TYPE_I)
+ {
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_MBENC_SFD_COST_TABLE_INDEX);
+ }
+ }
+ }
+
+ return;
+}
+
+static VAStatus
+gen9_avc_kernel_mbenc(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ bool i_frame_dist_in_use)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+
+ struct i965_gpe_context *gpe_context;
+ struct gpe_media_object_walker_parameter media_object_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
+ unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
+ int media_function = 0;
+ int kernel_idx = 0;
+ unsigned int mb_const_data_buffer_in_use = 0;
+ unsigned int mb_qp_buffer_in_use = 0;
+ unsigned int brc_enabled = 0;
+ unsigned int roi_enable = (generic_state->num_roi > 0)?1:0;
+ unsigned int dirty_roi_enable = ((generic_state->dirty_num_roi > 0) && (generic_state->frame_type == SLICE_TYPE_P) && (0));
+ struct mbenc_param param ;
+
+ int mbenc_i_frame_dist_in_use = i_frame_dist_in_use;
+ int mad_enable = 0;
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+
+ mb_const_data_buffer_in_use =
+ generic_state->mb_brc_enabled ||
+ roi_enable ||
+ dirty_roi_enable ||
+ avc_state->mb_qp_data_enable ||
+ avc_state->rolling_intra_refresh_enable;
+ mb_qp_buffer_in_use =
+ generic_state->mb_brc_enabled ||
+ generic_state->brc_roi_enable ||
+ avc_state->mb_qp_data_enable;
+
+ if(mbenc_i_frame_dist_in_use)
+ {
+ media_function = INTEL_MEDIA_STATE_ENC_I_FRAME_DIST;
+ kernel_idx = GEN9_AVC_KERNEL_BRC_I_FRAME_DIST;
+ downscaled_width_in_mb = generic_state->downscaled_width_4x_in_mb;
+ downscaled_height_in_mb = generic_state->downscaled_height_4x_in_mb;
+ mad_enable = 0;
+ brc_enabled = 0;
+
+ gpe_context = &(avc_ctx->context_brc.gpe_contexts[kernel_idx]);
+ }else
+ {
+ switch(generic_state->kernel_mode)
+ {
+ case INTEL_ENC_KERNEL_NORMAL :
+ {
+ media_function = INTEL_MEDIA_STATE_ENC_NORMAL;
+ kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_NORMAL_I;
+ break;
+ }
+ case INTEL_ENC_KERNEL_PERFORMANCE :
+ {
+ media_function = INTEL_MEDIA_STATE_ENC_PERFORMANCE;
+ kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_PERFORMANCE_I;
+ break;
+ }
+ case INTEL_ENC_KERNEL_QUALITY :
+ {
+ media_function = INTEL_MEDIA_STATE_ENC_QUALITY;
+ kernel_idx = MBENC_KERNEL_BASE + GEN9_AVC_KERNEL_MBENC_QUALITY_I;
+ break;
+ }
+ default:
+ assert(0);
+
+ }
+
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ kernel_idx += 1;
+ }
+ else if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ kernel_idx += 2;
+ }
+
+ downscaled_width_in_mb = generic_state->frame_width_in_mbs;
+ downscaled_height_in_mb = generic_state->frame_height_in_mbs;
+ mad_enable = avc_state->mad_enable;
+ brc_enabled = generic_state->brc_enabled;
+
+ gpe_context = &(avc_ctx->context_mbenc.gpe_contexts[kernel_idx]);
+ }
+
+ memset(&param,0,sizeof(struct mbenc_param));
+
+ param.mb_const_data_buffer_in_use = mb_const_data_buffer_in_use;
+ param.mb_qp_buffer_in_use = mb_qp_buffer_in_use;
+ param.mbenc_i_frame_dist_in_use = mbenc_i_frame_dist_in_use;
+ param.mad_enable = mad_enable;
+ param.brc_enabled = brc_enabled;
+ param.roi_enabled = roi_enable;
+
+ if(avc_state->mb_status_supported)
+ {
+ param.mb_vproc_stats_enable = avc_state->flatness_check_enable || avc_state->adaptive_transform_decision_enable;
+ }
+
+ if(!avc_state->mbenc_curbe_set_in_brc_update)
+ {
+ gen8_gpe_context_init(ctx, gpe_context);
+ }
+
+ gen9_gpe_reset_binding_table(ctx, gpe_context);
+
+ if(!avc_state->mbenc_curbe_set_in_brc_update)
+ {
+ /*set curbe here*/
+ generic_ctx->pfn_set_curbe_mbenc(ctx,encode_state,gpe_context,encoder_context,&param);
+ }
+
+ /* MB brc const data buffer set up*/
+ if(mb_const_data_buffer_in_use)
+ {
+ gen9_avc_load_mb_brc_const_data(ctx,encode_state,encoder_context);
+ }
+
+ /*clear the mad buffer*/
+ if(mad_enable)
+ {
+ i965_zero_gpe_resource(&(avc_ctx->res_mad_data_buffer));
+ }
+ /*send surface*/
+ generic_ctx->pfn_send_mbenc_surface(ctx,encode_state,gpe_context,encoder_context,&param);
+
+ gen8_gpe_setup_interface_data(ctx, gpe_context);
+
+ /*walker setting*/
+ memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
+
+ kernel_walker_param.use_scoreboard = 1;
+ kernel_walker_param.resolution_x = downscaled_width_in_mb ;
+ kernel_walker_param.resolution_y = downscaled_height_in_mb ;
+ if(mbenc_i_frame_dist_in_use)
+ {
+ kernel_walker_param.no_dependency = 1;
+ }else
+ {
+ switch(generic_state->frame_type)
+ {
+ case SLICE_TYPE_I:
+ kernel_walker_param.walker_degree = WALKER_45_DEGREE;
+ break;
+ case SLICE_TYPE_P:
+ kernel_walker_param.walker_degree = WALKER_26_DEGREE;
+ break;
+ case SLICE_TYPE_B:
+ kernel_walker_param.walker_degree = WALKER_26_DEGREE;
+ if(!slice_param->direct_spatial_mv_pred_flag)
+ {
+ kernel_walker_param.walker_degree = WALKER_45_DEGREE;
+ }
+ break;
+ default:
+ assert(0);
+ }
+ kernel_walker_param.no_dependency = 0;
+ }
+
+ i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
+
+ gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
+ gpe_context,
+ media_function,
+ &media_object_walker_param);
+ return VA_STATUS_SUCCESS;
+}
+
+/*
+me kernle related function
+*/
+static void
+gen9_avc_set_curbe_me(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ gen9_avc_me_curbe_data *curbe_cmd;
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+
+ struct me_param * curbe_param = (struct me_param *)param ;
+ unsigned char use_mv_from_prev_step = 0;
+ unsigned char write_distortions = 0;
+ unsigned char qp_prime_y = 0;
+ unsigned char me_method = gen9_avc_p_me_method[generic_state->preset];
+ unsigned char seach_table_idx = 0;
+ unsigned char mv_shift_factor = 0, prev_mv_read_pos_factor = 0;
+ unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
+ unsigned int scale_factor = 0;
+
+ qp_prime_y = avc_state->pic_param->pic_init_qp + slice_param->slice_qp_delta;
+ switch(curbe_param->hme_type)
+ {
+ case INTEL_ENC_HME_4x :
+ {
+ use_mv_from_prev_step = (generic_state->b16xme_enabled)? 1:0;
+ write_distortions = 1;
+ mv_shift_factor = 2;
+ scale_factor = 4;
+ prev_mv_read_pos_factor = 0;
+ break;
+ }
+ case INTEL_ENC_HME_16x :
+ {
+ use_mv_from_prev_step = (generic_state->b32xme_enabled)? 1:0;
+ write_distortions = 0;
+ mv_shift_factor = 2;
+ scale_factor = 16;
+ prev_mv_read_pos_factor = 1;
+ break;
+ }
+ case INTEL_ENC_HME_32x :
+ {
+ use_mv_from_prev_step = 0;
+ write_distortions = 0;
+ mv_shift_factor = 1;
+ scale_factor = 32;
+ prev_mv_read_pos_factor = 0;
+ break;
+ }
+ default:
+ assert(0);
+
+ }
+ curbe_cmd = i965_gpe_context_map_curbe(gpe_context);
+
+ if (!curbe_cmd)
+ return;
+
+ downscaled_width_in_mb = ALIGN(generic_state->frame_width_in_pixel/scale_factor,16)/16;
+ downscaled_height_in_mb = ALIGN(generic_state->frame_height_in_pixel/scale_factor,16)/16;
+
+ memcpy(curbe_cmd,gen9_avc_me_curbe_init_data,sizeof(gen9_avc_me_curbe_data));
+
+ curbe_cmd->dw3.sub_pel_mode = 3;
+ if(avc_state->field_scaling_output_interleaved)
+ {
+ /*frame set to zero,field specified*/
+ curbe_cmd->dw3.src_access = 0;
+ curbe_cmd->dw3.ref_access = 0;
+ curbe_cmd->dw7.src_field_polarity = 0;
+ }
+ curbe_cmd->dw4.picture_height_minus1 = downscaled_height_in_mb - 1;
+ curbe_cmd->dw4.picture_width = downscaled_width_in_mb;
+ curbe_cmd->dw5.qp_prime_y = qp_prime_y;
+
+ curbe_cmd->dw6.use_mv_from_prev_step = use_mv_from_prev_step;
+ curbe_cmd->dw6.write_distortions = write_distortions;
+ curbe_cmd->dw6.super_combine_dist = gen9_avc_super_combine_dist[generic_state->preset];
+ curbe_cmd->dw6.max_vmvr = i965_avc_get_max_mv_len(avc_state->seq_param->level_idc) * 4;//frame only
+
+ if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ curbe_cmd->dw1.bi_weight = 32;
+ curbe_cmd->dw13.num_ref_idx_l1_minus1 = slice_param->num_ref_idx_l1_active_minus1;
+ me_method = gen9_avc_b_me_method[generic_state->preset];
+ seach_table_idx = 1;
+ }
+
+ if(generic_state->frame_type == SLICE_TYPE_P ||
+ generic_state->frame_type == SLICE_TYPE_B )
+ curbe_cmd->dw13.num_ref_idx_l0_minus1 = slice_param->num_ref_idx_l0_active_minus1;
+
+ curbe_cmd->dw13.ref_streamin_cost = 5;
+ curbe_cmd->dw13.roi_enable = 0;
+
+ curbe_cmd->dw15.prev_mv_read_pos_factor = prev_mv_read_pos_factor;
+ curbe_cmd->dw15.mv_shift_factor = mv_shift_factor;
+
+ memcpy(&curbe_cmd->dw16,table_enc_search_path[seach_table_idx][me_method],14*sizeof(int));
+
+ curbe_cmd->dw32._4x_memv_output_data_surf_index = GEN9_AVC_ME_MV_DATA_SURFACE_INDEX;
+ curbe_cmd->dw33._16x_32x_memv_input_data_surf_index = (curbe_param->hme_type == INTEL_ENC_HME_32x)? GEN9_AVC_32XME_MV_DATA_SURFACE_INDEX:GEN9_AVC_16XME_MV_DATA_SURFACE_INDEX ;
+ curbe_cmd->dw34._4x_me_output_dist_surf_index = GEN9_AVC_ME_DISTORTION_SURFACE_INDEX;
+ curbe_cmd->dw35._4x_me_output_brc_dist_surf_index = GEN9_AVC_ME_BRC_DISTORTION_INDEX;
+ curbe_cmd->dw36.vme_fwd_inter_pred_surf_index = GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX;
+ curbe_cmd->dw37.vme_bdw_inter_pred_surf_index = GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX;
+ curbe_cmd->dw38.reserved = GEN9_AVC_ME_VDENC_STREAMIN_INDEX;
+
+ i965_gpe_context_unmap_curbe(gpe_context);
+ return;
+}
+
+static void
+gen9_avc_send_surface_me(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+
+ struct object_surface *obj_surface, *input_surface;
+ struct gen9_surface_avc *avc_priv_surface;
+ struct i965_gpe_resource *gpe_resource;
+ struct me_param * curbe_param = (struct me_param *)param ;
+
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+ VASurfaceID surface_id;
+ int i = 0;
+
+ /* all scaled input surface stored in reconstructed_object*/
+ obj_surface = encode_state->reconstructed_object;
+ if (!obj_surface || !obj_surface->private_data)
+ return;
+ avc_priv_surface = obj_surface->private_data;
+
+
+ switch(curbe_param->hme_type)
+ {
+ case INTEL_ENC_HME_4x :
+ {
+ /*memv output 4x*/
+ gpe_resource = &avc_ctx->s4x_memv_data_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_ME_MV_DATA_SURFACE_INDEX);
+
+ /*memv input 16x*/
+ if(generic_state->b16xme_enabled)
+ {
+ gpe_resource = &avc_ctx->s16x_memv_data_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_16XME_MV_DATA_SURFACE_INDEX);
+ }
+ /* brc distortion output*/
+ gpe_resource = &avc_ctx->res_brc_dist_data_surface;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_ME_BRC_DISTORTION_INDEX);
+ /* memv distortion output*/
+ gpe_resource = &avc_ctx->s4x_memv_distortion_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_ME_DISTORTION_SURFACE_INDEX);
+ /*input current down scaled YUV surface*/
+ obj_surface = encode_state->reconstructed_object;
+ avc_priv_surface = obj_surface->private_data;
+ input_surface = avc_priv_surface->scaled_4x_surface_obj;
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX);
+ /*input ref scaled YUV surface*/
+ for(i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList0[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ break;
+ avc_priv_surface = obj_surface->private_data;
+
+ input_surface = avc_priv_surface->scaled_4x_surface_obj;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX+i*2 + 1);
+ }
+
+ obj_surface = encode_state->reconstructed_object;
+ avc_priv_surface = obj_surface->private_data;
+ input_surface = avc_priv_surface->scaled_4x_surface_obj;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX);
+
+ for(i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList1[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ break;
+ avc_priv_surface = obj_surface->private_data;
+
+ input_surface = avc_priv_surface->scaled_4x_surface_obj;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX+i*2 + 1);
+ }
+ break;
+
+ }
+ case INTEL_ENC_HME_16x :
+ {
+ gpe_resource = &avc_ctx->s16x_memv_data_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_ME_MV_DATA_SURFACE_INDEX);
+
+ if(generic_state->b32xme_enabled)
+ {
+ gpe_resource = &avc_ctx->s32x_memv_data_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_32XME_MV_DATA_SURFACE_INDEX);
+ }
+
+ obj_surface = encode_state->reconstructed_object;
+ avc_priv_surface = obj_surface->private_data;
+ input_surface = avc_priv_surface->scaled_16x_surface_obj;
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX);
+
+ for(i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList0[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ break;
+ avc_priv_surface = obj_surface->private_data;
+
+ input_surface = avc_priv_surface->scaled_16x_surface_obj;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX+i*2 + 1);
+ }
+
+ obj_surface = encode_state->reconstructed_object;
+ avc_priv_surface = obj_surface->private_data;
+ input_surface = avc_priv_surface->scaled_16x_surface_obj;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX);
+
+ for(i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList1[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ break;
+ avc_priv_surface = obj_surface->private_data;
+
+ input_surface = avc_priv_surface->scaled_16x_surface_obj;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX+i*2 + 1);
+ }
+ break;
+ }
+ case INTEL_ENC_HME_32x :
+ {
+ gpe_resource = &avc_ctx->s32x_memv_data_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_ME_MV_DATA_SURFACE_INDEX);
+
+ obj_surface = encode_state->reconstructed_object;
+ avc_priv_surface = obj_surface->private_data;
+ input_surface = avc_priv_surface->scaled_32x_surface_obj;
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX);
+
+ for(i = 0; i < slice_param->num_ref_idx_l0_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList0[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ break;
+ avc_priv_surface = obj_surface->private_data;
+
+ input_surface = avc_priv_surface->scaled_32x_surface_obj;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_FWD_REF_INDEX+i*2 + 1);
+ }
+
+ obj_surface = encode_state->reconstructed_object;
+ avc_priv_surface = obj_surface->private_data;
+ input_surface = avc_priv_surface->scaled_32x_surface_obj;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX);
+
+ for(i = 0; i < slice_param->num_ref_idx_l1_active_minus1 + 1; i++)
+ {
+ surface_id = slice_param->RefPicList1[i].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ break;
+ avc_priv_surface = obj_surface->private_data;
+
+ input_surface = avc_priv_surface->scaled_32x_surface_obj;
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ input_surface,
+ GEN9_AVC_ME_CURR_FOR_BWD_REF_INDEX+i*2 + 1);
+ }
+ break;
+ }
+ default:
+ assert(0);
+
+ }
+}
+
+static VAStatus
+gen9_avc_kernel_me(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int hme_type)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+
+ struct i965_gpe_context *gpe_context;
+ struct gpe_media_object_walker_parameter media_object_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
+ unsigned int downscaled_width_in_mb, downscaled_height_in_mb;
+ int media_function = 0;
+ int kernel_idx = 0;
+ struct me_param param ;
+ unsigned int scale_factor = 0;
+
+ switch(hme_type)
+ {
+ case INTEL_ENC_HME_4x :
+ {
+ media_function = INTEL_MEDIA_STATE_4X_ME;
+ scale_factor = 4;
+ break;
+ }
+ case INTEL_ENC_HME_16x :
+ {
+ media_function = INTEL_MEDIA_STATE_16X_ME;
+ scale_factor = 16;
+ break;
+ }
+ case INTEL_ENC_HME_32x :
+ {
+ media_function = INTEL_MEDIA_STATE_32X_ME;
+ scale_factor = 32;
+ break;
+ }
+ default:
+ assert(0);
+
+ }
+
+ downscaled_width_in_mb = ALIGN(generic_state->frame_width_in_pixel/scale_factor,16)/16;
+ downscaled_height_in_mb = ALIGN(generic_state->frame_height_in_pixel/scale_factor,16)/16;
+
+ /* I frame should not come here.*/
+ kernel_idx = (generic_state->frame_type == SLICE_TYPE_P)? GEN9_AVC_KERNEL_ME_P_IDX : GEN9_AVC_KERNEL_ME_B_IDX;
+ gpe_context = &(avc_ctx->context_me.gpe_contexts[kernel_idx]);
+
+ gen8_gpe_context_init(ctx, gpe_context);
+ gen9_gpe_reset_binding_table(ctx, gpe_context);
+
+ /*set curbe*/
+ memset(&param,0,sizeof(param));
+ param.hme_type = hme_type;
+ generic_ctx->pfn_set_curbe_me(ctx,encode_state,gpe_context,encoder_context,&param);
+
+ /*send surface*/
+ generic_ctx->pfn_send_me_surface(ctx,encode_state,gpe_context,encoder_context,&param);
+
+ gen8_gpe_setup_interface_data(ctx, gpe_context);
+
+ memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
+ /* the scaling is based on 8x8 blk level */
+ kernel_walker_param.resolution_x = downscaled_width_in_mb ;
+ kernel_walker_param.resolution_y = downscaled_height_in_mb ;
+ kernel_walker_param.no_dependency = 1;
+
+ i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
+
+ gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
+ gpe_context,
+ media_function,
+ &media_object_walker_param);
+
+ return VA_STATUS_SUCCESS;
+}
+
+/*
+wp related function
+*/
+static void
+gen9_avc_set_curbe_wp(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ gen9_avc_wp_curbe_data *cmd;
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+ struct wp_param * curbe_param = (struct wp_param *)param;
+
+ cmd = i965_gpe_context_map_curbe(gpe_context);
+
+ if (!cmd)
+ return;
+ memset(cmd,0,sizeof(gen9_avc_wp_curbe_data));
+ if(curbe_param->ref_list_idx)
+ {
+ cmd->dw0.default_weight = slice_param->luma_weight_l1[0];
+ cmd->dw0.default_offset = slice_param->luma_offset_l1[0];
+ }else
+ {
+ cmd->dw0.default_weight = slice_param->luma_weight_l0[0];
+ cmd->dw0.default_offset = slice_param->luma_offset_l0[0];
+ }
+
+ cmd->dw49.input_surface = GEN9_AVC_WP_INPUT_REF_SURFACE_INDEX;
+ cmd->dw50.output_surface = GEN9_AVC_WP_OUTPUT_SCALED_SURFACE_INDEX;
+
+ i965_gpe_context_unmap_curbe(gpe_context);
+
+}
+
+static void
+gen9_avc_send_surface_wp(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ struct wp_param * curbe_param = (struct wp_param *)param;
+ struct object_surface *obj_surface;
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+ VASurfaceID surface_id;
+
+ if(curbe_param->ref_list_idx)
+ {
+ surface_id = slice_param->RefPicList1[0].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ avc_state->weighted_ref_l1_enable = 0;
+ else
+ avc_state->weighted_ref_l1_enable = 1;
+ }else
+ {
+ surface_id = slice_param->RefPicList0[0].picture_id;
+ obj_surface = SURFACE(surface_id);
+ if (!obj_surface || !obj_surface->private_data)
+ avc_state->weighted_ref_l0_enable = 0;
+ else
+ avc_state->weighted_ref_l0_enable = 1;
+ }
+ if(!obj_surface)
+ obj_surface = encode_state->reference_objects[0];
+
+
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ obj_surface,
+ GEN9_AVC_WP_INPUT_REF_SURFACE_INDEX);
+
+ obj_surface = avc_ctx->wp_output_pic_select_surface_obj[curbe_param->ref_list_idx];
+ gen9_add_adv_gpe_surface(ctx, gpe_context,
+ obj_surface,
+ GEN9_AVC_WP_OUTPUT_SCALED_SURFACE_INDEX);
+}
+
+
+static VAStatus
+gen9_avc_kernel_wp(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ unsigned int list1_in_use)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
+
+ struct i965_gpe_context *gpe_context;
+ struct gpe_media_object_walker_parameter media_object_walker_param;
+ struct gpe_encoder_kernel_walker_parameter kernel_walker_param;
+ int media_function = INTEL_MEDIA_STATE_ENC_WP;
+ struct wp_param param;
+
+ gpe_context = &(avc_ctx->context_wp.gpe_contexts);
+
+ gen8_gpe_context_init(ctx, gpe_context);
+ gen9_gpe_reset_binding_table(ctx, gpe_context);
+
+ memset(&param,0,sizeof(param));
+ param.ref_list_idx = (list1_in_use == 1)? 1: 0;
+ /*set curbe*/
+ generic_ctx->pfn_set_curbe_wp(ctx,encode_state,gpe_context,encoder_context,&param);
+
+ /*send surface*/
+ generic_ctx->pfn_send_wp_surface(ctx,encode_state,gpe_context,encoder_context,&param);
+
+ gen8_gpe_setup_interface_data(ctx, gpe_context);
+
+ memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
+ /* the scaling is based on 8x8 blk level */
+ kernel_walker_param.resolution_x = generic_state->frame_width_in_mbs;
+ kernel_walker_param.resolution_y = generic_state->frame_height_in_mbs;
+ kernel_walker_param.no_dependency = 1;
+
+ i965_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
+
+ gen9_avc_run_kernel_media_object_walker(ctx, encoder_context,
+ gpe_context,
+ media_function,
+ &media_object_walker_param);
+
+ return VA_STATUS_SUCCESS;
+}
+
+
+/*
+sfd related function
+*/
+static void
+gen9_avc_set_curbe_sfd(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ gen9_avc_sfd_curbe_data *cmd;
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+
+ cmd = i965_gpe_context_map_curbe(gpe_context);
+
+ if (!cmd)
+ return;
+ memset(cmd,0,sizeof(gen9_avc_sfd_curbe_data));
+
+ cmd->dw0.enable_intra_cost_scaling_for_static_frame = 1 ;
+ cmd->dw0.enable_adaptive_mv_stream_in = 0 ; //vdenc
+ cmd->dw0.stream_in_type = 7 ; //vdenc
+ cmd->dw0.slice_type = slice_type_kernel[generic_state->frame_type] ;
+ cmd->dw0.brc_mode_enable = generic_state->brc_enabled ;
+ cmd->dw0.vdenc_mode_disable = 1 ;
+
+ cmd->dw1.hme_stream_in_ref_cost = 5 ;
+ cmd->dw1.num_of_refs = slice_param->num_ref_idx_l0_active_minus1 ;//vdenc
+ cmd->dw1.qp_value = avc_state->pic_param->pic_init_qp + slice_param->slice_qp_delta ;
+
+ cmd->dw2.frame_width_in_mbs = generic_state->frame_width_in_mbs ;
+ cmd->dw2.frame_height_in_mbs = generic_state->frame_height_in_mbs ;
+
+ cmd->dw3.large_mv_threshold = 128 ;
+ cmd->dw4.total_large_mv_threshold = (generic_state->frame_width_in_mbs * generic_state->frame_height_in_mbs)/100 ;
+ cmd->dw5.zmv_threshold = 4 ;
+ cmd->dw6.total_zmv_threshold = (generic_state->frame_width_in_mbs * generic_state->frame_height_in_mbs * avc_state->zero_mv_threshold)/100 ; // zero_mv_threshold = 60;
+ cmd->dw7.min_dist_threshold = 10 ;
+
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ memcpy(cmd->cost_table,gen9_avc_sfd_cost_table_p_frame,52* sizeof(unsigned char));
+
+ }else if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ memcpy(cmd->cost_table,gen9_avc_sfd_cost_table_b_frame,52* sizeof(unsigned char));
+ }
+
+ cmd->dw21.actual_width_in_mb = cmd->dw2.frame_width_in_mbs ;
+ cmd->dw21.actual_height_in_mb = cmd->dw2.frame_height_in_mbs ;
+ cmd->dw24.vdenc_input_image_state_index = GEN9_AVC_SFD_VDENC_INPUT_IMAGE_STATE_INDEX ;
+ cmd->dw26.mv_data_surface_index = GEN9_AVC_SFD_MV_DATA_SURFACE_INDEX ;
+ cmd->dw27.inter_distortion_surface_index = GEN9_AVC_SFD_INTER_DISTORTION_SURFACE_INDEX ;
+ cmd->dw28.output_data_surface_index = GEN9_AVC_SFD_OUTPUT_DATA_SURFACE_INDEX ;
+ cmd->dw29.vdenc_output_image_state_index = GEN9_AVC_SFD_VDENC_OUTPUT_IMAGE_STATE_INDEX ;
+
+ i965_gpe_context_unmap_curbe(gpe_context);
+
+}
+
+static void
+gen9_avc_send_surface_sfd(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct i965_gpe_resource *gpe_resource;
+ int size = 0;
+
+ /*HME mv data surface memv output 4x*/
+ gpe_resource = &avc_ctx->s4x_memv_data_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_SFD_MV_DATA_SURFACE_INDEX);
+
+ /* memv distortion */
+ gpe_resource = &avc_ctx->s4x_memv_distortion_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_SFD_INTER_DISTORTION_SURFACE_INDEX);
+ /*buffer output*/
+ size = 32 * 4 *4;
+ gpe_resource = &avc_ctx->res_sfd_output_buffer;
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_resource,
+ 0,
+ size / 4,
+ 0,
+ GEN9_AVC_SFD_OUTPUT_DATA_SURFACE_INDEX);
+
+}
+
+static VAStatus
+gen9_avc_kernel_sfd(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
+
+ struct i965_gpe_context *gpe_context;
+ struct gpe_media_object_parameter media_object_param;
+ struct gpe_media_object_inline_data media_object_inline_data;
+ int media_function = INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION;
+ gpe_context = &(avc_ctx->context_sfd.gpe_contexts);
+
+ gen8_gpe_context_init(ctx, gpe_context);
+ gen9_gpe_reset_binding_table(ctx, gpe_context);
+
+ /*set curbe*/
+ generic_ctx->pfn_set_curbe_sfd(ctx,encode_state,gpe_context,encoder_context,NULL);
+
+ /*send surface*/
+ generic_ctx->pfn_send_sfd_surface(ctx,encode_state,gpe_context,encoder_context,NULL);
+
+ gen8_gpe_setup_interface_data(ctx, gpe_context);
+
+ memset(&media_object_param, 0, sizeof(media_object_param));
+ memset(&media_object_inline_data, 0, sizeof(media_object_inline_data));
+ media_object_param.pinline_data = &media_object_inline_data;
+ media_object_param.inline_size = sizeof(media_object_inline_data);
+
+ gen9_avc_run_kernel_media_object(ctx, encoder_context,
+ gpe_context,
+ media_function,
+ &media_object_param);
+
+ return VA_STATUS_SUCCESS;
+}
+
+/*
+kernel related function:init/destroy etc
+*/
+static void
+gen9_avc_kernel_init_scaling(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_scaling_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+
+ /* 4x scaling kernel*/
+ kernel_param.curbe_size = sizeof(gen9_avc_scaling4x_curbe_data);
+ kernel_param.inline_data_size = sizeof(gen9_avc_scaling4x_curbe_data);
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ gpe_context = &kernel_context->gpe_contexts[GEN9_AVC_KERNEL_SCALING_4X_IDX];
+ gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_SCALING4X,
+ 0,
+ &common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+ &common_kernel,
+ 1);
+
+ /*2x scaling kernel*/
+ kernel_param.curbe_size = sizeof(gen9_avc_scaling2x_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ gpe_context = &kernel_context->gpe_contexts[GEN9_AVC_KERNEL_SCALING_2X_IDX];
+ gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_SCALING2X,
+ 0,
+ &common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+ &common_kernel,
+ 1);
+
+}
+
+static void
+gen9_avc_kernel_init_me(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_me_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+ int i = 0;
+
+ kernel_param.curbe_size = sizeof(gen9_avc_me_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ for (i = 0; i < 2; i++) {
+ gpe_context = &kernel_context->gpe_contexts[i];
+ gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_ME,
+ i,
+ &common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+ &common_kernel,
+ 1);
+ }
+
+}
+
+static void
+gen9_avc_kernel_init_mbenc(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_mbenc_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+ int i = 0;
+
+ kernel_param.curbe_size = sizeof(gen9_avc_mbenc_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ for (i = 0; i < NUM_GEN9_AVC_KERNEL_MBENC ; i++) {
+ gpe_context = &kernel_context->gpe_contexts[i];
+ gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_MBENC,
+ i,
+ &common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+ &common_kernel,
+ 1);
+ }
+
+}
+
+static void
+gen9_avc_kernel_init_brc(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_brc_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+ int i = 0;
+
+ static const int brc_curbe_size[NUM_GEN9_AVC_KERNEL_BRC] = {
+ (sizeof(gen9_avc_brc_init_reset_curbe_data)),
+ (sizeof(gen9_avc_frame_brc_update_curbe_data)),
+ (sizeof(gen9_avc_brc_init_reset_curbe_data)),
+ (sizeof(gen9_avc_mbenc_curbe_data)),
+ 0,
+ (sizeof(gen9_avc_mb_brc_curbe_data))
+ };
+
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ for (i = 0; i < NUM_GEN9_AVC_KERNEL_BRC; i++) {
+ kernel_param.curbe_size = brc_curbe_size[i];
+ gpe_context = &kernel_context->gpe_contexts[i];
+ gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_BRC,
+ i,
+ &common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+ &common_kernel,
+ 1);
+ }
+
+}
+
+static void
+gen9_avc_kernel_init_wp(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_wp_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+
+ kernel_param.curbe_size = sizeof(gen9_avc_wp_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ gpe_context = &kernel_context->gpe_contexts;
+ gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_WP,
+ 0,
+ &common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+ &common_kernel,
+ 1);
+
+}
+
+static void
+gen9_avc_kernel_init_sfd(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_sfd_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+
+ kernel_param.curbe_size = sizeof(gen9_avc_sfd_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ gpe_context = &kernel_context->gpe_contexts;
+ gen9_init_gpe_context_avc(ctx, gpe_context, &kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context, &scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void *)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_SFD,
+ 0,
+ &common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+ &common_kernel,
+ 1);
+
+}
+
+static void
+gen9_avc_kernel_destroy(struct encoder_vme_mfc_context * vme_context)
+{
+
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+
+ int i = 0;
+
+ gen9_avc_free_resources(vme_context);
+
+ for(i = 0; i < NUM_GEN9_AVC_KERNEL_SCALING; i++)
+ gen8_gpe_context_destroy(&avc_ctx->context_scaling.gpe_contexts[i]);
+
+ for(i = 0; i < NUM_GEN9_AVC_KERNEL_BRC; i++)
+ gen8_gpe_context_destroy(&avc_ctx->context_brc.gpe_contexts[i]);
+
+ for(i = 0; i < NUM_GEN9_AVC_KERNEL_ME; i++)
+ gen8_gpe_context_destroy(&avc_ctx->context_me.gpe_contexts[i]);
+
+ for(i = 0; i < NUM_GEN9_AVC_KERNEL_MBENC; i++)
+ gen8_gpe_context_destroy(&avc_ctx->context_mbenc.gpe_contexts[i]);
+
+ gen8_gpe_context_destroy(&avc_ctx->context_wp.gpe_contexts);
+
+ gen8_gpe_context_destroy(&avc_ctx->context_sfd.gpe_contexts);
+
+}
+
+/*
+vme pipeline
+*/
+static void
+gen9_avc_update_parameters(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ VAEncSequenceParameterBufferH264 *seq_param;
+ VAEncPictureParameterBufferH264 *pic_param ;
+ VAEncSliceParameterBufferH264 * slice_param;
+ int i,j;
+ unsigned int preset = generic_state->preset;
+
+ /* seq/pic/slice parameter setting */
+ generic_state->b16xme_supported = gen9_avc_super_hme[preset];
+ generic_state->b32xme_supported = gen9_avc_ultra_hme[preset];
+
+ avc_state->seq_param = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ avc_state->pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+
+
+ avc_state->enable_avc_ildb = 0;
+ avc_state->slice_num = 0;
+ for (j = 0; j < encode_state->num_slice_params_ext && avc_state->enable_avc_ildb == 0; j++) {
+ assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer);
+ slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
+
+ for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) {
+ assert((slice_param->slice_type == SLICE_TYPE_I) ||
+ (slice_param->slice_type == SLICE_TYPE_SI) ||
+ (slice_param->slice_type == SLICE_TYPE_P) ||
+ (slice_param->slice_type == SLICE_TYPE_SP) ||
+ (slice_param->slice_type == SLICE_TYPE_B));
+
+ if (slice_param->disable_deblocking_filter_idc != 1) {
+ avc_state->enable_avc_ildb = 1;
+ }
+
+ avc_state->slice_param[i] = slice_param;
+ slice_param++;
+ avc_state->slice_num++;
+ }
+ }
+
+ /* how many slices support by now? 1 slice or multi slices, but row slice.not slice group. */
+ seq_param = avc_state->seq_param;
+ pic_param = avc_state->pic_param;
+ slice_param = avc_state->slice_param[0];
+
+ generic_state->frame_type = avc_state->slice_param[0]->slice_type;
+
+ if (slice_param->slice_type == SLICE_TYPE_I ||
+ slice_param->slice_type == SLICE_TYPE_SI)
+ generic_state->frame_type = SLICE_TYPE_I;
+ else if(slice_param->slice_type == SLICE_TYPE_P)
+ generic_state->frame_type = SLICE_TYPE_P;
+ else if(slice_param->slice_type == SLICE_TYPE_B)
+ generic_state->frame_type = SLICE_TYPE_B;
+ if (profile == VAProfileH264High)
+ avc_state->transform_8x8_mode_enable = !!pic_param->pic_fields.bits.transform_8x8_mode_flag;
+ else
+ avc_state->transform_8x8_mode_enable = 0;
+
+ /* rc init*/
+ if(generic_state->brc_enabled &&(!generic_state->brc_inited || generic_state->brc_need_reset ))
+ {
+ generic_state->target_bit_rate = ALIGN(seq_param->bits_per_second, 1000) / 1000;
+ generic_state->init_vbv_buffer_fullness_in_bit = seq_param->bits_per_second;
+ generic_state->vbv_buffer_size_in_bit = (uint64_t)seq_param->bits_per_second << 1;
+ generic_state->frames_per_100s = 3000; /* 30fps */
+ }
+
+ generic_state->gop_size = seq_param->intra_period;
+ generic_state->gop_ref_distance = seq_param->ip_period;
+
+ if (generic_state->internal_rate_mode == VA_RC_CBR) {
+ generic_state->max_bit_rate = generic_state->target_bit_rate;
+ generic_state->min_bit_rate = generic_state->target_bit_rate;
+ }
+
+ if(generic_state->frame_type == SLICE_TYPE_I || generic_state->first_frame)
+ {
+ gen9_avc_update_misc_parameters(ctx, encode_state, encoder_context);
+ }
+
+ generic_state->preset = encoder_context->quality_level;
+ if(encoder_context->quality_level == INTEL_PRESET_UNKNOWN)
+ {
+ generic_state->preset = INTEL_PRESET_RT_SPEED;
+ }
+ generic_state->kernel_mode = gen9_avc_kernel_mode[generic_state->preset];
+
+ if(!generic_state->brc_inited)
+ {
+ generic_state->brc_init_reset_input_bits_per_frame = ((double)(generic_state->max_bit_rate * 1000) * 100) / generic_state->frames_per_100s;;
+ generic_state->brc_init_current_target_buf_full_in_bits = generic_state->init_vbv_buffer_fullness_in_bit;
+ generic_state->brc_init_reset_buf_size_in_bits = generic_state->vbv_buffer_size_in_bit;
+ generic_state->brc_target_size = generic_state->init_vbv_buffer_fullness_in_bit;
+ }
+
+
+ generic_state->curr_pak_pass = 0;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+
+ if (generic_state->internal_rate_mode == VA_RC_CBR ||
+ generic_state->internal_rate_mode == VA_RC_VBR)
+ generic_state->brc_enabled = 1;
+ else
+ generic_state->brc_enabled = 0;
+
+ if (generic_state->brc_enabled &&
+ (!generic_state->init_vbv_buffer_fullness_in_bit ||
+ !generic_state->vbv_buffer_size_in_bit ||
+ !generic_state->max_bit_rate ||
+ !generic_state->target_bit_rate ||
+ !generic_state->frames_per_100s))
+ {
+ WARN_ONCE("Rate control parameter is required for BRC\n");
+ generic_state->brc_enabled = 0;
+ }
+
+ if (!generic_state->brc_enabled) {
+ generic_state->target_bit_rate = 0;
+ generic_state->max_bit_rate = 0;
+ generic_state->min_bit_rate = 0;
+ generic_state->init_vbv_buffer_fullness_in_bit = 0;
+ generic_state->vbv_buffer_size_in_bit = 0;
+ generic_state->num_pak_passes = 2;
+ } else {
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ }
+
+
+ generic_state->frame_width_in_mbs = seq_param->picture_width_in_mbs;
+ generic_state->frame_height_in_mbs = seq_param->picture_height_in_mbs;
+ generic_state->frame_width_in_pixel = generic_state->frame_width_in_mbs * 16;
+ generic_state->frame_height_in_pixel = generic_state->frame_height_in_mbs * 16;
+
+ generic_state->frame_width_4x = ALIGN(generic_state->frame_width_in_pixel/4,16);
+ generic_state->frame_height_4x = ALIGN(generic_state->frame_height_in_pixel/4,16);
+ generic_state->downscaled_width_4x_in_mb = generic_state->frame_width_4x/16 ;
+ generic_state->downscaled_height_4x_in_mb = generic_state->frame_height_4x/16;
+
+ generic_state->frame_width_16x = ALIGN(generic_state->frame_width_in_pixel/16,16);
+ generic_state->frame_height_16x = ALIGN(generic_state->frame_height_in_pixel/16,16);
+ generic_state->downscaled_width_16x_in_mb = generic_state->frame_width_16x/16 ;
+ generic_state->downscaled_height_16x_in_mb = generic_state->frame_height_16x/16;
+
+ generic_state->frame_width_32x = ALIGN(generic_state->frame_width_in_pixel/32,16);
+ generic_state->frame_height_32x = ALIGN(generic_state->frame_height_in_pixel/32,16);
+ generic_state->downscaled_width_32x_in_mb = generic_state->frame_width_32x/16 ;
+ generic_state->downscaled_height_32x_in_mb = generic_state->frame_height_32x/16;
+
+ if (generic_state->hme_supported) {
+ generic_state->hme_enabled = 1;
+ } else {
+ generic_state->hme_enabled = 0;
+ }
+
+ if (generic_state->b16xme_supported) {
+ generic_state->b16xme_enabled = 1;
+ } else {
+ generic_state->b16xme_enabled = 0;
+ }
+
+ if (generic_state->b32xme_supported) {
+ generic_state->b32xme_enabled = 1;
+ } else {
+ generic_state->b32xme_enabled = 0;
+ }
+ /* disable HME/16xME if the size is too small */
+ if (generic_state->frame_width_4x <= INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT) {
+ generic_state->b32xme_supported = 0;
+ generic_state->b32xme_enabled = 0;
+ generic_state->b16xme_supported = 0;
+ generic_state->b16xme_enabled = 0;
+ generic_state->frame_width_4x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
+ generic_state->downscaled_width_4x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
+ }
+ if (generic_state->frame_height_4x <= INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT) {
+ generic_state->b32xme_supported = 0;
+ generic_state->b32xme_enabled = 0;
+ generic_state->b16xme_supported = 0;
+ generic_state->b16xme_enabled = 0;
+ generic_state->frame_height_4x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
+ generic_state->downscaled_height_4x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
+ }
+
+ if (generic_state->frame_width_16x < INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT)
+ {
+ generic_state->b32xme_supported = 0;
+ generic_state->b32xme_enabled = 0;
+ generic_state->frame_width_16x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
+ generic_state->downscaled_width_16x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
+ }
+ if (generic_state->frame_height_16x < INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT) {
+ generic_state->b32xme_supported = 0;
+ generic_state->b32xme_enabled = 0;
+ generic_state->frame_height_16x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
+ generic_state->downscaled_height_16x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
+ }
+
+ if (generic_state->frame_width_32x < INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT)
+ {
+ generic_state->frame_width_32x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
+ generic_state->downscaled_width_32x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
+ }
+ if (generic_state->frame_height_32x < INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT) {
+ generic_state->frame_height_32x = INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT;
+ generic_state->downscaled_height_32x_in_mb = WIDTH_IN_MACROBLOCKS(INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT);
+ }
+
+}
+
+static VAStatus
+gen9_avc_encode_check_parameter(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+ unsigned int rate_control_mode = encoder_context->rate_control_mode;
+ unsigned int preset = generic_state->preset;
+ VAEncPictureParameterBufferH264 *pic_param ;
+ int i = 0;
+
+ /*resolution change detection*/
+ pic_param = avc_state->pic_param;
+
+ /*avbr init*/
+ generic_state->avbr_curracy = 30;
+ generic_state->avbr_convergence = 150;
+
+ switch (rate_control_mode & 0x7f) {
+ case VA_RC_CBR:
+ generic_state->internal_rate_mode = VA_RC_CBR;
+ break;
+
+ case VA_RC_VBR:
+ generic_state->internal_rate_mode = VA_RC_VBR;
+ break;
+
+ case VA_RC_CQP:
+ default:
+ generic_state->internal_rate_mode = VA_RC_CQP;
+ break;
+ }
+
+ if (rate_control_mode != VA_RC_NONE &&
+ rate_control_mode != VA_RC_CQP) {
+ generic_state->brc_enabled = 1;
+ generic_state->brc_distortion_buffer_supported = 1;
+ generic_state->brc_constant_buffer_supported = 1;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ }
+
+ /*check brc parameter*/
+ if(generic_state->brc_enabled)
+ {
+ avc_state->mb_qp_data_enable = 0;
+ }
+
+ /*set the brc init and reset accordingly*/
+ if(generic_state->brc_need_reset &&
+ (generic_state->brc_distortion_buffer_supported == 0 ||
+ rate_control_mode == VA_RC_CQP))
+ {
+ generic_state->brc_need_reset = 0;// not support by CQP
+ }
+
+ if(generic_state->brc_need_reset && !avc_state->sfd_mb_enable)
+ {
+ avc_state->sfd_enable = 0;
+ }
+
+ if(generic_state->window_size == 0)
+ {
+ generic_state->window_size = (generic_state->frames_per_100s/100 < 60)?(generic_state->frames_per_100s/100):60;
+ }else if(generic_state->window_size > 2 * generic_state->frames_per_100s/100)
+ {
+ generic_state->window_size = (generic_state->frames_per_100s/100 < 60)?(generic_state->frames_per_100s/100):60;
+ }
+
+ if(generic_state->brc_enabled)
+ {
+ generic_state->hme_enabled = generic_state->frame_type != SLICE_TYPE_I;
+ if(avc_state->min_max_qp_enable)
+ {
+ generic_state->num_pak_passes = 1;
+ }
+ generic_state->brc_roi_enable = (rate_control_mode != VA_RC_CQP) && (generic_state->num_roi > 0);// only !CQP
+ generic_state->mb_brc_enabled = generic_state->mb_brc_enabled || generic_state->brc_roi_enable;
+ }else
+ {
+ generic_state->num_pak_passes = 2;// CQP only one pass
+ }
+
+ avc_state->mbenc_i_frame_dist_in_use = 0;
+ avc_state->mbenc_i_frame_dist_in_use = (generic_state->brc_enabled) && (generic_state->brc_distortion_buffer_supported) && (generic_state->frame_type == SLICE_TYPE_I);
+
+ /*ROI must enable mbbrc.*/
+
+ /*CAD check*/
+ if(avc_state->caf_supported)
+ {
+ switch(generic_state->frame_type)
+ {
+ case SLICE_TYPE_I:
+ break;
+ case SLICE_TYPE_P:
+ avc_state->caf_enable = gen9_avc_all_fractional[preset] & 0x01;
+ break;
+ case SLICE_TYPE_B:
+ avc_state->caf_enable = (gen9_avc_all_fractional[preset] >> 1) & 0x01;
+ break;
+ }
+
+ if(avc_state->caf_enable && avc_state->caf_disable_hd && gen9_avc_disable_all_fractional_check_for_high_res[preset])
+ {
+ if(generic_state->frame_width_in_pixel >= 1280 && generic_state->frame_height_in_pixel >= 720)
+ avc_state->caf_enable = 0;
+ }
+ }
+
+ avc_state->adaptive_transform_decision_enable &= gen9_avc_enable_adaptive_tx_decision[preset&0x7];
+
+ /* Flatness check is enabled only if scaling will be performed and CAF is enabled. here only frame */
+ if(avc_state->flatness_check_supported )
+ {
+ avc_state->flatness_check_enable = ((avc_state->caf_enable) && (generic_state->brc_enabled || generic_state->hme_supported)) ;
+ }else
+ {
+ avc_state->flatness_check_enable = 0;
+ }
+
+ /* check mb_status_supported/enbale*/
+ if(avc_state->adaptive_transform_decision_enable)
+ {
+ avc_state->mb_status_enable = 1;
+ }else
+ {
+ avc_state->mb_status_enable = 0;
+ }
+ /*slice check,all the slices use the same slice height except the last slice*/
+ avc_state->arbitrary_num_mbs_in_slice = 0;
+ for(i = 0; i < avc_state->slice_num;i++)
+ {
+ assert(avc_state->slice_param[i]->num_macroblocks % generic_state->frame_width_in_mbs == 0);
+ avc_state->slice_height = avc_state->slice_param[i]->num_macroblocks / generic_state->frame_width_in_mbs;
+ /*add it later for muli slices map*/
+ }
+
+ if(generic_state->frame_type == SLICE_TYPE_I)
+ {
+ generic_state->hme_enabled = 0;
+ generic_state->b16xme_enabled = 0;
+ generic_state->b32xme_enabled = 0;
+ }
+
+ if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ gen9_avc_get_dist_scale_factor(ctx,encode_state,encoder_context);
+ avc_state->bi_weight = gen9_avc_get_biweight(avc_state->dist_scale_factor_list0[0],pic_param->pic_fields.bits.weighted_bipred_idc);
+ }
+
+ /* Determine if SkipBiasAdjustment should be enabled for P picture 1. No B frame 2. Qp >= 22 3. CQP mode */
+ avc_state->skip_bias_adjustment_enable = avc_state->skip_bias_adjustment_supported && (generic_state->frame_type == SLICE_TYPE_P)
+ && (generic_state->gop_ref_distance == 1) && (avc_state->pic_param->pic_init_qp + avc_state->slice_param[0]->slice_qp_delta >= 22) && !generic_state->brc_enabled;
+
+ if(generic_state->kernel_mode == INTEL_ENC_KERNEL_QUALITY)
+ {
+ avc_state->tq_enable = 1;
+ avc_state->tq_rounding = 6;
+ if(generic_state->brc_enabled)
+ {
+ generic_state->mb_brc_enabled = 1;
+ }
+ }
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus
+gen9_avc_vme_gpe_kernel_prepare(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus va_status;
+ struct encoder_vme_mfc_context * vme_context = (struct encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_encoder_context * generic_ctx = (struct generic_encoder_context * )vme_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context * )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state * )vme_context->private_enc_state;
+
+ struct object_surface *obj_surface;
+ struct object_buffer *obj_buffer;
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+ struct i965_coded_buffer_segment *coded_buffer_segment;
+
+ struct gen9_surface_avc *avc_priv_surface;
+ dri_bo *bo;
+ struct avc_surface_param surface_param;
+ int i,j = 0;
+ unsigned char * pdata;
+
+ /* Setup current reco